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[openwrt/openwrt.git] / target / linux / adm5120 / files / drivers / net / adm5120sw.c
1 /*
2 * ADM5120 built in ethernet switch driver
3 *
4 * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
5 *
6 * Inspiration for this driver came from the original ADMtek 2.4
7 * driver, Copyright ADMtek Inc.
8 *
9 * NAPI extensions by Thomas Langer (Thomas.Langer@infineon.com)
10 * and Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
11 *
12 * TODO: Add support of high prio queues (currently disabled)
13 *
14 */
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/spinlock.h>
21
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25
26 #include <linux/io.h>
27 #include <linux/irq.h>
28
29 #include <asm/mipsregs.h>
30
31 #include <adm5120_info.h>
32 #include <adm5120_defs.h>
33 #include <adm5120_irq.h>
34 #include <adm5120_switch.h>
35
36 #include "adm5120sw.h"
37
38 #define DRV_NAME "adm5120-switch"
39 #define DRV_DESC "ADM5120 built-in ethernet switch driver"
40 #define DRV_VERSION "0.1.0"
41
42 MODULE_AUTHOR("Jeroen Vreeken (pe1rxq@amsat.org)");
43 MODULE_DESCRIPTION("ADM5120 ethernet switch driver");
44 MODULE_LICENSE("GPL");
45
46 /* ------------------------------------------------------------------------ */
47
48 #if 1 /*def ADM5120_SWITCH_DEBUG*/
49 #define SW_DBG(f, a...) printk(KERN_DEBUG "%s: " f, DRV_NAME , ## a)
50 #else
51 #define SW_DBG(f, a...) do {} while (0)
52 #endif
53 #define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
54 #define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
55
56 #define SWITCH_NUM_PORTS 6
57 #define ETH_CSUM_LEN 4
58
59 #define RX_MAX_PKTLEN 1550
60 #define RX_RING_SIZE 64
61
62 #define TX_RING_SIZE 32
63 #define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
64 #define TX_TIMEOUT HZ*400
65
66 #define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
67 #define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
68
69 #define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF)
70 #define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF)
71 #define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH)
72 #define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \
73 SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \
74 SWITCH_INT_CPQF | SWITCH_INT_GQF)
75
76 #define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \
77 SWITCH_INTS_ERR | SWITCH_INTS_Q | \
78 SWITCH_INT_MD | SWITCH_INT_PSC)
79
80 #define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
81 #define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF)
82
83 /* ------------------------------------------------------------------------ */
84
85 struct dma_desc {
86 __u32 buf1;
87 #define DESC_OWN (1UL << 31) /* Owned by the switch */
88 #define DESC_EOR (1UL << 28) /* End of Ring */
89 #define DESC_ADDR_MASK 0x1FFFFFF
90 #define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
91 __u32 buf2;
92 #define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
93 __u32 buflen;
94 __u32 misc;
95 /* definitions for tx/rx descriptors */
96 #define DESC_PKTLEN_SHIFT 16
97 #define DESC_PKTLEN_MASK 0x7FF
98 /* tx descriptor specific part */
99 #define DESC_CSUM (1UL << 31) /* Append checksum */
100 #define DESC_DSTPORT_SHIFT 8
101 #define DESC_DSTPORT_MASK 0x3F
102 #define DESC_VLAN_MASK 0x3F
103 /* rx descriptor specific part */
104 #define DESC_SRCPORT_SHIFT 12
105 #define DESC_SRCPORT_MASK 0x7
106 #define DESC_DA_MASK 0x3
107 #define DESC_DA_SHIFT 4
108 #define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
109 #define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
110 #define DESC_TYPE_MASK 0x3 /* mask for Packet type */
111 #define DESC_TYPE_IP 0x0 /* IP packet */
112 #define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
113 } __attribute__ ((aligned(16)));
114
115 static inline u32 desc_get_srcport(struct dma_desc *desc)
116 {
117 return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
118 }
119
120 static inline u32 desc_get_pktlen(struct dma_desc *desc)
121 {
122 return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
123 }
124
125 static inline int desc_ipcsum_fail(struct dma_desc *desc)
126 {
127 return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
128 }
129
130 /* ------------------------------------------------------------------------ */
131
132 /* default settings - unlimited TX and RX on all ports, default shaper mode */
133 static unsigned char bw_matrix[SWITCH_NUM_PORTS] = {
134 0, 0, 0, 0, 0, 0
135 };
136
137 static int adm5120_nrdevs;
138
139 static struct net_device *adm5120_devs[SWITCH_NUM_PORTS];
140 /* Lookup table port -> device */
141 static struct net_device *adm5120_port[SWITCH_NUM_PORTS];
142
143 static struct dma_desc txh_descs_v[TX_RING_SIZE] __attribute__((aligned(16)));
144 static struct dma_desc txl_descs_v[TX_RING_SIZE] __attribute__((aligned(16)));
145 static struct dma_desc rxh_descs_v[RX_RING_SIZE] __attribute__((aligned(16)));
146 static struct dma_desc rxl_descs_v[RX_RING_SIZE] __attribute__((aligned(16)));
147 static struct dma_desc *txh_descs;
148 static struct dma_desc *txl_descs;
149 static struct dma_desc *rxh_descs;
150 static struct dma_desc *rxl_descs;
151
152 static struct sk_buff *rxl_skbuff[RX_RING_SIZE];
153 static struct sk_buff *rxh_skbuff[RX_RING_SIZE];
154 static struct sk_buff *txl_skbuff[TX_RING_SIZE];
155 static struct sk_buff *txh_skbuff[TX_RING_SIZE];
156
157 static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */
158 static unsigned int cur_txl, dirty_txl;
159
160 static unsigned int sw_used;
161
162 static spinlock_t sw_lock = SPIN_LOCK_UNLOCKED;
163
164 static struct net_device sw_dev;
165
166 /* ------------------------------------------------------------------------ */
167
168 static inline u32 sw_read_reg(u32 reg)
169 {
170 return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
171 }
172
173 static inline void sw_write_reg(u32 reg, u32 val)
174 {
175 __raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
176 }
177
178 static inline void sw_int_disable(u32 mask)
179 {
180 u32 t;
181
182 t = sw_read_reg(SWITCH_REG_INT_MASK);
183 t |= mask;
184 sw_write_reg(SWITCH_REG_INT_MASK, t);
185 }
186
187 static inline void sw_int_enable(u32 mask)
188 {
189 u32 t;
190
191 t = sw_read_reg(SWITCH_REG_INT_MASK);
192 t &= ~mask;
193 sw_write_reg(SWITCH_REG_INT_MASK, t);
194 }
195
196 static inline void sw_int_ack(u32 mask)
197 {
198 sw_write_reg(SWITCH_REG_INT_STATUS, mask);
199 }
200
201 /* ------------------------------------------------------------------------ */
202
203 static void sw_dump_desc(char *label, struct dma_desc *desc, int tx)
204 {
205 u32 t;
206
207 SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc);
208
209 t = desc->buf1;
210 SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t,
211 t & DESC_ADDR_MASK,
212 desc->buflen,
213 (t & DESC_OWN) ? "SWITCH" : "CPU",
214 (t & DESC_EOR) ? " RE" : "");
215
216 t = desc->buf2;
217 SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2,
218 t & DESC_ADDR_MASK,
219 (t & DESC_BUF2_EN) ? " EN" : "" );
220
221 t = desc->misc;
222 if (tx)
223 SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t,
224 (t & DESC_CSUM) ? " CSUM" : "",
225 (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
226 (t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK,
227 t & DESC_VLAN_MASK);
228 else
229 SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
230 t,
231 (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
232 (t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK,
233 (t >> DESC_DA_SHIFT) & DESC_DA_MASK,
234 (t & DESC_IPCSUM_FAIL) ? " IPCF" : "",
235 (t & DESC_VLAN_TAG) ? " VLAN" : "",
236 (t & DESC_TYPE_MASK));
237 }
238
239 static void sw_dump_intr_mask(char *label, u32 mask)
240 {
241 SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
242 label, mask,
243 (mask & SWITCH_INT_SHD) ? " SHD" : "",
244 (mask & SWITCH_INT_SLD) ? " SLD" : "",
245 (mask & SWITCH_INT_RHD) ? " RHD" : "",
246 (mask & SWITCH_INT_RLD) ? " RLD" : "",
247 (mask & SWITCH_INT_HDF) ? " HDF" : "",
248 (mask & SWITCH_INT_LDF) ? " LDF" : "",
249 (mask & SWITCH_INT_P0QF) ? " P0QF" : "",
250 (mask & SWITCH_INT_P1QF) ? " P1QF" : "",
251 (mask & SWITCH_INT_P2QF) ? " P2QF" : "",
252 (mask & SWITCH_INT_P3QF) ? " P3QF" : "",
253 (mask & SWITCH_INT_P4QF) ? " P4QF" : "",
254 (mask & SWITCH_INT_CPQF) ? " CPQF" : "",
255 (mask & SWITCH_INT_GQF) ? " GQF" : "",
256 (mask & SWITCH_INT_MD) ? " MD" : "",
257 (mask & SWITCH_INT_BCS) ? " BCS" : "",
258 (mask & SWITCH_INT_PSC) ? " PSC" : "",
259 (mask & SWITCH_INT_ID) ? " ID" : "",
260 (mask & SWITCH_INT_W0TE) ? " W0TE" : "",
261 (mask & SWITCH_INT_W1TE) ? " W1TE" : "",
262 (mask & SWITCH_INT_RDE) ? " RDE" : "",
263 (mask & SWITCH_INT_SDE) ? " SDE" : "",
264 (mask & SWITCH_INT_CPUH) ? " CPUH" : "");
265 }
266
267 /* ------------------------------------------------------------------------ */
268
269 static inline void adm5120_rx_dma_update(struct dma_desc *desc,
270 struct sk_buff *skb, int end)
271 {
272 desc->misc = 0;
273 desc->buf2 = 0;
274 desc->buflen = RX_MAX_PKTLEN;
275 desc->buf1 = DESC_ADDR(skb->data) |
276 DESC_OWN | (end ? DESC_EOR : 0);
277 }
278
279 static int adm5120_switch_rx(struct net_device *dev, int *budget)
280 {
281 struct sk_buff *skb, *skbn;
282 struct adm5120_sw *priv;
283 struct net_device *cdev;
284 struct dma_desc *desc;
285 int len, quota;
286
287 quota = min(dev->quota, *budget);
288 SW_DBG("%s polling, quota=%d\n", dev->name, quota);
289
290 sw_int_ack(SWITCH_INTS_POLL);
291
292 desc = &rxl_descs[cur_rxl];
293 while (!(desc->buf1 & DESC_OWN) && quota) {
294 u32 port = desc_get_srcport(desc);
295 cdev = adm5120_port[port];
296 if (cdev != dev) { /* The current packet belongs to a different device */
297 if ((cdev==NULL) || !netif_running(cdev)) {
298 /* discard (update with old skb) */
299 skb = skbn = NULL;
300 goto rx_skip;
301 }
302 else {
303 netif_rx_schedule(cdev);/* Start polling next device */
304 return 1; /* return 1 -> More packets to process */
305 }
306
307 }
308 skb = rxl_skbuff[cur_rxl];
309 len = desc_get_pktlen(desc);
310 len -= ETH_CSUM_LEN;
311
312 priv = netdev_priv(dev);
313 if (len <= 0 || len > RX_MAX_PKTLEN ||
314 desc_ipcsum_fail(desc)) {
315 dev->stats.rx_errors++;
316 skbn = NULL;
317 } else {
318 skbn = dev_alloc_skb(SKB_ALLOC_LEN);
319 if (skbn) {
320 skb_put(skb, len);
321 skb->dev = dev;
322 skb->protocol = eth_type_trans(skb, dev);
323 skb->ip_summed = CHECKSUM_UNNECESSARY;
324 dev->last_rx = jiffies;
325 dev->stats.rx_packets++;
326 dev->stats.rx_bytes += len;
327 skb_reserve(skbn, SKB_RESERVE_LEN);
328 rxl_skbuff[cur_rxl] = skbn;
329 } else {
330 SW_INFO("%s recycling!\n", dev->name);
331 }
332 }
333 rx_skip:
334 adm5120_rx_dma_update(&rxl_descs[cur_rxl],
335 rxl_skbuff[cur_rxl],
336 (RX_RING_SIZE-1==cur_rxl));
337 if (RX_RING_SIZE == ++cur_rxl)
338 cur_rxl = 0;
339 desc = &rxl_descs[cur_rxl];
340 if (skbn){
341 netif_receive_skb(skb);
342 dev->quota--;
343 (*budget)--;
344 quota--;
345 }
346 } /* while */
347
348 if (quota) {
349 netif_rx_complete(dev);
350 sw_int_enable(SWITCH_INTS_POLL);
351 return 0;
352 }
353
354 /* If there are still packets to process, return 1 */
355 return 1;
356 }
357
358 static void adm5120_switch_tx(void)
359 {
360 unsigned int entry;
361
362 /* find and cleanup dirty tx descriptors */
363 entry = dirty_txl % TX_RING_SIZE;
364 while (dirty_txl != cur_txl) {
365 struct dma_desc *desc = &txl_descs[entry];
366 struct sk_buff *skb = txl_skbuff[entry];
367
368 if (desc->buf1 & DESC_OWN)
369 break;
370
371 sw_dump_desc("tx done", desc, 1);
372 if (netif_running(skb->dev)) {
373 skb->dev->stats.tx_bytes += skb->len;
374 skb->dev->stats.tx_packets++;
375 }
376
377 dev_kfree_skb_irq(skb);
378 txl_skbuff[entry] = NULL;
379 entry = (++dirty_txl) % TX_RING_SIZE;
380 }
381
382 if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) {
383 /* wake up queue of all devices */
384 int i;
385 for (i = 0; i < SWITCH_NUM_PORTS; i++) {
386 if (!adm5120_devs[i])
387 continue;
388 netif_wake_queue(adm5120_devs[i]);
389 }
390 }
391 }
392
393 static irqreturn_t adm5120_poll_irq(int irq, void *dev_id)
394 {
395 struct net_device *dev = dev_id;
396 u32 status;
397
398 status = sw_read_reg(SWITCH_REG_INT_STATUS);
399 status &= ~(sw_read_reg(SWITCH_REG_INT_MASK));
400
401 status &= SWITCH_INTS_POLL;
402 if (!status)
403 return IRQ_NONE;
404
405 sw_int_disable(SWITCH_INTS_POLL);
406 netif_rx_schedule(dev);
407
408 SW_DBG("%s handling IRQ%d\n", dev->name, irq);
409 return IRQ_HANDLED;
410 }
411
412 static irqreturn_t adm5120_switch_irq(int irq, void *dev_id)
413 {
414 irqreturn_t ret;
415 u32 status;
416
417 status = sw_read_reg(SWITCH_REG_INT_STATUS);
418 status &= ~(sw_read_reg(SWITCH_REG_INT_MASK));
419
420 sw_dump_intr_mask("sw irq", status);
421
422 status &= SWITCH_INTS_ALL & ~SWITCH_INTS_POLL;
423 if (!status)
424 return IRQ_NONE;
425
426 sw_int_ack(status);
427
428 if (status & SWITCH_INT_SLD) {
429 spin_lock(&sw_lock);
430 adm5120_switch_tx();
431 spin_unlock(&sw_lock);
432 }
433
434 return IRQ_HANDLED;
435 }
436
437 static void adm5120_set_vlan(char *matrix)
438 {
439 unsigned long val;
440 int vlan_port, port;
441
442 val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
443 sw_write_reg(SWITCH_REG_VLAN_G1, val);
444 val = matrix[4] + (matrix[5]<<8);
445 sw_write_reg(SWITCH_REG_VLAN_G2, val);
446
447 /* Now set/update the port vs. device lookup table */
448 for (port=0; port<SWITCH_NUM_PORTS; port++) {
449 for (vlan_port=0; vlan_port<SWITCH_NUM_PORTS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++);
450 if (vlan_port <SWITCH_NUM_PORTS)
451 adm5120_port[port] = adm5120_devs[vlan_port];
452 else
453 adm5120_port[port] = NULL;
454 }
455 }
456
457 static void adm5120_set_bw(char *matrix)
458 {
459 unsigned long val;
460
461 /* Port 0 to 3 are set using the bandwidth control 0 register */
462 val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
463 sw_write_reg(SWITCH_REG_BW_CNTL0, val);
464
465 /* Port 4 and 5 are set using the bandwidth control 1 register */
466 val = matrix[4];
467 if (matrix[5] == 1)
468 sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000);
469 else
470 sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
471
472 SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
473 sw_read_reg(SWITCH_REG_BW_CNTL1));
474 }
475
476 static int adm5120_switch_open(struct net_device *dev)
477 {
478 u32 t;
479 int i;
480
481 netif_start_queue(dev);
482 if (!sw_used++)
483 /* enable interrupts on first open */
484 sw_int_enable(SWITCH_INTS_USED);
485
486 /* enable (additional) port */
487 t = sw_read_reg(SWITCH_REG_PORT_CONF0);
488 for (i = 0; i < SWITCH_NUM_PORTS; i++) {
489 if (dev == adm5120_devs[i])
490 t &= ~adm5120_eth_vlans[i];
491 }
492 sw_write_reg(SWITCH_REG_PORT_CONF0, t);
493
494 return 0;
495 }
496
497 static int adm5120_switch_stop(struct net_device *dev)
498 {
499 u32 t;
500 int i;
501
502 if (!--sw_used)
503 sw_int_disable(SWITCH_INTS_USED);
504
505 /* disable port if not assigned to other devices */
506 t = sw_read_reg(SWITCH_REG_PORT_CONF0);
507 t |= SWITCH_PORTS_NOCPU;
508 for (i = 0; i < SWITCH_NUM_PORTS; i++) {
509 if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i]))
510 t &= ~adm5120_eth_vlans[i];
511 }
512 sw_write_reg(SWITCH_REG_PORT_CONF0, t);
513
514 netif_stop_queue(dev);
515 return 0;
516 }
517
518 static int adm5120_sw_start_xmit(struct sk_buff *skb, struct net_device *dev)
519 {
520 struct dma_desc *desc;
521 struct adm5120_sw *priv = netdev_priv(dev);
522 unsigned int entry;
523 unsigned long data;
524
525 /* calculate the next TX descriptor entry. */
526 entry = cur_txl % TX_RING_SIZE;
527
528 desc = &txl_descs[entry];
529 if (desc->buf1 & DESC_OWN) {
530 /* We want to write a packet but the TX queue is still
531 * occupied by the DMA. We are faster than the DMA... */
532 dev_kfree_skb(skb);
533 dev->stats.tx_dropped++;
534 return 0;
535 }
536
537 txl_skbuff[entry] = skb;
538 data = (desc->buf1 & DESC_EOR);
539 data |= DESC_ADDR(skb->data);
540
541 desc->misc =
542 ((skb->len<ETH_ZLEN?ETH_ZLEN:skb->len) << DESC_PKTLEN_SHIFT) |
543 (0x1 << priv->port);
544
545 desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
546
547 /* lock switch irq */
548 spin_lock_irq(&sw_lock);
549
550 desc->buf1 = data | DESC_OWN;
551 sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL);
552
553 cur_txl++;
554 if (cur_txl == dirty_txl + TX_QUEUE_LEN) {
555 /* FIXME: stop queue for all devices */
556 netif_stop_queue(dev);
557 }
558
559 dev->trans_start = jiffies;
560
561 spin_unlock_irq(&sw_lock);
562
563 return 0;
564 }
565
566 static void adm5120_tx_timeout(struct net_device *dev)
567 {
568 SW_INFO("TX timeout on %s\n",dev->name);
569 }
570
571 static void adm5120_set_multicast_list(struct net_device *dev)
572 {
573 struct adm5120_sw *priv = netdev_priv(dev);
574 u32 ports;
575 u32 t;
576
577 ports = adm5120_eth_vlans[priv->port] & SWITCH_PORTS_NOCPU;
578
579 t = sw_read_reg(SWITCH_REG_CPUP_CONF);
580 if (dev->flags & IFF_PROMISC)
581 /* enable unknown packets */
582 t &= ~(ports << CPUP_CONF_DUNP_SHIFT);
583 else
584 /* disable unknown packets */
585 t |= (ports << CPUP_CONF_DUNP_SHIFT);
586
587 if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI ||
588 dev->mc_count)
589 /* enable multicast packets */
590 t &= ~(ports << CPUP_CONF_DMCP_SHIFT);
591 else
592 /* disable multicast packets */
593 t |= (ports << CPUP_CONF_DMCP_SHIFT);
594
595 /* If there is any port configured to be in promiscuous mode, then the */
596 /* Bridge Test Mode has to be activated. This will result in */
597 /* transporting also packets learned in another VLAN to be forwarded */
598 /* to the CPU. */
599 /* The difficult scenario is when we want to build a bridge on the CPU.*/
600 /* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
601 /* CPU port in VLAN1. Now we build a bridge on the CPU between */
602 /* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
603 /* Now assume a packet with ethernet source address 99 enters port 0 */
604 /* It will be forwarded to the CPU because it is unknown. Then the */
605 /* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
606 /* When now a packet with ethernet destination address 99 comes in at */
607 /* port 1 in VLAN1, then the switch has learned that this address is */
608 /* located at port 0 in VLAN0. Therefore the switch will drop */
609 /* this packet. In order to avoid this and to send the packet still */
610 /* to the CPU, the Bridge Test Mode has to be activated. */
611
612 /* Check if there is any vlan in promisc mode. */
613 if (t & (SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT))
614 t &= ~CPUP_CONF_BTM; /* Disable Bridge Testing Mode */
615 else
616 t |= CPUP_CONF_BTM; /* Enable Bridge Testing Mode */
617
618 sw_write_reg(SWITCH_REG_CPUP_CONF, t);
619
620 }
621
622 static void adm5120_write_mac(struct net_device *dev)
623 {
624 struct adm5120_sw *priv = netdev_priv(dev);
625 unsigned char *mac = dev->dev_addr;
626 u32 t;
627
628 t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) |
629 (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC4_SHIFT);
630 sw_write_reg(SWITCH_REG_MAC_WT1, t);
631
632 t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
633 MAC_WT0_MAWC | MAC_WT0_WVE | (priv->port<<3);
634
635 sw_write_reg(SWITCH_REG_MAC_WT0, t);
636
637 while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD));
638 }
639
640 static int adm5120_sw_set_mac_address(struct net_device *dev, void *p)
641 {
642 struct sockaddr *addr = p;
643
644 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
645 adm5120_write_mac(dev);
646 return 0;
647 }
648
649 static int adm5120_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
650 {
651 int err;
652 struct adm5120_sw_info info;
653 struct adm5120_sw *priv = netdev_priv(dev);
654
655 switch(cmd) {
656 case SIOCGADMINFO:
657 info.magic = 0x5120;
658 info.ports = adm5120_nrdevs;
659 info.vlan = priv->port;
660 err = copy_to_user(rq->ifr_data, &info, sizeof(info));
661 if (err)
662 return -EFAULT;
663 break;
664 case SIOCSMATRIX:
665 if (!capable(CAP_NET_ADMIN))
666 return -EPERM;
667 err = copy_from_user(adm5120_eth_vlans, rq->ifr_data,
668 sizeof(adm5120_eth_vlans));
669 if (err)
670 return -EFAULT;
671 adm5120_set_vlan(adm5120_eth_vlans);
672 break;
673 case SIOCGMATRIX:
674 err = copy_to_user(rq->ifr_data, adm5120_eth_vlans,
675 sizeof(adm5120_eth_vlans));
676 if (err)
677 return -EFAULT;
678 break;
679 case SIOCGETBW:
680 err = copy_to_user(rq->ifr_data, bw_matrix, sizeof(bw_matrix));
681 if (err)
682 return -EFAULT;
683 break;
684 case SIOCSETBW:
685 if (!capable(CAP_NET_ADMIN))
686 return -EPERM;
687 err = copy_from_user(bw_matrix, rq->ifr_data, sizeof(bw_matrix));
688 if (err)
689 return -EFAULT;
690 adm5120_set_bw(bw_matrix);
691 break;
692 default:
693 return -EOPNOTSUPP;
694 }
695 return 0;
696 }
697
698 static void adm5120_dma_tx_init(struct dma_desc *desc, struct sk_buff **skbl,
699 int num)
700 {
701 memset(desc, 0, num * sizeof(*desc));
702 desc[num-1].buf1 |= DESC_EOR;
703 memset(skbl, 0, sizeof(struct skb*)*num);
704 }
705
706 static void adm5120_dma_rx_init(struct dma_desc *desc, struct sk_buff **skbl,
707 int num)
708 {
709 int i;
710
711 memset(desc, 0, num * sizeof(*desc));
712 for (i=0; i<num; i++) {
713 skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
714 if (!skbl[i]) {
715 i=num;
716 break;
717 }
718 skb_reserve(skbl[i], SKB_RESERVE_LEN);
719 adm5120_rx_dma_update(&desc[i], skbl[i], (num-1==i));
720 }
721 }
722
723 static int __init adm5120_sw_init(void)
724 {
725 struct net_device *dev;
726 u32 t;
727 int i, err;
728
729 err = request_irq(ADM5120_IRQ_SWITCH, adm5120_switch_irq,
730 (IRQF_SHARED | IRQF_DISABLED), "switch", &sw_dev);
731 if (err)
732 goto out;
733
734 adm5120_nrdevs = adm5120_eth_num_ports;
735
736 t = CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
737 SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT |
738 SWITCH_PORTS_NOCPU << CPUP_CONF_DMCP_SHIFT ;
739 sw_write_reg(SWITCH_REG_CPUP_CONF, t);
740
741 t = (SWITCH_PORTS_NOCPU << PORT_CONF0_EMCP_SHIFT) |
742 (SWITCH_PORTS_NOCPU << PORT_CONF0_BP_SHIFT) |
743 (SWITCH_PORTS_NOCPU);
744 sw_write_reg(SWITCH_REG_PORT_CONF0, t);
745
746 /* setup ports to Autoneg/100M/Full duplex/Auto MDIX */
747 t = SWITCH_PORTS_PHY |
748 (SWITCH_PORTS_PHY << PHY_CNTL2_SC_SHIFT) |
749 (SWITCH_PORTS_PHY << PHY_CNTL2_DC_SHIFT) |
750 (SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
751 (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
752 PHY_CNTL2_RMAE;
753 SW_WRITE_REG(PHY_CNTL2, t);
754
755 t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
756 t |= PHY_CNTL3_RNT;
757 sw_write_reg(SWITCH_REG_PHY_CNTL3, t);
758
759 /* Force all the packets from all ports are low priority */
760 sw_write_reg(SWITCH_REG_PRI_CNTL, 0);
761
762 sw_int_disable(SWITCH_INTS_ALL);
763 sw_int_ack(SWITCH_INTS_ALL);
764
765 cur_txl = dirty_txl = 0;
766 cur_rxl = dirty_rxl = 0;
767
768 txh_descs = (void *)KSEG1ADDR((u32)txh_descs_v);
769 txl_descs = (void *)KSEG1ADDR((u32)txl_descs_v);
770 rxh_descs = (void *)KSEG1ADDR((u32)rxh_descs_v);
771 rxl_descs = (void *)KSEG1ADDR((u32)rxl_descs_v);
772
773 adm5120_dma_tx_init(txh_descs, txh_skbuff, TX_RING_SIZE);
774 adm5120_dma_tx_init(txl_descs, txl_skbuff, TX_RING_SIZE);
775 adm5120_dma_rx_init(rxh_descs, rxh_skbuff, RX_RING_SIZE);
776 adm5120_dma_rx_init(rxl_descs, rxl_skbuff, RX_RING_SIZE);
777 sw_write_reg(SWITCH_REG_SHDA, KSEG1ADDR(txh_descs));
778 sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs));
779 sw_write_reg(SWITCH_REG_RHDA, KSEG1ADDR(rxh_descs));
780 sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs));
781
782 for (i = 0; i < SWITCH_NUM_PORTS; i++) {
783 adm5120_devs[i] = alloc_etherdev(sizeof(struct adm5120_sw));
784 if (!adm5120_devs[i]) {
785 err = -ENOMEM;
786 goto out_int;
787 }
788
789 dev = adm5120_devs[i];
790 err = request_irq(ADM5120_IRQ_SWITCH, adm5120_poll_irq,
791 (IRQF_SHARED | IRQF_DISABLED), dev->name, dev);
792 if (err) {
793 SW_ERR("unable to get irq for %s\n", dev->name);
794 goto out_int;
795 }
796
797 SET_MODULE_OWNER(dev);
798 memset(netdev_priv(dev), 0, sizeof(struct adm5120_sw));
799 ((struct adm5120_sw*)netdev_priv(dev))->port = i;
800 dev->base_addr = ADM5120_SWITCH_BASE;
801 dev->irq = ADM5120_IRQ_SWITCH;
802 dev->open = adm5120_switch_open;
803 dev->hard_start_xmit = adm5120_sw_start_xmit;
804 dev->stop = adm5120_switch_stop;
805 dev->set_multicast_list = adm5120_set_multicast_list;
806 dev->do_ioctl = adm5120_do_ioctl;
807 dev->tx_timeout = adm5120_tx_timeout;
808 dev->watchdog_timeo = TX_TIMEOUT;
809 dev->set_mac_address = adm5120_sw_set_mac_address;
810 dev->poll = adm5120_switch_rx;
811 dev->weight = 64;
812
813 memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
814 adm5120_write_mac(dev);
815
816 if ((err = register_netdev(dev))) {
817 free_irq(ADM5120_IRQ_SWITCH, dev);
818 free_netdev(dev);
819 goto out_int;
820 }
821 SW_INFO("%s created for switch port%d\n", dev->name, i);
822 }
823 /* setup vlan/port mapping after devs are filled up */
824 adm5120_set_vlan(adm5120_eth_vlans);
825
826 /* enable CPU port */
827 t = sw_read_reg(SWITCH_REG_CPUP_CONF);
828 t &= ~CPUP_CONF_DCPUP;
829 sw_write_reg(SWITCH_REG_CPUP_CONF, t);
830
831 return 0;
832
833 out_int:
834 /* Undo everything that did succeed */
835 for (; i; i--) {
836 unregister_netdev(adm5120_devs[i-1]);
837 free_netdev(adm5120_devs[i-1]);
838 }
839 free_irq(ADM5120_IRQ_SWITCH, NULL);
840 out:
841 SW_ERR("init failed\n");
842 return err;
843 }
844
845 static void __exit adm5120_sw_exit(void)
846 {
847 int i;
848
849 for (i = 0; i < SWITCH_NUM_PORTS; i++) {
850 struct net_device *dev = adm5120_devs[i];
851 unregister_netdev(dev);
852 free_irq(ADM5120_IRQ_SWITCH, dev);
853 free_netdev(dev);
854 }
855
856 free_irq(ADM5120_IRQ_SWITCH, &sw_dev);
857
858 for (i = 0; i < RX_RING_SIZE; i++) {
859 if (!rxh_skbuff[i])
860 break;
861 kfree_skb(rxh_skbuff[i]);
862 }
863
864 for (i = 0; i < RX_RING_SIZE; i++) {
865 if (!rxl_skbuff[i])
866 break;
867 kfree_skb(rxl_skbuff[i]);
868 }
869 }
870
871 module_init(adm5120_sw_init);
872 module_exit(adm5120_sw_exit);
OpenWrt Source Repository