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[openwrt/openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ahcd fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 *
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
17 *
18 * This file is licenced under the GPL.
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
44
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
47
48 #define DRIVER_VERSION "v0.10"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #undef ADMHC_VERBOSE_DEBUG /* not always helpful */
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58
59 #define ADMHC_INTR_INIT \
60 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
61 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
62
63 /*-------------------------------------------------------------------------*/
64
65 static const char hcd_name [] = "admhc-hcd";
66
67 #define STATECHANGE_DELAY msecs_to_jiffies(300)
68
69 #include "adm5120.h"
70
71 static void admhc_dump(struct admhcd *ahcd, int verbose);
72 static int admhc_init(struct admhcd *ahcd);
73 static void admhc_stop(struct usb_hcd *hcd);
74
75 #include "adm5120-dbg.c"
76 #include "adm5120-mem.c"
77 #include "adm5120-pm.c"
78 #include "adm5120-hub.c"
79 #include "adm5120-q.c"
80
81 /*-------------------------------------------------------------------------*/
82
83 /*
84 * queue up an urb for anything except the root hub
85 */
86 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
87 struct urb *urb, gfp_t mem_flags)
88 {
89 struct admhcd *ahcd = hcd_to_admhcd(hcd);
90 struct ed *ed;
91 struct urb_priv *urb_priv;
92 unsigned int pipe = urb->pipe;
93 int td_cnt = 0;
94 unsigned long flags;
95 int ret = 0;
96
97 #ifdef ADMHC_VERBOSE_DEBUG
98 spin_lock_irqsave(&ahcd->lock, flags);
99 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe));
100 spin_unlock_irqrestore(&ahcd->lock, flags);
101 #endif
102
103 /* every endpoint has an ed, locate and maybe (re)initialize it */
104 ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
105 if (!ed)
106 return -ENOMEM;
107
108 /* for the private part of the URB we need the number of TDs */
109 switch (ed->type) {
110 case PIPE_CONTROL:
111 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
112 /* td_submit_urb() doesn't yet handle these */
113 return -EMSGSIZE;
114
115 /* 1 TD for setup, 1 for ACK, plus ... */
116 td_cnt = 2;
117 /* FALLTHROUGH */
118 case PIPE_BULK:
119 /* one TD for every 4096 Bytes (can be upto 8K) */
120 td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
121 /* ... and for any remaining bytes ... */
122 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
123 td_cnt++;
124 /* ... and maybe a zero length packet to wrap it up */
125 if (td_cnt == 0)
126 td_cnt++;
127 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
128 && (urb->transfer_buffer_length
129 % usb_maxpacket(urb->dev, pipe,
130 usb_pipeout (pipe))) == 0)
131 td_cnt++;
132 break;
133 case PIPE_INTERRUPT:
134 /*
135 * for Interrupt IN/OUT transactions, each ED contains
136 * only 1 TD.
137 * TODO: check transfer_buffer_length?
138 */
139 td_cnt = 1;
140 break;
141 case PIPE_ISOCHRONOUS:
142 /* number of packets from URB */
143 td_cnt = urb->number_of_packets;
144 break;
145 default:
146 /* paranoia */
147 admhc_err(ahcd, "bad EP type %d", ed->type);
148 return -EINVAL;
149 }
150
151 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
152 if (!urb_priv)
153 return -ENOMEM;
154
155 urb_priv->ed = ed;
156
157 spin_lock_irqsave(&ahcd->lock, flags);
158 /* don't submit to a dead HC */
159 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
160 ret = -ENODEV;
161 goto fail;
162 }
163 if (!HC_IS_RUNNING(hcd->state)) {
164 ret = -ENODEV;
165 goto fail;
166 }
167
168 /* in case of unlink-during-submit */
169 spin_lock(&urb->lock);
170 if (urb->status != -EINPROGRESS) {
171 spin_unlock(&urb->lock);
172 urb->hcpriv = urb_priv;
173 finish_urb(ahcd, urb);
174 ret = 0;
175 goto fail;
176 }
177
178 /* schedule the ed if needed */
179 if (ed->state == ED_IDLE) {
180 ret = ed_schedule(ahcd, ed);
181 if (ret < 0)
182 goto fail0;
183
184 if (ed->type == PIPE_ISOCHRONOUS) {
185 u16 frame = admhc_frame_no(ahcd);
186
187 /* delay a few frames before the first TD */
188 frame += max_t (u16, 8, ed->interval);
189 frame &= ~(ed->interval - 1);
190 frame |= ed->branch;
191 urb->start_frame = frame;
192
193 /* yes, only URB_ISO_ASAP is supported, and
194 * urb->start_frame is never used as input.
195 */
196 }
197 } else if (ed->type == PIPE_ISOCHRONOUS)
198 urb->start_frame = ed->last_iso + ed->interval;
199
200 /* fill the TDs and link them to the ed; and
201 * enable that part of the schedule, if needed
202 * and update count of queued periodic urbs
203 */
204 urb->hcpriv = urb_priv;
205 td_submit_urb(ahcd, urb);
206
207 #ifdef ADMHC_VERBOSE_DEBUG
208 admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
209 #endif
210 fail0:
211 spin_unlock(&urb->lock);
212 fail:
213 if (ret)
214 urb_priv_free(ahcd, urb_priv);
215
216 spin_unlock_irqrestore(&ahcd->lock, flags);
217 return ret;
218 }
219
220 /*
221 * decouple the URB from the HC queues (TDs, urb_priv); it's
222 * already marked using urb->status. reporting is always done
223 * asynchronously, and we might be dealing with an urb that's
224 * partially transferred, or an ED with other urbs being unlinked.
225 */
226 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
227 {
228 struct admhcd *ahcd = hcd_to_admhcd(hcd);
229 unsigned long flags;
230
231 #ifdef ADMHC_VERBOSE_DEBUG
232 urb_print(ahcd, urb, "DEQUEUE", 1);
233 #endif
234
235 spin_lock_irqsave(&ahcd->lock, flags);
236 if (HC_IS_RUNNING(hcd->state)) {
237 struct urb_priv *urb_priv;
238
239 /* Unless an IRQ completed the unlink while it was being
240 * handed to us, flag it for unlink and giveback, and force
241 * some upcoming INTR_SF to call finish_unlinks()
242 */
243 urb_priv = urb->hcpriv;
244 if (urb_priv) {
245 if (urb_priv->ed->state == ED_OPER)
246 start_ed_unlink(ahcd, urb_priv->ed);
247 }
248 } else {
249 /*
250 * with HC dead, we won't respect hc queue pointers
251 * any more ... just clean up every urb's memory.
252 */
253 if (urb->hcpriv)
254 finish_urb(ahcd, urb);
255 }
256 spin_unlock_irqrestore(&ahcd->lock, flags);
257
258 return 0;
259 }
260
261 /*-------------------------------------------------------------------------*/
262
263 /* frees config/altsetting state for endpoints,
264 * including ED memory, dummy TD, and bulk/intr data toggle
265 */
266
267 static void admhc_endpoint_disable(struct usb_hcd *hcd,
268 struct usb_host_endpoint *ep)
269 {
270 struct admhcd *ahcd = hcd_to_admhcd(hcd);
271 unsigned long flags;
272 struct ed *ed = ep->hcpriv;
273 unsigned limit = 1000;
274
275 /* ASSERT: any requests/urbs are being unlinked */
276 /* ASSERT: nobody can be submitting urbs for this any more */
277
278 if (!ed)
279 return;
280
281 #ifdef ADMHC_VERBOSE_DEBUG
282 spin_lock_irqsave(&ahcd->lock, flags);
283 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
284 spin_unlock_irqrestore(&ahcd->lock, flags);
285 #endif
286
287 rescan:
288 spin_lock_irqsave(&ahcd->lock, flags);
289
290 if (!HC_IS_RUNNING(hcd->state)) {
291 sanitize:
292 ed->state = ED_IDLE;
293 finish_unlinks(ahcd, 0);
294 }
295
296 switch (ed->state) {
297 case ED_UNLINK: /* wait for hw to finish? */
298 /* major IRQ delivery trouble loses INTR_SOFI too... */
299 if (limit-- == 0) {
300 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
301 goto sanitize;
302 }
303 spin_unlock_irqrestore(&ahcd->lock, flags);
304 schedule_timeout_uninterruptible(1);
305 goto rescan;
306 case ED_IDLE: /* fully unlinked */
307 if (list_empty(&ed->td_list)) {
308 td_free (ahcd, ed->dummy);
309 ed_free (ahcd, ed);
310 break;
311 }
312 /* else FALL THROUGH */
313 default:
314 /* caller was supposed to have unlinked any requests;
315 * that's not our job. can't recover; must leak ed.
316 */
317 admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
318 ed, ep->desc.bEndpointAddress, ed->state,
319 list_empty(&ed->td_list) ? "" : " (has tds)");
320 td_free(ahcd, ed->dummy);
321 break;
322 }
323
324 ep->hcpriv = NULL;
325
326 spin_unlock_irqrestore(&ahcd->lock, flags);
327 return;
328 }
329
330 static int admhc_get_frame_number(struct usb_hcd *hcd)
331 {
332 struct admhcd *ahcd = hcd_to_admhcd(hcd);
333
334 return admhc_frame_no(ahcd);
335 }
336
337 static void admhc_usb_reset(struct admhcd *ahcd)
338 {
339 #if 0
340 ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
341 ahcd->hc_control &= OHCI_CTRL_RWC;
342 admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
343 #else
344 /* FIXME */
345 ahcd->host_control = ADMHC_BUSS_RESET;
346 admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
347 #endif
348 }
349
350 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
351 * other cases where the next software may expect clean state from the
352 * "firmware". this is bus-neutral, unlike shutdown() methods.
353 */
354 static void
355 admhc_shutdown(struct usb_hcd *hcd)
356 {
357 struct admhcd *ahcd;
358
359 ahcd = hcd_to_admhcd(hcd);
360 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
361 admhc_dma_disable(ahcd);
362 admhc_usb_reset(ahcd);
363 /* flush the writes */
364 admhc_writel_flush(ahcd);
365 }
366
367 /*-------------------------------------------------------------------------*
368 * HC functions
369 *-------------------------------------------------------------------------*/
370
371 static void admhc_eds_cleanup(struct admhcd *ahcd)
372 {
373 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
374 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
375 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
376 }
377
378 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
379 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
380 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
381 }
382
383 if (ahcd->ed_tails[PIPE_CONTROL]) {
384 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
385 ahcd->ed_tails[PIPE_CONTROL] = NULL;
386 }
387
388 if (ahcd->ed_tails[PIPE_BULK]) {
389 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
390 ahcd->ed_tails[PIPE_BULK] = NULL;
391 }
392
393 ahcd->ed_head = NULL;
394 }
395
396 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
397
398 static int admhc_eds_init(struct admhcd *ahcd)
399 {
400 struct ed *ed;
401
402 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
403 if (!ed)
404 goto err;
405
406 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
407
408 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
409 if (!ed)
410 goto err;
411
412 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
413 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
414 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
415 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
416
417 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
418 if (!ed)
419 goto err;
420
421 ahcd->ed_tails[PIPE_CONTROL] = ed;
422 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
423 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
424 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
425
426 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
427 if (!ed)
428 goto err;
429
430 ahcd->ed_tails[PIPE_BULK] = ed;
431 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
432 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
433 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
434
435 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
436
437 #ifdef ADMHC_VERBOSE_DEBUG
438 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
439 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
440 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
441 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
442 #endif
443
444 return 0;
445
446 err:
447 admhc_eds_cleanup(ahcd);
448 return -ENOMEM;
449 }
450
451 /* init memory, and kick BIOS/SMM off */
452
453 static int admhc_init(struct admhcd *ahcd)
454 {
455 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
456 int ret;
457
458 admhc_disable(ahcd);
459 ahcd->regs = hcd->regs;
460
461 /* Disable HC interrupts */
462 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
463
464 /* Read the number of ports unless overridden */
465 if (ahcd->num_ports == 0)
466 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
467
468 ret = admhc_mem_init(ahcd);
469 if (ret)
470 goto err;
471
472 /* init dummy endpoints */
473 ret = admhc_eds_init(ahcd);
474 if (ret)
475 goto err;
476
477 create_debug_files(ahcd);
478
479 return 0;
480
481 err:
482 admhc_stop(hcd);
483 return ret;
484 }
485
486 /*-------------------------------------------------------------------------*/
487
488 /* Start an OHCI controller, set the BUS operational
489 * resets USB and controller
490 * enable interrupts
491 */
492 static int admhc_run(struct admhcd *ahcd)
493 {
494 u32 temp;
495 int first = ahcd->fminterval == 0;
496 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
497
498 admhc_disable(ahcd);
499
500 /* boot firmware should have set this up (5.1.1.3.1) */
501 if (first) {
502 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
503 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
504 if (ahcd->fminterval != FI)
505 admhc_dbg(ahcd, "fminterval delta %d\n",
506 ahcd->fminterval - FI);
507 ahcd->fminterval |=
508 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
509 /* also: power/overcurrent flags in rhdesc */
510 }
511
512 #if 0 /* TODO: not applicable */
513 /* Reset USB nearly "by the book". RemoteWakeupConnected was
514 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
515 * or if bus glue did the same (e.g. for PCI add-in cards with
516 * PCI PM support).
517 */
518 if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
519 && !device_may_wakeup(hcd->self.controller))
520 device_init_wakeup(hcd->self.controller, 1);
521 #endif
522
523 switch (ahcd->host_control & ADMHC_HC_BUSS) {
524 case ADMHC_BUSS_OPER:
525 temp = 0;
526 break;
527 case ADMHC_BUSS_SUSPEND:
528 /* FALLTHROUGH ? */
529 case ADMHC_BUSS_RESUME:
530 ahcd->host_control = ADMHC_BUSS_RESUME;
531 temp = 10 /* msec wait */;
532 break;
533 /* case ADMHC_BUSS_RESET: */
534 default:
535 ahcd->host_control = ADMHC_BUSS_RESET;
536 temp = 50 /* msec wait */;
537 break;
538 }
539 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
540
541 /* flush the writes */
542 admhc_writel_flush(ahcd);
543
544 msleep(temp);
545 temp = admhc_read_rhdesc(ahcd);
546 if (!(temp & ADMHC_RH_NPS)) {
547 /* power down each port */
548 for (temp = 0; temp < ahcd->num_ports; temp++)
549 admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
550 }
551 /* flush those writes */
552 admhc_writel_flush(ahcd);
553
554 /* 2msec timelimit here means no irqs/preempt */
555 spin_lock_irq(&ahcd->lock);
556
557 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
558 temp = 30; /* ... allow extra time */
559 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
560 if (--temp == 0) {
561 spin_unlock_irq(&ahcd->lock);
562 admhc_err(ahcd, "USB HC reset timed out!\n");
563 return -1;
564 }
565 udelay(1);
566 }
567
568 /* enable HOST mode, before access any host specific register */
569 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
570
571 /* Tell the controller where the descriptor list is */
572 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
573
574 periodic_reinit(ahcd);
575
576 /* use rhsc irqs after khubd is fully initialized */
577 hcd->poll_rh = 1;
578 hcd->uses_new_polling = 1;
579
580 #if 0
581 /* wake on ConnectStatusChange, matching external hubs */
582 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
583 #else
584 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
585 #endif
586
587 /* Choose the interrupts we care about now, others later on demand */
588 admhc_intr_ack(ahcd, ~0);
589 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
590
591 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
592
593 /* flush those writes */
594 admhc_writel_flush(ahcd);
595
596 /* start controller operations */
597 ahcd->host_control = ADMHC_BUSS_OPER;
598 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
599
600 temp = 20;
601 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
602 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
603 if (--temp == 0) {
604 spin_unlock_irq(&ahcd->lock);
605 admhc_err(ahcd, "unable to setup operational mode!\n");
606 return -1;
607 }
608 mdelay(1);
609 }
610
611 hcd->state = HC_STATE_RUNNING;
612
613 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
614
615 #if 0
616 /* FIXME: enabling DMA is always failed here for an unknown reason */
617 admhc_dma_enable(ahcd);
618
619 temp = 200;
620 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
621 & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
622 if (--temp == 0) {
623 spin_unlock_irq(&ahcd->lock);
624 admhc_err(ahcd, "unable to enable DMA!\n");
625 admhc_dump(ahcd, 1);
626 return -1;
627 }
628 mdelay(1);
629 }
630
631 #endif
632
633 spin_unlock_irq(&ahcd->lock);
634
635 mdelay(ADMHC_POTPGT);
636
637 return 0;
638 }
639
640 /*-------------------------------------------------------------------------*/
641
642 /* an interrupt happens */
643
644 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
645 {
646 struct admhcd *ahcd = hcd_to_admhcd(hcd);
647 struct admhcd_regs __iomem *regs = ahcd->regs;
648 u32 ints;
649
650 ints = admhc_readl(ahcd, &regs->int_status);
651 if ((ints & ADMHC_INTR_INTA) == 0) {
652 /* no unmasked interrupt status is set */
653 return IRQ_NONE;
654 }
655
656 ints &= admhc_readl(ahcd, &regs->int_enable);
657
658 if (ints & ADMHC_INTR_FATI) {
659 /* e.g. due to PCI Master/Target Abort */
660 admhc_disable(ahcd);
661 admhc_err(ahcd, "Fatal Error, controller disabled\n");
662 admhc_dump(ahcd, 1);
663 admhc_usb_reset(ahcd);
664 }
665
666 if (ints & ADMHC_INTR_BABI) {
667 admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
668 admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
669 admhc_err(ahcd, "Babble Detected\n");
670 }
671
672 if (ints & ADMHC_INTR_INSM) {
673 admhc_vdbg(ahcd, "Root Hub Status Change\n");
674 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
675 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
676
677 /* NOTE: Vendors didn't always make the same implementation
678 * choices for RHSC. Many followed the spec; RHSC triggers
679 * on an edge, like setting and maybe clearing a port status
680 * change bit. With others it's level-triggered, active
681 * until khubd clears all the port status change bits. We'll
682 * always disable it here and rely on polling until khubd
683 * re-enables it.
684 */
685 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
686 usb_hcd_poll_rh_status(hcd);
687 } else if (ints & ADMHC_INTR_RESI) {
688 /* For connect and disconnect events, we expect the controller
689 * to turn on RHSC along with RD. But for remote wakeup events
690 * this might not happen.
691 */
692 admhc_vdbg(ahcd, "Resume Detect\n");
693 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
694 hcd->poll_rh = 1;
695 if (ahcd->autostop) {
696 spin_lock(&ahcd->lock);
697 admhc_rh_resume(ahcd);
698 spin_unlock(&ahcd->lock);
699 } else
700 usb_hcd_resume_root_hub(hcd);
701 }
702
703 if (ints & ADMHC_INTR_TDC) {
704 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
705 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
706 if (HC_IS_RUNNING(hcd->state))
707 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
708 spin_lock(&ahcd->lock);
709 admhc_td_complete(ahcd);
710 spin_unlock(&ahcd->lock);
711 if (HC_IS_RUNNING(hcd->state))
712 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
713 }
714
715 if (ints & ADMHC_INTR_SO) {
716 /* could track INTR_SO to reduce available PCI/... bandwidth */
717 admhc_vdbg(ahcd, "Schedule Overrun\n");
718 }
719
720 #if 1
721 spin_lock(&ahcd->lock);
722 if (ahcd->ed_rm_list)
723 finish_unlinks(ahcd, admhc_frame_no(ahcd));
724
725 if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
726 && HC_IS_RUNNING(hcd->state))
727 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
728 spin_unlock(&ahcd->lock);
729 #else
730 if (ints & ADMHC_INTR_SOFI) {
731 admhc_vdbg(ahcd, "Start Of Frame\n");
732 spin_lock(&ahcd->lock);
733
734 /* handle any pending ED removes */
735 finish_unlinks(ahcd, admhc_frameno(ahcd));
736
737 /* leaving INTR_SOFI enabled when there's still unlinking
738 * to be done in the (next frame).
739 */
740 if ((ahcd->ed_rm_list == NULL) ||
741 HC_IS_RUNNING(hcd->state) == 0)
742 /*
743 * disable INTR_SOFI if there are no unlinking to be
744 * done (in the next frame)
745 */
746 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
747
748 spin_unlock(&ahcd->lock);
749 }
750 #endif
751
752 if (HC_IS_RUNNING(hcd->state)) {
753 admhc_intr_ack(ahcd, ints);
754 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
755 admhc_writel_flush(ahcd);
756 }
757
758 return IRQ_HANDLED;
759 }
760
761 /*-------------------------------------------------------------------------*/
762
763 static void admhc_stop(struct usb_hcd *hcd)
764 {
765 struct admhcd *ahcd = hcd_to_admhcd(hcd);
766
767 admhc_dump(ahcd, 1);
768
769 flush_scheduled_work();
770
771 admhc_usb_reset(ahcd);
772 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
773
774 free_irq(hcd->irq, hcd);
775 hcd->irq = -1;
776
777 remove_debug_files(ahcd);
778 admhc_eds_cleanup(ahcd);
779 admhc_mem_cleanup(ahcd);
780 }
781
782 /*-------------------------------------------------------------------------*/
783
784 #ifdef CONFIG_MIPS_ADM5120
785 #include "adm5120-drv.c"
786 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
787 #endif
788
789 #if !defined(PLATFORM_DRIVER)
790 #error "missing bus glue for admhc-hcd"
791 #endif
792
793 #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
794
795 static int __init admhc_hcd_mod_init(void)
796 {
797 int ret = 0;
798
799 if (usb_disabled())
800 return -ENODEV;
801
802 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
803 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
804 sizeof (struct ed), sizeof (struct td));
805
806 #ifdef PLATFORM_DRIVER
807 ret = platform_driver_register(&PLATFORM_DRIVER);
808 if (ret < 0)
809 goto error_platform;
810 #endif
811
812 return ret;
813
814 #ifdef PLATFORM_DRIVER
815 platform_driver_unregister(&PLATFORM_DRIVER);
816 error_platform:
817 #endif
818 return ret;
819 }
820 module_init(admhc_hcd_mod_init);
821
822 static void __exit admhc_hcd_mod_exit(void)
823 {
824 platform_driver_unregister(&PLATFORM_DRIVER);
825 }
826 module_exit(admhc_hcd_mod_exit);
827
828 MODULE_AUTHOR(DRIVER_AUTHOR);
829 MODULE_DESCRIPTION(DRIVER_INFO);
830 MODULE_LICENSE("GPL");
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