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[openwrt/openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-q.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * This file is licenced under the GPL.
8 */
9
10 #include <linux/irq.h>
11
12 /*-------------------------------------------------------------------------*/
13
14 /*
15 * URB goes back to driver, and isn't reissued.
16 * It's completely gone from HC data structures.
17 * PRECONDITION: ahcd lock held, irqs blocked.
18 */
19 static void
20 finish_urb(struct admhcd *ahcd, struct urb *urb)
21 __releases(ahcd->lock)
22 __acquires(ahcd->lock)
23 {
24 urb_priv_free(ahcd, urb->hcpriv);
25 urb->hcpriv = NULL;
26
27 spin_lock(&urb->lock);
28 if (likely(urb->status == -EINPROGRESS))
29 urb->status = 0;
30
31 /* report short control reads right even though the data TD always
32 * has TD_R set. (much simpler, but creates the 1-td limit.)
33 */
34 if (unlikely(urb->transfer_flags & URB_SHORT_NOT_OK)
35 && unlikely(usb_pipecontrol(urb->pipe))
36 && urb->actual_length < urb->transfer_buffer_length
37 && usb_pipein(urb->pipe)
38 && urb->status == 0) {
39 urb->status = -EREMOTEIO;
40 #ifdef ADMHC_VERBOSE_DEBUG
41 urb_print(urb, "SHORT", usb_pipeout (urb->pipe));
42 #endif
43 }
44 spin_unlock(&urb->lock);
45
46 switch (usb_pipetype(urb->pipe)) {
47 case PIPE_ISOCHRONOUS:
48 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
49 break;
50 case PIPE_INTERRUPT:
51 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
52 break;
53 }
54
55 #ifdef ADMHC_VERBOSE_DEBUG
56 urb_print(urb, "RET", usb_pipeout (urb->pipe));
57 #endif
58
59 /* urb->complete() can reenter this HCD */
60 spin_unlock(&ahcd->lock);
61 usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb);
62 spin_lock(&ahcd->lock);
63 }
64
65
66 /*-------------------------------------------------------------------------*
67 * ED handling functions
68 *-------------------------------------------------------------------------*/
69
70 #if 0 /* FIXME */
71 /* search for the right schedule branch to use for a periodic ed.
72 * does some load balancing; returns the branch, or negative errno.
73 */
74 static int balance(struct admhcd *ahcd, int interval, int load)
75 {
76 int i, branch = -ENOSPC;
77
78 /* iso periods can be huge; iso tds specify frame numbers */
79 if (interval > NUM_INTS)
80 interval = NUM_INTS;
81
82 /* search for the least loaded schedule branch of that period
83 * that has enough bandwidth left unreserved.
84 */
85 for (i = 0; i < interval ; i++) {
86 if (branch < 0 || ahcd->load [branch] > ahcd->load [i]) {
87 int j;
88
89 /* usb 1.1 says 90% of one frame */
90 for (j = i; j < NUM_INTS; j += interval) {
91 if ((ahcd->load [j] + load) > 900)
92 break;
93 }
94 if (j < NUM_INTS)
95 continue;
96 branch = i;
97 }
98 }
99 return branch;
100 }
101 #endif
102
103 /*-------------------------------------------------------------------------*/
104
105 #if 0 /* FIXME */
106 /* both iso and interrupt requests have periods; this routine puts them
107 * into the schedule tree in the apppropriate place. most iso devices use
108 * 1msec periods, but that's not required.
109 */
110 static void periodic_link (struct admhcd *ahcd, struct ed *ed)
111 {
112 unsigned i;
113
114 admhc_vdbg (ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
115 (ed->hwINFO & cpu_to_hc32 (ahcd, ED_ISO)) ? "iso " : "",
116 ed, ed->branch, ed->load, ed->interval);
117
118 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
119 struct ed **prev = &ahcd->periodic [i];
120 __hc32 *prev_p = &ahcd->hcca->int_table [i];
121 struct ed *here = *prev;
122
123 /* sorting each branch by period (slow before fast)
124 * lets us share the faster parts of the tree.
125 * (plus maybe: put interrupt eds before iso)
126 */
127 while (here && ed != here) {
128 if (ed->interval > here->interval)
129 break;
130 prev = &here->ed_next;
131 prev_p = &here->hwNextED;
132 here = *prev;
133 }
134 if (ed != here) {
135 ed->ed_next = here;
136 if (here)
137 ed->hwNextED = *prev_p;
138 wmb ();
139 *prev = ed;
140 *prev_p = cpu_to_hc32(ahcd, ed->dma);
141 wmb();
142 }
143 ahcd->load [i] += ed->load;
144 }
145 admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
146 }
147 #endif
148
149 /* link an ed into the HC chain */
150
151 static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
152 {
153 struct ed *old_tail;
154
155 if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
156 return -EAGAIN;
157
158 ed->state = ED_OPER;
159
160 old_tail = ahcd->ed_tails[ed->type];
161
162 ed->ed_next = old_tail->ed_next;
163 if (ed->ed_next) {
164 ed->ed_next->ed_prev = ed;
165 ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
166 }
167 ed->ed_prev = old_tail;
168
169 old_tail->ed_next = ed;
170 old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
171
172 ahcd->ed_tails[ed->type] = ed;
173
174 admhc_dma_enable(ahcd);
175
176 return 0;
177 }
178
179 /*-------------------------------------------------------------------------*/
180
181 #if 0 /* FIXME */
182 /* scan the periodic table to find and unlink this ED */
183 static void periodic_unlink (struct admhcd *ahcd, struct ed *ed)
184 {
185 int i;
186
187 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
188 struct ed *temp;
189 struct ed **prev = &ahcd->periodic [i];
190 __hc32 *prev_p = &ahcd->hcca->int_table [i];
191
192 while (*prev && (temp = *prev) != ed) {
193 prev_p = &temp->hwNextED;
194 prev = &temp->ed_next;
195 }
196 if (*prev) {
197 *prev_p = ed->hwNextED;
198 *prev = ed->ed_next;
199 }
200 ahcd->load [i] -= ed->load;
201 }
202
203 admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
204 admhc_vdbg (ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
205 (ed->hwINFO & cpu_to_hc32 (ahcd, ED_ISO)) ? "iso " : "",
206 ed, ed->branch, ed->load, ed->interval);
207 }
208 #endif
209
210 /* unlink an ed from the HC chain.
211 * just the link to the ed is unlinked.
212 * the link from the ed still points to another operational ed or 0
213 * so the HC can eventually finish the processing of the unlinked ed
214 * (assuming it already started that, which needn't be true).
215 *
216 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
217 * it won't. ED_SKIP means the HC will finish its current transaction,
218 * but won't start anything new. The TD queue may still grow; device
219 * drivers don't know about this HCD-internal state.
220 *
221 * When the HC can't see the ED, something changes ED_UNLINK to one of:
222 *
223 * - ED_OPER: when there's any request queued, the ED gets rescheduled
224 * immediately. HC should be working on them.
225 *
226 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
227 * to care about this ED; safe to disable the endpoint.
228 *
229 * When finish_unlinks() runs later, after SOF interrupt, it will often
230 * complete one or more URB unlinks before making that state change.
231 */
232 static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
233 {
234 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
235 wmb();
236 ed->state = ED_UNLINK;
237
238 /* remove this ED from the HC list */
239 ed->ed_prev->hwNextED = ed->hwNextED;
240
241 /* and remove it from our list also */
242 ed->ed_prev->ed_next = ed->ed_next;
243
244 if (ed->ed_next)
245 ed->ed_next->ed_prev = ed->ed_prev;
246
247 if (ahcd->ed_tails[ed->type] == ed)
248 ahcd->ed_tails[ed->type] = ed->ed_prev;
249 }
250
251 /*-------------------------------------------------------------------------*/
252
253 static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
254 {
255 struct ed *ed;
256 struct td *td;
257
258 ed = ed_alloc(ahcd, GFP_ATOMIC);
259 if (!ed)
260 goto err;
261
262 /* dummy td; end of td list for this ed */
263 td = td_alloc(ahcd, GFP_ATOMIC);
264 if (!td)
265 goto err_free_ed;
266
267 switch (type) {
268 case PIPE_INTERRUPT:
269 info |= ED_INT;
270 break;
271 case PIPE_ISOCHRONOUS:
272 info |= ED_ISO;
273 break;
274 }
275
276 ed->dummy = td;
277 ed->state = ED_IDLE;
278 ed->type = type;
279
280 ed->hwINFO = cpu_to_hc32(ahcd, info);
281 ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
282 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
283
284 return ed;
285
286 err_free_ed:
287 ed_free(ahcd, ed);
288 err:
289 return NULL;
290 }
291
292 /* get and maybe (re)init an endpoint. init _should_ be done only as part
293 * of enumeration, usb_set_configuration() or usb_set_interface().
294 */
295 static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
296 struct usb_device *udev, unsigned int pipe, int interval)
297 {
298 struct ed *ed;
299 unsigned long flags;
300
301 spin_lock_irqsave(&ahcd->lock, flags);
302
303 ed = ep->hcpriv;
304 if (!ed) {
305 u32 info;
306
307 /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
308 * suceeds ... otherwise we wouldn't need "pipe".
309 */
310 info = usb_pipedevice(pipe);
311 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
312 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
313 if (udev->speed == USB_SPEED_FULL)
314 info |= ED_SPEED_FULL;
315
316 ed = ed_create(ahcd, usb_pipetype(pipe), info);
317 if (ed)
318 ep->hcpriv = ed;
319 }
320
321 spin_unlock_irqrestore(&ahcd->lock, flags);
322
323 return ed;
324 }
325
326 /*-------------------------------------------------------------------------*/
327
328 /* request unlinking of an endpoint from an operational HC.
329 * put the ep on the rm_list
330 * real work is done at the next start frame (SOFI) hardware interrupt
331 * caller guarantees HCD is running, so hardware access is safe,
332 * and that ed->state is ED_OPER
333 */
334 static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
335 {
336 ed->hwINFO |= cpu_to_hc32 (ahcd, ED_DEQUEUE);
337 ed_deschedule(ahcd, ed);
338
339 /* add this ED into the remove list */
340 ed->ed_rm_next = ahcd->ed_rm_list;
341 ahcd->ed_rm_list = ed;
342
343 /* enable SOF interrupt */
344 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
345 admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
346 /* flush those writes */
347 admhc_writel_flush(ahcd);
348
349 /* SOF interrupt might get delayed; record the frame counter value that
350 * indicates when the HC isn't looking at it, so concurrent unlinks
351 * behave. frame_no wraps every 2^16 msec, and changes right before
352 * SOF is triggered.
353 */
354 ed->tick = admhc_frame_no(ahcd) + 1;
355 }
356
357 /*-------------------------------------------------------------------------*
358 * TD handling functions
359 *-------------------------------------------------------------------------*/
360
361 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
362
363 static void
364 td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
365 struct urb *urb, int index)
366 {
367 struct td *td, *td_pt;
368 struct urb_priv *urb_priv = urb->hcpriv;
369 int hash;
370 u32 cbl = 0;
371
372 #if 1
373 if (index == (urb_priv->td_cnt - 1) &&
374 ((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
375 cbl |= TD_IE;
376 #else
377 if (index == (urb_priv->td_cnt - 1))
378 cbl |= TD_IE;
379 #endif
380
381 /* use this td as the next dummy */
382 td_pt = urb_priv->td[index];
383
384 /* fill the old dummy TD */
385 td = urb_priv->td[index] = urb_priv->ed->dummy;
386 urb_priv->ed->dummy = td_pt;
387
388 td->ed = urb_priv->ed;
389 td->next_dl_td = NULL;
390 td->index = index;
391 td->urb = urb;
392 td->data_dma = data;
393 if (!len)
394 data = 0;
395
396 if (data)
397 cbl |= (len & TD_BL_MASK);
398
399 info |= TD_OWN;
400
401 /* setup hardware specific fields */
402 td->hwINFO = cpu_to_hc32(ahcd, info);
403 td->hwDBP = cpu_to_hc32(ahcd, data);
404 td->hwCBL = cpu_to_hc32(ahcd, cbl);
405 td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
406
407 /* append to queue */
408 list_add_tail(&td->td_list, &td->ed->td_list);
409
410 /* hash it for later reverse mapping */
411 hash = TD_HASH_FUNC(td->td_dma);
412 td->td_hash = ahcd->td_hash[hash];
413 ahcd->td_hash[hash] = td;
414
415 /* HC might read the TD (or cachelines) right away ... */
416 wmb();
417 td->ed->hwTailP = td->hwNextTD;
418 }
419
420 /*-------------------------------------------------------------------------*/
421
422 /* Prepare all TDs of a transfer, and queue them onto the ED.
423 * Caller guarantees HC is active.
424 * Usually the ED is already on the schedule, so TDs might be
425 * processed as soon as they're queued.
426 */
427 static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
428 {
429 struct urb_priv *urb_priv = urb->hcpriv;
430 dma_addr_t data;
431 int data_len = urb->transfer_buffer_length;
432 int cnt = 0;
433 u32 info = 0;
434 int is_out = usb_pipeout(urb->pipe);
435 int periodic = 0;
436 u32 toggle = 0;
437 struct td *td;
438
439 /* OHCI handles the bulk/interrupt data toggles itself. We just
440 * use the device toggle bits for resetting, and rely on the fact
441 * that resetting toggle is meaningless if the endpoint is active.
442 */
443
444 if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
445 toggle = TD_T_CARRY;
446 } else {
447 toggle = TD_T_DATA0;
448 usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
449 is_out, 1);
450 }
451
452 urb_priv->td_idx = 0;
453 list_add(&urb_priv->pending, &ahcd->pending);
454
455 if (data_len)
456 data = urb->transfer_dma;
457 else
458 data = 0;
459
460 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
461 * using TD_CC_GET, as well as by seeing them on the done list.
462 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
463 */
464 switch (urb_priv->ed->type) {
465 case PIPE_INTERRUPT:
466 info = is_out
467 ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
468 : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
469
470 /* setup service interval and starting frame number */
471 info |= (urb->start_frame & TD_FN_MASK);
472 info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
473
474 td_fill(ahcd, info, data, data_len, urb, cnt);
475 cnt++;
476
477 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
478 break;
479
480 case PIPE_BULK:
481 info = is_out
482 ? TD_SCC_NOTACCESSED | TD_DP_OUT
483 : TD_SCC_NOTACCESSED | TD_DP_IN;
484
485 /* TDs _could_ transfer up to 8K each */
486 while (data_len > TD_DATALEN_MAX) {
487 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
488 data, TD_DATALEN_MAX, urb, cnt);
489 data += TD_DATALEN_MAX;
490 data_len -= TD_DATALEN_MAX;
491 cnt++;
492 }
493
494 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
495 data_len, urb, cnt);
496 cnt++;
497
498 if ((urb->transfer_flags & URB_ZERO_PACKET)
499 && (cnt < urb_priv->td_cnt)) {
500 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
501 0, 0, urb, cnt);
502 cnt++;
503 }
504 break;
505
506 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
507 * any DATA phase works normally, and the STATUS ack is special.
508 */
509 case PIPE_CONTROL:
510 /* fill a TD for the setup */
511 info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
512 td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
513
514 if (data_len > 0) {
515 /* fill a TD for the data */
516 info = TD_SCC_NOTACCESSED | TD_T_DATA1;
517 info |= is_out ? TD_DP_OUT : TD_DP_IN;
518 /* NOTE: mishandles transfers >8K, some >4K */
519 td_fill(ahcd, info, data, data_len, urb, cnt++);
520 }
521
522 /* fill a TD for the ACK */
523 info = (is_out || data_len == 0)
524 ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
525 : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
526 td_fill(ahcd, info, data, 0, urb, cnt++);
527
528 break;
529
530 /* ISO has no retransmit, so no toggle;
531 * Each TD could handle multiple consecutive frames (interval 1);
532 * we could often reduce the number of TDs here.
533 */
534 case PIPE_ISOCHRONOUS:
535 info = TD_SCC_NOTACCESSED;
536 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
537 int frame = urb->start_frame;
538
539 frame += cnt * urb->interval;
540 frame &= TD_FN_MASK;
541 td_fill(ahcd, info | frame,
542 data + urb->iso_frame_desc[cnt].offset,
543 urb->iso_frame_desc[cnt].length, urb, cnt);
544 }
545 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
546 break;
547 }
548
549 if (urb_priv->td_cnt != cnt)
550 admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
551 }
552
553 /*-------------------------------------------------------------------------*
554 * Done List handling functions
555 *-------------------------------------------------------------------------*/
556
557 /* calculate transfer length/status and update the urb
558 * PRECONDITION: irqsafe (only for urb->status locking)
559 */
560 static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
561 {
562 struct urb_priv *urb_priv = urb->hcpriv;
563 u32 info = hc32_to_cpup(ahcd, &td->hwINFO);
564 int type = usb_pipetype(urb->pipe);
565 int cc;
566
567 cc = TD_CC_GET(info);
568
569 /* ISO ... drivers see per-TD length/status */
570 if (type == PIPE_ISOCHRONOUS) {
571 #if 0
572 /* TODO */
573 int dlen = 0;
574
575 /* NOTE: assumes FC in tdINFO == 0, and that
576 * only the first of 0..MAXPSW psws is used.
577 */
578
579 cc = TD_CC_GET(td);
580 if (tdINFO & TD_CC) /* hc didn't touch? */
581 return;
582
583 if (usb_pipeout (urb->pipe))
584 dlen = urb->iso_frame_desc [td->index].length;
585 else {
586 /* short reads are always OK for ISO */
587 if (cc == TD_DATAUNDERRUN)
588 cc = TD_CC_NOERROR;
589 dlen = tdPSW & 0x3ff;
590 }
591 urb->actual_length += dlen;
592 urb->iso_frame_desc [td->index].actual_length = dlen;
593 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
594
595 if (cc != TD_CC_NOERROR)
596 admhc_vdbg (ahcd,
597 "urb %p iso td %p (%d) len %d cc %d\n",
598 urb, td, 1 + td->index, dlen, cc);
599 #endif
600 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
601 * except that "setup" bytes aren't counted and "short" transfers
602 * might not be reported as errors.
603 */
604 } else {
605 u32 bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
606 u32 tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
607
608 /* update packet status if needed (short is normally ok) */
609 if (cc == TD_CC_DATAUNDERRUN
610 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
611 cc = TD_CC_NOERROR;
612
613 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0) {
614 spin_lock(&urb->lock);
615 if (urb->status == -EINPROGRESS)
616 urb->status = cc_to_error[cc];
617 spin_unlock(&urb->lock);
618 }
619
620 /* count all non-empty packets except control SETUP packet */
621 if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) {
622 urb->actual_length += tdDBP - td->data_dma + bl;
623 }
624
625 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
626 admhc_vdbg(ahcd,
627 "urb %p td %p (%d) cc %d, len=%d/%d\n",
628 urb, td, td->index, cc,
629 urb->actual_length,
630 urb->transfer_buffer_length);
631 }
632
633 list_del(&td->td_list);
634 urb_priv->td_idx++;
635
636 return cc;
637 }
638
639 /*-------------------------------------------------------------------------*/
640
641 static inline struct td *
642 ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
643 {
644 struct urb *urb = td->urb;
645 struct ed *ed = td->ed;
646 struct list_head *tmp = td->td_list.next;
647 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ahcd, ED_C);
648
649 admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
650 /* clear ed halt; this is the td that caused it, but keep it inactive
651 * until its urb->complete() has a chance to clean up.
652 */
653 ed->hwINFO |= cpu_to_hc32 (ahcd, ED_SKIP);
654 wmb();
655 ed->hwHeadP &= ~cpu_to_hc32 (ahcd, ED_H);
656
657 /* put any later tds from this urb onto the donelist, after 'td',
658 * order won't matter here: no errors, and nothing was transferred.
659 * also patch the ed so it looks as if those tds completed normally.
660 */
661 while (tmp != &ed->td_list) {
662 struct td *next;
663 __hc32 info;
664
665 next = list_entry(tmp, struct td, td_list);
666 tmp = next->td_list.next;
667
668 if (next->urb != urb)
669 break;
670
671 /* NOTE: if multi-td control DATA segments get supported,
672 * this urb had one of them, this td wasn't the last td
673 * in that segment (TD_R clear), this ed halted because
674 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
675 * then we need to leave the control STATUS packet queued
676 * and clear ED_SKIP.
677 */
678 info = next->hwINFO;
679 #if 0 /* FIXME */
680 info |= cpu_to_hc32 (ahcd, TD_DONE);
681 #endif
682 info &= ~cpu_to_hc32 (ahcd, TD_CC);
683 next->hwINFO = info;
684
685 next->next_dl_td = rev;
686 rev = next;
687
688 ed->hwHeadP = next->hwNextTD | toggle;
689 }
690
691 /* help for troubleshooting: report anything that
692 * looks odd ... that doesn't include protocol stalls
693 * (or maybe some other things)
694 */
695 switch (cc) {
696 case TD_CC_DATAUNDERRUN:
697 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
698 break;
699 /* fallthrough */
700 case TD_CC_STALL:
701 if (usb_pipecontrol(urb->pipe))
702 break;
703 /* fallthrough */
704 default:
705 admhc_dbg (ahcd,
706 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
707 urb, urb->dev->devpath,
708 usb_pipeendpoint (urb->pipe),
709 usb_pipein (urb->pipe) ? "in" : "out",
710 hc32_to_cpu(ahcd, td->hwINFO),
711 cc, cc_to_error [cc]);
712 }
713
714 return rev;
715 }
716
717 /*-------------------------------------------------------------------------*/
718
719 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
720 static void
721 finish_unlinks(struct admhcd *ahcd, u16 tick)
722 {
723 struct ed *ed, **last;
724
725 rescan_all:
726 for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
727 struct list_head *entry, *tmp;
728 int completed, modified;
729 __hc32 *prev;
730
731 /* only take off EDs that the HC isn't using, accounting for
732 * frame counter wraps and EDs with partially retired TDs
733 */
734 if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
735 if (tick_before (tick, ed->tick)) {
736 skip_ed:
737 last = &ed->ed_rm_next;
738 continue;
739 }
740
741 if (!list_empty (&ed->td_list)) {
742 struct td *td;
743 u32 head;
744
745 td = list_entry(ed->td_list.next, struct td,
746 td_list);
747 head = hc32_to_cpu(ahcd, ed->hwHeadP) &
748 TD_MASK;
749
750 /* INTR_WDH may need to clean up first */
751 if (td->td_dma != head)
752 goto skip_ed;
753 }
754 }
755
756 /* reentrancy: if we drop the schedule lock, someone might
757 * have modified this list. normally it's just prepending
758 * entries (which we'd ignore), but paranoia won't hurt.
759 */
760 *last = ed->ed_rm_next;
761 ed->ed_rm_next = NULL;
762 modified = 0;
763
764 /* unlink urbs as requested, but rescan the list after
765 * we call a completion since it might have unlinked
766 * another (earlier) urb
767 *
768 * When we get here, the HC doesn't see this ed. But it
769 * must not be rescheduled until all completed URBs have
770 * been given back to the driver.
771 */
772 rescan_this:
773 completed = 0;
774 prev = &ed->hwHeadP;
775 list_for_each_safe (entry, tmp, &ed->td_list) {
776 struct td *td;
777 struct urb *urb;
778 struct urb_priv *urb_priv;
779 __hc32 savebits;
780
781 td = list_entry(entry, struct td, td_list);
782 urb = td->urb;
783 urb_priv = td->urb->hcpriv;
784
785 if (urb->status == -EINPROGRESS) {
786 prev = &td->hwNextTD;
787 continue;
788 }
789
790 if ((urb_priv) == NULL)
791 continue;
792
793 /* patch pointer hc uses */
794 savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
795 *prev = td->hwNextTD | savebits;
796
797 /* HC may have partly processed this TD */
798 urb_print(urb, "PARTIAL", 1);
799 td_done(ahcd, urb, td);
800
801 /* if URB is done, clean up */
802 if (urb_priv->td_idx == urb_priv->td_cnt) {
803 modified = completed = 1;
804 finish_urb(ahcd, urb);
805 }
806 }
807 if (completed && !list_empty (&ed->td_list))
808 goto rescan_this;
809
810 /* ED's now officially unlinked, hc doesn't see */
811 ed->state = ED_IDLE;
812 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
813 ed->hwNextED = 0;
814 wmb ();
815 ed->hwINFO &= ~cpu_to_hc32 (ahcd, ED_SKIP | ED_DEQUEUE);
816
817 /* but if there's work queued, reschedule */
818 if (!list_empty (&ed->td_list)) {
819 if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
820 ed_schedule(ahcd, ed);
821 }
822
823 if (modified)
824 goto rescan_all;
825 }
826 }
827
828 /*-------------------------------------------------------------------------*/
829
830 /*
831 * Process normal completions (error or success) and clean the schedules.
832 *
833 * This is the main path for handing urbs back to drivers. The only other
834 * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
835 * scanning the (re-reversed) donelist as this does.
836 */
837
838 static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb)
839 {
840 struct list_head *entry,*tmp;
841 struct urb_priv *urb_priv = urb->hcpriv;
842 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ahcd, ED_C);
843
844
845 #ifdef ADMHC_VERBOSE_DEBUG
846 admhc_dump_ed(ahcd, "UNHALT", ed, 0);
847 #endif
848 /* clear ed halt; this is the td that caused it, but keep it inactive
849 * until its urb->complete() has a chance to clean up.
850 */
851 ed->hwINFO |= cpu_to_hc32 (ahcd, ED_SKIP);
852 wmb();
853 ed->hwHeadP &= ~cpu_to_hc32 (ahcd, ED_H);
854
855 list_for_each_safe(entry, tmp, &ed->td_list) {
856 struct td *td = list_entry(entry, struct td, td_list);
857 __hc32 info;
858
859 if (td->urb != urb)
860 break;
861
862 info = td->hwINFO;
863 info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN);
864 td->hwINFO = info;
865
866 ed->hwHeadP = td->hwNextTD | toggle;
867 wmb();
868 }
869
870 }
871
872 static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed)
873 {
874 return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H);
875 }
876
877 static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed,
878 struct td *td)
879 {
880 return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) ==
881 (hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK));
882 }
883
884 static void ed_update(struct admhcd *ahcd, struct ed *ed)
885 {
886 struct list_head *entry,*tmp;
887
888 #ifdef ADMHC_VERBOSE_DEBUG
889 admhc_dump_ed(ahcd, "UPDATE", ed, 0);
890 #endif
891
892 list_for_each_safe(entry, tmp, &ed->td_list) {
893 struct td *td = list_entry(entry, struct td, td_list);
894 struct urb *urb = td->urb;
895 struct urb_priv *urb_priv = urb->hcpriv;
896 int cc;
897
898 if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
899 break;
900
901 /* update URB's length and status from TD */
902 cc = td_done(ahcd, urb, td);
903 if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td))
904 ed_unhalt(ahcd, ed, urb);
905
906 /* If all this urb's TDs are done, call complete() */
907 if (urb_priv->td_idx == urb_priv->td_cnt)
908 finish_urb(ahcd, urb);
909
910 /* clean schedule: unlink EDs that are no longer busy */
911 if (list_empty(&ed->td_list)) {
912 if (ed->state == ED_OPER)
913 start_ed_unlink(ahcd, ed);
914
915 /* ... reenabling halted EDs only after fault cleanup */
916 } else if ((ed->hwINFO & cpu_to_hc32 (ahcd,
917 ED_SKIP | ED_DEQUEUE))
918 == cpu_to_hc32 (ahcd, ED_SKIP)) {
919 td = list_entry(ed->td_list.next, struct td, td_list);
920 #if 0
921 if (!(td->hwINFO & cpu_to_hc32 (ahcd, TD_DONE))) {
922 ed->hwINFO &= ~cpu_to_hc32 (ahcd, ED_SKIP);
923 /* ... hc may need waking-up */
924 switch (ed->type) {
925 case PIPE_CONTROL:
926 admhc_writel (ahcd, OHCI_CLF,
927 &ahcd->regs->cmdstatus);
928 break;
929 case PIPE_BULK:
930 admhc_writel (ahcd, OHCI_BLF,
931 &ahcd->regs->cmdstatus);
932 break;
933 }
934 }
935 #else
936 if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
937 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
938 #endif
939 }
940
941 }
942 }
943
944 /* there are some tds completed; called in_irq(), with HCD locked */
945 static void admhc_td_complete(struct admhcd *ahcd)
946 {
947 struct ed *ed;
948
949 for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
950 if (ed->state != ED_OPER)
951 continue;
952
953 ed_update(ahcd, ed);
954 }
955 }
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