target/linux/adm8668/files/arch/mips/include/asm/mach-adm8668/adm8668.h

   1 /************************************************************************
   2  *
   3  *    Copyright (c) 2005
   4  *    Infineon Technologies AG
   5  *    St. Martin Strasse 53; 81669 Muenchen; Germany
   6  *
   7  ************************************************************************/
   8
   9 #ifndef  __ADM8668_H__
  10 #define  __ADM8668_H__
  11
  12 #define SYS_CLOCK               175000000
  13
  14 /*=======================  Physical Memory Map  ============================*/
  15 #define ADM8668_SDRAM_BASE      0
  16 #define ADM8668_SMEM1_BASE      0x10000000
  17 #define ADM8668_MPMC_BASE       0x11000000
  18 #define ADM8668_USB_BASE        0x11200000
  19 #define ADM8668_CONFIG_BASE     0x11400000
  20 #define ADM8668_WAN_BASE        0x11600000
  21 #define ADM8668_WLAN_BASE       0x11800000
  22 #define ADM8668_LAN_BASE        0x11A00000
  23 #define ADM8668_INTC_BASE       0x1E000000
  24 #define ADM8668_TMR_BASE        0x1E200000
  25 #define ADM8668_UART0_BASE      0x1E400000
  26 #define ADM8668_SMEM0_BASE      0x1FC00000
  27 #define ADM8668_NAND_BASE       0x1FFFFF00
  28
  29 #define PCICFG_BASE             0x12200000
  30 #define PCIDAT_BASE             0x12400000
  31
  32 /** onboard uart **/
  33 #define ADM8668_UARTCLK_FREQ    62500000
  34
  35 /* interrupt controller */
  36 #define IRQ_STATUS_REG          0x00    /* Read */
  37 #define IRQ_ENABLE_REG          0x08    /* Read/Write */
  38 #define IRQ_DISABLE_REG         0x0C    /* Write */
  39
  40 /* interrupt levels */
  41 #define INT_LVL_SWI             1
  42 #define INT_LVL_COMMS_RX        2
  43 #define INT_LVL_COMMS_TX        3
  44 #define INT_LVL_TIMERINT0       4
  45 #define INT_LVL_TIMERINT1       5
  46 #define INT_LVL_UART0           6
  47 #define INT_LVL_LAN             7
  48 #define INT_LVL_WAN             8
  49 #define INT_LVL_WLAN            9
  50 #define INT_LVL_GPIO            10
  51 #define INT_LVL_IDE             11
  52 #define INT_LVL_PCI2            12
  53 #define INT_LVL_PCI1            13
  54 #define INT_LVL_PCI0            14
  55 #define INT_LVL_USB             15
  56 #define INT_LVL_MAX             INT_LVL_USB
  57
  58 /* register access macros */
  59 #define ADM8668_INTC_REG(_reg)  \
  60         (*((volatile unsigned long *)(KSEG1ADDR(ADM8668_INTC_BASE + (_reg)))))
  61 #define ADM8668_LAN_REG(_reg)           \
  62         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_LAN_BASE + (_reg)))))
  63 #define ADM8668_WAN_REG(_reg)           \
  64         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WAN_BASE + (_reg)))))
  65 #define ADM8668_WLAN_REG(_reg)          \
  66         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WLAN_BASE + (_reg)))))
  67 #define ADM8668_CONFIG_REG(_reg)        \
  68         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_CONFIG_BASE + (_reg)))))
  69
  70 /* lan registers */
  71 #define NETCSR6                 0x30
  72 #define NETCSR7                 0x38
  73 #define NETCSR37                0xF8
  74
  75 /* known/used CPU configuration registers */
  76 #define ADM8668_CR0             0x00
  77 #define ADM8668_CR1             0x04
  78 #define ADM8668_CR3             0x0C
  79
  80 /** For GPIO control **/
  81 #define GPIO_REG                0x5C    /* on WLAN */
  82 #define CRGPIO_REG              0x20    /* on CPU */
  83 #define GPIO0_OUTPUT_ENABLE     0x1000
  84 #define GPIO1_OUTPUT_ENABLE     0x2000
  85 #define GPIO2_OUTPUT_ENABLE     0x4000
  86 #define GPIO_OUTPUT_ENABLE_ALL  0x7000
  87 #define GPIO0_OUTPUT_1          0x40
  88 #define GPIO1_OUTPUT_1          0x80
  89 #define GPIO2_OUTPUT_1          0x100
  90 #define GPIO0_INPUT_1           0x1
  91 #define GPIO1_INPUT_1           0x2
  92 #define GPIO2_INPUT_1           0x4
  93
  94 #define GPIO_SET_HI(num)        \
  95         ADM8668_WLAN_REG(GPIO_REG) |= (1 << (6 + num))
  96
  97 #define GPIO_SET_LOW(num)       \
  98         ADM8668_WLAN_REG(GPIO_REG) &= ~(1 << (6 + num))
  99
 100 #define GPIO_TOGGLE(num)        \
 101         ADM8668_WLAN_REG(GPIO_REG) ^= (1 << (6 + num))
 102
 103 #define CRGPIO_SET_HI(num)      \
 104         ADM8668_CONFIG_REG(CRGPIO_REG) |= (1 << (6 + num))
 105
 106 #define CRGPIO_SET_LOW(num)     \
 107         ADM8668_CONFIG_REG(CRGPIO_REG) &= ~(1 << (6 + num))
 108
 109 #define CRGPIO_TOGGLE(num)      \
 110         ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
 111
 112 void adm8668_init_clocks(void);
 113
 114 #endif /* __ADM8668_H__ */