move clock frequencies into clock driver
[openwrt/openwrt.git] / target / linux / adm8668 / files / arch / mips / include / asm / mach-adm8668 / adm8668.h
1 /************************************************************************
2 *
3 * Copyright (c) 2005
4 * Infineon Technologies AG
5 * St. Martin Strasse 53; 81669 Muenchen; Germany
6 *
7 ************************************************************************/
8
9 #ifndef __ADM8668_H__
10 #define __ADM8668_H__
11
12 /*======================= Physical Memory Map ============================*/
13 #define ADM8668_SDRAM_BASE 0
14 #define ADM8668_SMEM1_BASE 0x10000000
15 #define ADM8668_MPMC_BASE 0x11000000
16 #define ADM8668_USB_BASE 0x11200000
17 #define ADM8668_CONFIG_BASE 0x11400000
18 #define ADM8668_WAN_BASE 0x11600000
19 #define ADM8668_WLAN_BASE 0x11800000
20 #define ADM8668_LAN_BASE 0x11A00000
21 #define ADM8668_INTC_BASE 0x1E000000
22 #define ADM8668_TMR_BASE 0x1E200000
23 #define ADM8668_UART0_BASE 0x1E400000
24 #define ADM8668_SMEM0_BASE 0x1FC00000
25 #define ADM8668_NAND_BASE 0x1FFFFF00
26
27 #define ADM8668_PCICFG_BASE 0x12200000
28 #define ADM8668_PCIDAT_BASE 0x12400000
29
30 /* interrupt levels */
31 #define INT_LVL_SWI 1
32 #define INT_LVL_COMMS_RX 2
33 #define INT_LVL_COMMS_TX 3
34 #define INT_LVL_TIMERINT0 4
35 #define INT_LVL_TIMERINT1 5
36 #define INT_LVL_UART0 6
37 #define INT_LVL_LAN 7
38 #define INT_LVL_WAN 8
39 #define INT_LVL_WLAN 9
40 #define INT_LVL_GPIO 10
41 #define INT_LVL_IDE 11
42 #define INT_LVL_PCI2 12
43 #define INT_LVL_PCI1 13
44 #define INT_LVL_PCI0 14
45 #define INT_LVL_USB 15
46 #define INT_LVL_MAX INT_LVL_USB
47
48 /* register access macros */
49 #define ADM8668_LAN_REG(_reg) \
50 (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_LAN_BASE + (_reg)))))
51 #define ADM8668_WAN_REG(_reg) \
52 (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WAN_BASE + (_reg)))))
53 #define ADM8668_WLAN_REG(_reg) \
54 (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WLAN_BASE + (_reg)))))
55 #define ADM8668_CONFIG_REG(_reg) \
56 (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_CONFIG_BASE + (_reg)))))
57
58 /* lan registers */
59 #define NETCSR6 0x30
60 #define NETCSR7 0x38
61 #define NETCSR37 0xF8
62
63 /* known/used CPU configuration registers */
64 #define ADM8668_CR0 0x00
65 #define ADM8668_CR1 0x04
66 #define ADM8668_CR3 0x0C
67
68 /** For GPIO control **/
69 #define GPIO_REG 0x5C /* on WLAN */
70 #define CRGPIO_REG 0x20 /* on CPU */
71 #define GPIO0_OUTPUT_ENABLE 0x1000
72 #define GPIO1_OUTPUT_ENABLE 0x2000
73 #define GPIO2_OUTPUT_ENABLE 0x4000
74 #define GPIO_OUTPUT_ENABLE_ALL 0x7000
75 #define GPIO0_OUTPUT_1 0x40
76 #define GPIO1_OUTPUT_1 0x80
77 #define GPIO2_OUTPUT_1 0x100
78 #define GPIO0_INPUT_1 0x1
79 #define GPIO1_INPUT_1 0x2
80 #define GPIO2_INPUT_1 0x4
81
82 #define GPIO_SET_HI(num) \
83 ADM8668_WLAN_REG(GPIO_REG) |= (1 << (6 + num))
84
85 #define GPIO_SET_LOW(num) \
86 ADM8668_WLAN_REG(GPIO_REG) &= ~(1 << (6 + num))
87
88 #define GPIO_TOGGLE(num) \
89 ADM8668_WLAN_REG(GPIO_REG) ^= (1 << (6 + num))
90
91 #define CRGPIO_SET_HI(num) \
92 ADM8668_CONFIG_REG(CRGPIO_REG) |= (1 << (6 + num))
93
94 #define CRGPIO_SET_LOW(num) \
95 ADM8668_CONFIG_REG(CRGPIO_REG) &= ~(1 << (6 + num))
96
97 #define CRGPIO_TOGGLE(num) \
98 ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
99
100 void adm8668_init_clocks(void);
101
102 #endif /* __ADM8668_H__ */