mediatek: mt7988a: sync dts compatible string
[openwrt/openwrt.git] / target / linux / apm821xx / dts / apm82181.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Device Tree for Bluestone (APM821xx) board.
4 *
5 * Copyright (c) 2010, Applied Micro Circuits Corporation
6 * Author: Tirumala R Marri <tmarri@apm.com>
7 */
8
9 #include <dt-bindings/dma/dw-dmac.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13
14 / {
15 #address-cells = <2>;
16 #size-cells = <1>;
17 dcr-parent = <&{/cpus/cpu@0}>;
18 compatible = "apm,bluestone";
19
20 aliases {
21 ethernet0 = &EMAC0; /* needed for BSP u-boot */
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 CPU0: cpu@0 {
29 device_type = "cpu";
30 model = "PowerPC,apm82181";
31 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
34 i-cache-line-size = <32>;
35 d-cache-line-size = <32>;
36 i-cache-size = <32768>;
37 d-cache-size = <32768>;
38 dcr-controller;
39 dcr-access-method = "native";
40 next-level-cache = <&L2C0>;
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
47 };
48
49 UIC0: interrupt-controller0 {
50 compatible = "apm,uic-apm82181", "ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 UIC1: interrupt-controller1 {
60 compatible = "apm,uic-apm82181", "ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <0x1e IRQ_TYPE_LEVEL_HIGH>,
68 <0x1f IRQ_TYPE_LEVEL_HIGH>; /* cascade */
69 interrupt-parent = <&UIC0>;
70 };
71
72 UIC2: interrupt-controller2 {
73 compatible = "apm,uic-apm82181", "ibm,uic";
74 interrupt-controller;
75 cell-index = <2>;
76 dcr-reg = <0x0e0 0x009>;
77 #address-cells = <0>;
78 #size-cells = <0>;
79 #interrupt-cells = <2>;
80 interrupts = <0x0a IRQ_TYPE_LEVEL_HIGH>,
81 <0x0b IRQ_TYPE_LEVEL_HIGH>; /* cascade */
82 interrupt-parent = <&UIC0>;
83 };
84
85 UIC3: interrupt-controller3 {
86 compatible = "apm,uic-apm82181","ibm,uic";
87 interrupt-controller;
88 cell-index = <3>;
89 dcr-reg = <0x0f0 0x009>;
90 #address-cells = <0>;
91 #size-cells = <0>;
92 #interrupt-cells = <2>;
93 interrupts = <0x10 IRQ_TYPE_LEVEL_HIGH>,
94 <0x11 IRQ_TYPE_LEVEL_HIGH>; /* cascade */
95 interrupt-parent = <&UIC0>;
96 };
97
98 OCM1: ocm@400040000 {
99 compatible = "apm,ocm-apm82181", "ibm,ocm";
100 status = "okay";
101 cell-index = <1>;
102 /* configured in U-Boot */
103 reg = <4 0x00040000 0x8000>; /* 32K */
104 };
105
106 SDR0: sdr {
107 compatible = "apm,sdr-apm82181", "ibm,sdr-460ex";
108 dcr-reg = <0x00e 0x002>;
109 };
110
111 CPR0: cpr {
112 compatible = "apm,cpr-apm82181", "ibm,cpr-460ex";
113 dcr-reg = <0x00c 0x002>;
114 };
115
116 L2C0: l2c {
117 compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
118 dcr-reg = <0x020 0x008
119 0x030 0x008>;
120 cache-line-size = <32>;
121 cache-size = <262144>;
122 interrupt-parent = <&UIC1>;
123 interrupts = <0x0b IRQ_TYPE_EDGE_RISING>;
124 };
125
126 CPM0: cpm {
127 compatible = "ibm,cpm-apm821xx", "ibm,cpm";
128 cell-index = <0>;
129 dcr-reg = <0x160 0x003>;
130 pm-cpu = <0x02000000>;
131 pm-doze = <0x302570F0>;
132 pm-nap = <0x302570F0>;
133 pm-deepsleep = <0x302570F0>;
134 pm-iic-device = <&IIC0>;
135 pm-emac-device = <&EMAC0>;
136 unused-units = <0x00000100>;
137 idle-doze = <0x02000000>;
138 standby = <0xfeff791d>;
139 };
140
141 plb {
142 compatible = "apm,plb-apm82181", "ibm,plb-460ex", "ibm,plb4";
143 #address-cells = <2>;
144 #size-cells = <1>;
145 ranges; /* Filled in by U-Boot */
146 clock-frequency = <0>; /* Filled in by U-Boot */
147
148 SDRAM0: sdram {
149 compatible = "apm,sdram-apm82181", "ibm,sdram-460ex", "ibm,sdram-405gp";
150 dcr-reg = <0x010 0x002>;
151 };
152
153 RTC: rtc {
154 compatible = "ibm,rtc";
155 dcr-reg = <0x240 0x009>;
156 interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-parent = <&UIC2>;
158 status = "disabled";
159 };
160
161 TRNG: trng@110000 {
162 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng", "amcc, ppc4xx-trng";
163 reg = <4 0x00110000 0x100>;
164 interrupt-parent = <&UIC1>;
165 interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
166 status = "disabled";
167 };
168
169 PKA: pka@114000 {
170 compatible = "ppc4xx-pka", "amcc,ppc4xx-pka", "amcc, ppc4xx-pka";
171 reg = <4 0x00114000 0x4000>;
172 interrupt-parent = <&UIC0>;
173 interrupts = <0x14 IRQ_TYPE_EDGE_RISING>;
174 status = "disabled";
175 };
176
177 CRYPTO: crypto@180000 {
178 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
179 reg = <4 0x00180000 0x80400>;
180 interrupt-parent = <&UIC0>;
181 interrupts = <0x1d IRQ_TYPE_LEVEL_HIGH>;
182 status = "disabled"; /* hardware option */
183 };
184
185 MAL0: mcmal {
186 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
187 descriptor-memory = "ocm";
188 dcr-reg = <0x180 0x062>;
189 num-tx-chans = <1>;
190 num-rx-chans = <1>;
191 #address-cells = <0>;
192 #size-cells = <0>;
193 interrupt-parent = <&UIC2>;
194 interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>,
195 <0x07 IRQ_TYPE_LEVEL_HIGH>,
196 <0x03 IRQ_TYPE_LEVEL_HIGH>,
197 <0x04 IRQ_TYPE_LEVEL_HIGH>,
198 <0x05 IRQ_TYPE_LEVEL_HIGH>,
199 <0x08 IRQ_TYPE_EDGE_FALLING>,
200 <0x09 IRQ_TYPE_EDGE_FALLING>,
201 <0x0c IRQ_TYPE_EDGE_FALLING>,
202 <0x0d IRQ_TYPE_EDGE_FALLING>;
203 interrupt-names = "txeob", "rxeob", "serr",
204 "txde", "rxde",
205 "tx0coal", "tx1coal",
206 "rx0coal", "rx1coal";
207 };
208
209 POB0: opb {
210 compatible = "ibm,opb-460ex", "ibm,opb";
211 #address-cells = <1>;
212 #size-cells = <1>;
213 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
214 clock-frequency = <0>; /* Filled in by U-Boot */
215
216 EBC0: ebc {
217 compatible = "ibm,ebc-460ex", "ibm,ebc";
218 dcr-reg = <0x012 0x002>;
219 #address-cells = <2>;
220 #size-cells = <1>;
221 clock-frequency = <0>; /* Filled in by U-Boot */
222 /* ranges property is supplied by U-Boot */
223 ranges = <0x00000003 0x00000000 0xe0000000 0x8000000>;
224 interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>;
225 interrupt-parent = <&UIC1>;
226
227 nor_flash@0,0 {
228 compatible = "cfi-flash";
229 bank-width = <1>;
230 reg = <0x00000000 0x00000000 0x00100000>;
231 #address-cells = <1>;
232 #size-cells = <1>;
233 status = "disabled";
234 };
235
236 ndfc: ndfc@1,0 {
237 compatible = "ibm,ndfc";
238 reg = <00000003 00000000 00002000>;
239 ccr = <0x00001000>;
240 bank-settings = <0x80002222>;
241 status = "disabled";
242
243 nand {
244 /*
245 * These are the same fixed "MAGIC" values
246 * settings as in the drivers code.
247 * They are the same for all devices that
248 * have NAND.
249 */
250 nand-ecc-engine = <&ndfc>;
251 nand-ecc-algo = "hamming";
252 nand-ecc-step-size = <256>;
253 nand-ecc-strength = <1>;
254 };
255 };
256 };
257
258 UART0: serial@ef600300 {
259 /*
260 * AMCC's BSP u-boot scans for the "ns16550"
261 * compatible, without it, u-boot wouldn't
262 * set the required "clock-frequency".
263 *
264 * The hardware documentation states:
265 * "Register compatibility with 16750 register set"
266 */
267 compatible = "ns16750", "ns16550";
268 reg = <0xef600300 0x00000008>;
269 virtual-reg = <0xef600300>;
270 clock-frequency = <0>; /* Filled in by U-Boot */
271 interrupt-parent = <&UIC1>;
272 interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
273 status = "disabled";
274 };
275
276 UART1: serial@ef600400 {
277 /* same "ns16750" as with UART0 */
278 compatible = "ns16750", "ns16550";
279 reg = <0xef600400 0x00000008>;
280 virtual-reg = <0xef600400>;
281 clock-frequency = <0>; /* Filled in by U-Boot */
282 interrupt-parent = <&UIC0>;
283 interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
284 status = "disabled";
285 };
286
287 IIC0: i2c@ef600700 {
288 compatible = "ibm,iic-460ex", "ibm,iic";
289 reg = <0xef600700 0x00000014>;
290 interrupt-parent = <&UIC0>;
291 interrupts = <0x02 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 status = "disabled";
295 };
296
297 IIC1: i2c@ef600800 {
298 compatible = "ibm,iic-460ex", "ibm,iic";
299 reg = <0xef600800 0x00000014>;
300 interrupt-parent = <&UIC0>;
301 interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 status = "disabled";
305 };
306
307 GPIO0: gpio@ef600b00 {
308 compatible = "ibm,ppc4xx-gpio";
309 reg = <0xef600b00 0x00000048>;
310 #gpio-cells = <2>;
311 gpio-controller;
312 status = "disabled";
313 };
314
315 EMAC0: ethernet@ef600c00 {
316 device_type = "network";
317 compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
318 interrupt-parent = <&EMAC0>;
319 interrupts = <0 1>;
320 #interrupt-cells = <1>;
321 #address-cells = <0>;
322 #size-cells = <0>;
323 interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH>,
324 <1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "status", "wake";
326
327 reg = <0xef600c00 0x000000c4>;
328 local-mac-address = [000000000000]; /* Filled in by U-Boot */
329 mal-device = <&MAL0>;
330 mal-tx-channel = <0>;
331 mal-rx-channel = <0>;
332 cell-index = <0>;
333 max-frame-size = <9000>;
334 rx-fifo-size = <16384>;
335 tx-fifo-size = <2048>;
336 phy-mode = "rgmii";
337 phy-map = <0x00000000>;
338 rgmii-device = <&RGMII0>;
339 rgmii-channel = <0>;
340 tah-device = <&TAH0>;
341 tah-channel = <0>;
342 has-inverted-stacr-oc;
343 has-new-stacr-staopc;
344 status = "disabled";
345 };
346
347 TAH0: emac-tah@ef601350 {
348 compatible = "ibm,tah-460ex", "ibm,tah";
349 reg = <0xef601350 0x00000030>;
350 };
351
352 RGMII0: emac-rgmii@ef601500 {
353 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
354 reg = <0xef601500 0x00000008>;
355 has-mdio;
356 };
357 };
358
359 USBOTG0: usbotg@bff80000 {
360 compatible = "amcc,dwc-otg";
361 reg = <4 0xbff80000 0x10000>;
362 interrupt-parent = <&USBOTG0>;
363 interrupts = <0 1 2>;
364 #interrupt-cells = <1>;
365 #address-cells = <0>;
366 #size-cells = <0>;
367 interrupt-map = <0 &UIC2 0x1c IRQ_TYPE_LEVEL_HIGH>,
368 <1 &UIC1 0x1a IRQ_TYPE_LEVEL_LOW>,
369 <2 &UIC0 0x0c IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-names = "usb-otg", "high-power", "dma";
371 dr_mode = "host";
372 status = "disabled";
373 };
374
375 AHBDMA0: dma@bffd0800 {
376 compatible = "snps,dma-spear1340";
377 reg = <4 0xbffd0800 0x400>;
378 interrupt-parent = <&UIC0>;
379 interrupts = <0x19 IRQ_TYPE_LEVEL_HIGH>;
380 #dma-cells = <3>;
381
382 dma-channels = <2>;
383 dma-masters = <3>;
384 block_size = <4095>;
385 data-width = <4>, <4>, <4>;
386 multi-block = <1>, <1>;
387
388 chan_allocation_order = <1>;
389 chan_priority = <1>;
390
391 snps,dma-protection-control =
392 <(DW_DMAC_HPROT1_PRIVILEGED_MODE |
393 DW_DMAC_HPROT2_BUFFERABLE)>;
394 is_memcpy;
395 };
396
397 SATA0: sata@bffd1000 {
398 compatible = "amcc,sata-460ex";
399 reg = <4 0xbffd1000 0x800>;
400 interrupt-parent = <&UIC0>;
401 interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
402 dmas = <&AHBDMA0 0 0 1>;
403 dma-names = "sata-dma";
404 status = "disabled";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 };
408
409 SATA1: sata@bffd1800 {
410 compatible = "amcc,sata-460ex";
411 reg = <4 0xbffd1800 0x800>;
412 interrupt-parent = <&UIC0>;
413 interrupts = <0x1b IRQ_TYPE_LEVEL_HIGH>;
414 dmas = <&AHBDMA0 1 0 2>;
415 dma-names = "sata-dma";
416 status = "disabled";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 };
420
421 PCIE0: pciex@d00000000 {
422 device_type = "pci"; /* see ppc4xx_pci_find_bridge */
423 #interrupt-cells = <1>;
424 #size-cells = <2>;
425 #address-cells = <3>;
426 compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
427 primary;
428 port = <0x0>; /* port number */
429 reg = <0x0000000d 0x00000000 0x20000000>, /* Config space access */
430 <0x0000000c 0x08010000 0x00001000>; /* Registers */
431 dcr-reg = <0x100 0x020>;
432 sdr-base = <0x300>;
433
434 /*
435 * Outbound ranges, one memory and one IO,
436 * later cannot be changed
437 */
438 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000>,
439 <0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000>,
440 <0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
441
442 /* Inbound 2GB range starting at 0 */
443 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
444
445 /* This drives busses 0x40 to 0x7f */
446 bus-range = <0x40 0x7f>;
447
448 /*
449 * Legacy interrupts (note the weird polarity, the bridge seems
450 * to invert PCIe legacy interrupts).
451 * We are de-swizzling here because the numbers are actually for
452 * port of the root complex virtual P2P bridge. But I want
453 * to avoid putting a node for it in the tree, so the numbers
454 * below are basically de-swizzled numbers.
455 * The real slot is on idsel 0, so the swizzling is 1:1
456 */
457 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
458 interrupt-map =
459 <0x0 0x0 0x0 0x1 &UIC3 0x0c IRQ_TYPE_LEVEL_HIGH>, /* swizzled int A */
460 <0x0 0x0 0x0 0x2 &UIC3 0x0d IRQ_TYPE_LEVEL_HIGH>, /* swizzled int B */
461 <0x0 0x0 0x0 0x3 &UIC3 0x0e IRQ_TYPE_LEVEL_HIGH>, /* swizzled int C */
462 <0x0 0x0 0x0 0x4 &UIC3 0x0f IRQ_TYPE_LEVEL_HIGH>; /* swizzled int D */
463 status = "disabled";
464 };
465 };
466 };