Fix tx error handling (#2552). Make rx ring size actually configurable through ethtool
[openwrt/openwrt.git] / target / linux / ar7 / files / drivers / net / cpmac.c
1 /*
2 * Copyright (C) 2006, 2007 OpenWrt.org
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
39 #include <asm/gpio.h>
40
41 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
42 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
43 MODULE_LICENSE("GPL");
44
45 static int debug_level = 8;
46 static int dumb_switch;
47
48 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
49 module_param(debug_level, int, 0444);
50 module_param(dumb_switch, int, 0444);
51
52 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
53 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
54
55 #define CPMAC_VERSION "0.5.0"
56 /* stolen from net/ieee80211.h */
57 #ifndef MAC_FMT
58 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
59 #define MAC_ARG(x) ((u8*)(x))[0], ((u8*)(x))[1], ((u8*)(x))[2], \
60 ((u8*)(x))[3], ((u8*)(x))[4], ((u8*)(x))[5]
61 #endif
62 /* frame size + 802.1q tag */
63 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
64 #define CPMAC_QUEUES 8
65
66 /* Ethernet registers */
67 #define CPMAC_TX_CONTROL 0x0004
68 #define CPMAC_TX_TEARDOWN 0x0008
69 #define CPMAC_RX_CONTROL 0x0014
70 #define CPMAC_RX_TEARDOWN 0x0018
71 #define CPMAC_MBP 0x0100
72 # define MBP_RXPASSCRC 0x40000000
73 # define MBP_RXQOS 0x20000000
74 # define MBP_RXNOCHAIN 0x10000000
75 # define MBP_RXCMF 0x01000000
76 # define MBP_RXSHORT 0x00800000
77 # define MBP_RXCEF 0x00400000
78 # define MBP_RXPROMISC 0x00200000
79 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
80 # define MBP_RXBCAST 0x00002000
81 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
82 # define MBP_RXMCAST 0x00000020
83 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
84 #define CPMAC_UNICAST_ENABLE 0x0104
85 #define CPMAC_UNICAST_CLEAR 0x0108
86 #define CPMAC_MAX_LENGTH 0x010c
87 #define CPMAC_BUFFER_OFFSET 0x0110
88 #define CPMAC_MAC_CONTROL 0x0160
89 # define MAC_TXPTYPE 0x00000200
90 # define MAC_TXPACE 0x00000040
91 # define MAC_MII 0x00000020
92 # define MAC_TXFLOW 0x00000010
93 # define MAC_RXFLOW 0x00000008
94 # define MAC_MTEST 0x00000004
95 # define MAC_LOOPBACK 0x00000002
96 # define MAC_FDX 0x00000001
97 #define CPMAC_MAC_STATUS 0x0164
98 # define MAC_STATUS_QOS 0x00000004
99 # define MAC_STATUS_RXFLOW 0x00000002
100 # define MAC_STATUS_TXFLOW 0x00000001
101 #define CPMAC_TX_INT_ENABLE 0x0178
102 #define CPMAC_TX_INT_CLEAR 0x017c
103 #define CPMAC_MAC_INT_VECTOR 0x0180
104 # define MAC_INT_STATUS 0x00080000
105 # define MAC_INT_HOST 0x00040000
106 # define MAC_INT_RX 0x00020000
107 # define MAC_INT_TX 0x00010000
108 #define CPMAC_MAC_EOI_VECTOR 0x0184
109 #define CPMAC_RX_INT_ENABLE 0x0198
110 #define CPMAC_RX_INT_CLEAR 0x019c
111 #define CPMAC_MAC_INT_ENABLE 0x01a8
112 #define CPMAC_MAC_INT_CLEAR 0x01ac
113 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
114 #define CPMAC_MAC_ADDR_MID 0x01d0
115 #define CPMAC_MAC_ADDR_HI 0x01d4
116 #define CPMAC_MAC_HASH_LO 0x01d8
117 #define CPMAC_MAC_HASH_HI 0x01dc
118 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
119 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
120 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
121 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
122 #define CPMAC_REG_END 0x0680
123 /*
124 * Rx/Tx statistics
125 * TODO: use some of them to fill stats in cpmac_stats()
126 */
127 #define CPMAC_STATS_RX_GOOD 0x0200
128 #define CPMAC_STATS_RX_BCAST 0x0204
129 #define CPMAC_STATS_RX_MCAST 0x0208
130 #define CPMAC_STATS_RX_PAUSE 0x020c
131 #define CPMAC_STATS_RX_CRC 0x0210
132 #define CPMAC_STATS_RX_ALIGN 0x0214
133 #define CPMAC_STATS_RX_OVER 0x0218
134 #define CPMAC_STATS_RX_JABBER 0x021c
135 #define CPMAC_STATS_RX_UNDER 0x0220
136 #define CPMAC_STATS_RX_FRAG 0x0224
137 #define CPMAC_STATS_RX_FILTER 0x0228
138 #define CPMAC_STATS_RX_QOSFILTER 0x022c
139 #define CPMAC_STATS_RX_OCTETS 0x0230
140
141 #define CPMAC_STATS_TX_GOOD 0x0234
142 #define CPMAC_STATS_TX_BCAST 0x0238
143 #define CPMAC_STATS_TX_MCAST 0x023c
144 #define CPMAC_STATS_TX_PAUSE 0x0240
145 #define CPMAC_STATS_TX_DEFER 0x0244
146 #define CPMAC_STATS_TX_COLLISION 0x0248
147 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
148 #define CPMAC_STATS_TX_MULTICOLL 0x0250
149 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
150 #define CPMAC_STATS_TX_LATECOLL 0x0258
151 #define CPMAC_STATS_TX_UNDERRUN 0x025c
152 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
153 #define CPMAC_STATS_TX_OCTETS 0x0264
154
155 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
156 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
157 (reg)))
158
159 /* MDIO bus */
160 #define CPMAC_MDIO_VERSION 0x0000
161 #define CPMAC_MDIO_CONTROL 0x0004
162 # define MDIOC_IDLE 0x80000000
163 # define MDIOC_ENABLE 0x40000000
164 # define MDIOC_PREAMBLE 0x00100000
165 # define MDIOC_FAULT 0x00080000
166 # define MDIOC_FAULTDETECT 0x00040000
167 # define MDIOC_INTTEST 0x00020000
168 # define MDIOC_CLKDIV(div) ((div) & 0xff)
169 #define CPMAC_MDIO_ALIVE 0x0008
170 #define CPMAC_MDIO_LINK 0x000c
171 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
172 # define MDIO_BUSY 0x80000000
173 # define MDIO_WRITE 0x40000000
174 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
175 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
176 # define MDIO_DATA(data) ((data) & 0xffff)
177 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
178 # define PHYSEL_LINKSEL 0x00000040
179 # define PHYSEL_LINKINT 0x00000020
180
181 struct cpmac_desc {
182 u32 hw_next;
183 u32 hw_data;
184 u16 buflen;
185 u16 bufflags;
186 u16 datalen;
187 u16 dataflags;
188 #define CPMAC_SOP 0x8000
189 #define CPMAC_EOP 0x4000
190 #define CPMAC_OWN 0x2000
191 #define CPMAC_EOQ 0x1000
192 struct sk_buff *skb;
193 struct cpmac_desc *next;
194 dma_addr_t mapping;
195 dma_addr_t data_mapping;
196 };
197
198 struct cpmac_priv {
199 spinlock_t lock;
200 spinlock_t rx_lock;
201 struct cpmac_desc *rx_head;
202 int ring_size;
203 struct cpmac_desc *desc_ring;
204 dma_addr_t dma_ring;
205 void __iomem *regs;
206 struct mii_bus *mii_bus;
207 struct phy_device *phy;
208 char phy_name[BUS_ID_SIZE];
209 int oldlink, oldspeed, oldduplex;
210 u32 msg_enable;
211 struct net_device *dev;
212 struct work_struct reset_work;
213 struct platform_device *pdev;
214 };
215
216 static irqreturn_t cpmac_irq(int, void *);
217 static void cpmac_hw_start(struct net_device *dev);
218 static void cpmac_hw_stop(struct net_device *dev);
219 static int cpmac_stop(struct net_device *dev);
220 static int cpmac_open(struct net_device *dev);
221
222 static void cpmac_dump_regs(struct net_device *dev)
223 {
224 int i;
225 struct cpmac_priv *priv = netdev_priv(dev);
226 for (i = 0; i < CPMAC_REG_END; i += 4) {
227 if (i % 16 == 0) {
228 if (i)
229 printk("\n");
230 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
231 priv->regs + i);
232 }
233 printk(" %08x", cpmac_read(priv->regs, i));
234 }
235 printk("\n");
236 }
237
238 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
239 {
240 int i;
241 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
242 for (i = 0; i < sizeof(*desc) / 4; i++)
243 printk(" %08x", ((u32 *)desc)[i]);
244 printk("\n");
245 }
246
247 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
248 {
249 int i;
250 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
251 for (i = 0; i < skb->len; i++) {
252 if (i % 16 == 0) {
253 if (i)
254 printk("\n");
255 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
256 skb->data + i);
257 }
258 printk(" %02x", ((u8 *)skb->data)[i]);
259 }
260 printk("\n");
261 }
262
263 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
264 {
265 u32 val;
266
267 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
268 cpu_relax();
269 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
270 MDIO_PHY(phy_id));
271 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
272 cpu_relax();
273 return MDIO_DATA(val);
274 }
275
276 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
277 int reg, u16 val)
278 {
279 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
280 cpu_relax();
281 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
282 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
283 return 0;
284 }
285
286 static int cpmac_mdio_reset(struct mii_bus *bus)
287 {
288 ar7_device_reset(AR7_RESET_BIT_MDIO);
289 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
290 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
291 return 0;
292 }
293
294 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
295
296 static struct mii_bus cpmac_mii = {
297 .name = "cpmac-mii",
298 .read = cpmac_mdio_read,
299 .write = cpmac_mdio_write,
300 .reset = cpmac_mdio_reset,
301 .irq = mii_irqs,
302 };
303
304 static int cpmac_config(struct net_device *dev, struct ifmap *map)
305 {
306 if (dev->flags & IFF_UP)
307 return -EBUSY;
308
309 /* Don't allow changing the I/O address */
310 if (map->base_addr != dev->base_addr)
311 return -EOPNOTSUPP;
312
313 /* ignore other fields */
314 return 0;
315 }
316
317 static void cpmac_set_multicast_list(struct net_device *dev)
318 {
319 struct dev_mc_list *iter;
320 int i;
321 u8 tmp;
322 u32 mbp, bit, hash[2] = { 0, };
323 struct cpmac_priv *priv = netdev_priv(dev);
324
325 mbp = cpmac_read(priv->regs, CPMAC_MBP);
326 if (dev->flags & IFF_PROMISC) {
327 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
328 MBP_RXPROMISC);
329 } else {
330 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
331 if (dev->flags & IFF_ALLMULTI) {
332 /* enable all multicast mode */
333 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
334 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
335 } else {
336 /*
337 * cpmac uses some strange mac address hashing
338 * (not crc32)
339 */
340 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
341 i++, iter = iter->next) {
342 bit = 0;
343 tmp = iter->dmi_addr[0];
344 bit ^= (tmp >> 2) ^ (tmp << 4);
345 tmp = iter->dmi_addr[1];
346 bit ^= (tmp >> 4) ^ (tmp << 2);
347 tmp = iter->dmi_addr[2];
348 bit ^= (tmp >> 6) ^ tmp;
349 tmp = iter->dmi_addr[3];
350 bit ^= (tmp >> 2) ^ (tmp << 4);
351 tmp = iter->dmi_addr[4];
352 bit ^= (tmp >> 4) ^ (tmp << 2);
353 tmp = iter->dmi_addr[5];
354 bit ^= (tmp >> 6) ^ tmp;
355 bit &= 0x3f;
356 hash[bit / 32] |= 1 << (bit % 32);
357 }
358
359 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
360 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
361 }
362 }
363 }
364
365 static struct sk_buff *cpmac_rx_one(struct net_device *dev,
366 struct cpmac_priv *priv,
367 struct cpmac_desc *desc)
368 {
369 struct sk_buff *skb, *result = NULL;
370
371 if (unlikely(netif_msg_hw(priv)))
372 cpmac_dump_desc(dev, desc);
373 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
374 if (unlikely(!desc->datalen)) {
375 if (netif_msg_rx_err(priv) && net_ratelimit())
376 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
377 dev->name);
378 return NULL;
379 }
380
381 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
382 if (likely(skb)) {
383 skb_reserve(skb, 2);
384 skb_put(desc->skb, desc->datalen);
385 desc->skb->protocol = eth_type_trans(desc->skb, dev);
386 desc->skb->ip_summed = CHECKSUM_NONE;
387 dev->stats.rx_packets++;
388 dev->stats.rx_bytes += desc->datalen;
389 result = desc->skb;
390 dma_unmap_single(&dev->dev, desc->data_mapping, CPMAC_SKB_SIZE,
391 DMA_FROM_DEVICE);
392 desc->skb = skb;
393 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
394 CPMAC_SKB_SIZE,
395 DMA_FROM_DEVICE);
396 desc->hw_data = (u32)desc->data_mapping;
397 if (unlikely(netif_msg_pktdata(priv))) {
398 printk(KERN_DEBUG "%s: received packet:\n", dev->name);
399 cpmac_dump_skb(dev, result);
400 }
401 } else {
402 if (netif_msg_rx_err(priv) && net_ratelimit())
403 printk(KERN_WARNING
404 "%s: low on skbs, dropping packet\n", dev->name);
405 dev->stats.rx_dropped++;
406 }
407
408 desc->buflen = CPMAC_SKB_SIZE;
409 desc->dataflags = CPMAC_OWN;
410
411 return result;
412 }
413
414 static int cpmac_poll(struct net_device *dev, int *budget)
415 {
416 struct sk_buff *skb;
417 struct cpmac_desc *desc;
418 int received = 0, quota = min(dev->quota, *budget);
419 struct cpmac_priv *priv = netdev_priv(dev);
420
421 spin_lock(&priv->rx_lock);
422 if (unlikely(!priv->rx_head)) {
423 if (netif_msg_rx_err(priv) && net_ratelimit())
424 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
425 dev->name);
426 netif_rx_complete(dev);
427 return 0;
428 }
429
430 desc = priv->rx_head;
431 while ((received < quota) && ((desc->dataflags & CPMAC_OWN) == 0)) {
432 skb = cpmac_rx_one(dev, priv, desc);
433 if (likely(skb)) {
434 netif_receive_skb(skb);
435 received++;
436 }
437 desc = desc->next;
438 }
439
440 priv->rx_head = desc;
441 spin_unlock(&priv->rx_lock);
442 *budget -= received;
443 dev->quota -= received;
444 if (unlikely(netif_msg_rx_status(priv)))
445 printk(KERN_DEBUG "%s: poll processed %d packets\n", dev->name,
446 received);
447 if (desc->dataflags & CPMAC_OWN) {
448 netif_rx_complete(dev);
449 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
450 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
451 return 0;
452 }
453
454 return 1;
455 }
456
457 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
458 {
459 int queue, len;
460 struct cpmac_desc *desc;
461 struct cpmac_priv *priv = netdev_priv(dev);
462
463 if (unlikely(skb_padto(skb, ETH_ZLEN)))
464 return NETDEV_TX_OK;
465
466 len = max(skb->len, ETH_ZLEN);
467 queue = skb->queue_mapping;
468 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
469 netif_stop_subqueue(dev, queue);
470 #else
471 netif_stop_queue(dev);
472 #endif
473
474 desc = &priv->desc_ring[queue];
475 if (unlikely(desc->dataflags & CPMAC_OWN)) {
476 if (netif_msg_tx_err(priv) && net_ratelimit())
477 printk(KERN_WARNING "%s: tx dma ring full\n",
478 dev->name);
479 return NETDEV_TX_BUSY;
480 }
481
482 spin_lock(&priv->lock);
483 dev->trans_start = jiffies;
484 spin_unlock(&priv->lock);
485 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
486 desc->skb = skb;
487 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
488 DMA_TO_DEVICE);
489 desc->hw_data = (u32)desc->data_mapping;
490 desc->datalen = len;
491 desc->buflen = len;
492 if (unlikely(netif_msg_tx_queued(priv)))
493 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
494 skb->len);
495 if (unlikely(netif_msg_hw(priv)))
496 cpmac_dump_desc(dev, desc);
497 if (unlikely(netif_msg_pktdata(priv)))
498 cpmac_dump_skb(dev, skb);
499 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
500
501 return NETDEV_TX_OK;
502 }
503
504 static void cpmac_end_xmit(struct net_device *dev, int queue)
505 {
506 struct cpmac_desc *desc;
507 struct cpmac_priv *priv = netdev_priv(dev);
508
509 desc = &priv->desc_ring[queue];
510 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
511 if (likely(desc->skb)) {
512 spin_lock(&priv->lock);
513 dev->stats.tx_packets++;
514 dev->stats.tx_bytes += desc->skb->len;
515 spin_unlock(&priv->lock);
516 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
517 DMA_TO_DEVICE);
518
519 if (unlikely(netif_msg_tx_done(priv)))
520 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
521 desc->skb, desc->skb->len);
522
523 dev_kfree_skb_irq(desc->skb);
524 desc->skb = NULL;
525 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
526 if (netif_subqueue_stopped(dev, queue))
527 netif_wake_subqueue(dev, queue);
528 #else
529 if (netif_queue_stopped(dev))
530 netif_wake_queue(dev);
531 #endif
532 } else {
533 if (netif_msg_tx_err(priv) && net_ratelimit())
534 printk(KERN_WARNING
535 "%s: end_xmit: spurious interrupt\n", dev->name);
536 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
537 if (netif_subqueue_stopped(dev, queue))
538 netif_wake_subqueue(dev, queue);
539 #else
540 if (netif_queue_stopped(dev))
541 netif_wake_queue(dev);
542 #endif
543 }
544 }
545
546 static void cpmac_hw_stop(struct net_device *dev)
547 {
548 int i;
549 struct cpmac_priv *priv = netdev_priv(dev);
550 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
551
552 ar7_device_reset(pdata->reset_bit);
553 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
554 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
555 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
556 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
557 for (i = 0; i < 8; i++) {
558 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
559 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
560 }
561 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
562 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
563 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
564 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
565 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
566 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
567 }
568
569 static void cpmac_hw_start(struct net_device *dev)
570 {
571 int i;
572 struct cpmac_priv *priv = netdev_priv(dev);
573 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
574
575 ar7_device_reset(pdata->reset_bit);
576 for (i = 0; i < 8; i++) {
577 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
578 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
579 }
580 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
581
582 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
583 MBP_RXMCAST);
584 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
585 for (i = 0; i < 8; i++)
586 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
587 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
588 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
589 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
590 (dev->dev_addr[3] << 24));
591 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
592 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
593 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
594 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
595 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
596 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
597 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
598 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
599 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
600
601 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
602 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
603 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
604 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
605 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
606 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
607 MAC_FDX);
608 }
609
610 static void cpmac_clear_rx(struct net_device *dev)
611 {
612 struct cpmac_priv *priv = netdev_priv(dev);
613 struct cpmac_desc *desc;
614 int i;
615 if (unlikely(!priv->rx_head))
616 return;
617 desc = priv->rx_head;
618 for (i = 0; i < priv->ring_size; i++) {
619 if ((desc->dataflags & CPMAC_OWN) == 0) {
620 if (netif_msg_rx_err(priv) && net_ratelimit())
621 printk(KERN_WARNING "%s: packet dropped\n",
622 dev->name);
623 if (unlikely(netif_msg_hw(priv)))
624 cpmac_dump_desc(dev, desc);
625 desc->dataflags = CPMAC_OWN;
626 dev->stats.rx_dropped++;
627 }
628 desc = desc->next;
629 }
630 }
631
632 static void cpmac_clear_tx(struct net_device *dev)
633 {
634 struct cpmac_priv *priv = netdev_priv(dev);
635 int i;
636 if (unlikely(!priv->desc_ring))
637 return;
638 for (i = 0; i < CPMAC_QUEUES; i++) {
639 priv->desc_ring[i].dataflags = 0;
640 if (priv->desc_ring[i].skb) {
641 dev_kfree_skb_any(priv->desc_ring[i].skb);
642 if (netif_subqueue_stopped(dev, i))
643 netif_wake_subqueue(dev, i);
644 }
645 }
646 }
647
648 static void cpmac_hw_error(struct work_struct *work)
649 {
650 struct cpmac_priv *priv =
651 container_of(work, struct cpmac_priv, reset_work);
652
653 spin_lock(&priv->rx_lock);
654 cpmac_clear_rx(priv->dev);
655 spin_unlock(&priv->rx_lock);
656 cpmac_clear_tx(priv->dev);
657 cpmac_hw_start(priv->dev);
658 netif_start_queue(priv->dev);
659 }
660
661 static irqreturn_t cpmac_irq(int irq, void *dev_id)
662 {
663 struct net_device *dev = dev_id;
664 struct cpmac_priv *priv;
665 int queue;
666 u32 status;
667
668 if (!dev)
669 return IRQ_NONE;
670
671 priv = netdev_priv(dev);
672
673 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
674
675 if (unlikely(netif_msg_intr(priv)))
676 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
677 status);
678
679 if (status & MAC_INT_TX)
680 cpmac_end_xmit(dev, (status & 7));
681
682 if (status & MAC_INT_RX) {
683 queue = (status >> 8) & 7;
684 netif_rx_schedule(dev);
685 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
686 }
687
688 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
689
690 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
691 if (netif_msg_drv(priv) && net_ratelimit())
692 printk(KERN_ERR "%s: hw error, resetting...\n",
693 dev->name);
694 netif_stop_queue(dev);
695 cpmac_hw_stop(dev);
696 schedule_work(&priv->reset_work);
697 if (unlikely(netif_msg_hw(priv)))
698 cpmac_dump_regs(dev);
699 }
700
701 return IRQ_HANDLED;
702 }
703
704 static void cpmac_tx_timeout(struct net_device *dev)
705 {
706 struct cpmac_priv *priv = netdev_priv(dev);
707 int i;
708
709 spin_lock(&priv->lock);
710 dev->stats.tx_errors++;
711 spin_unlock(&priv->lock);
712 if (netif_msg_tx_err(priv) && net_ratelimit())
713 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
714 /*
715 * FIXME: waking up random queue is not the best thing to
716 * do... on the other hand why we got here at all?
717 */
718 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
719 for (i = 0; i < CPMAC_QUEUES; i++)
720 if (priv->desc_ring[i].skb) {
721 priv->desc_ring[i].dataflags = 0;
722 dev_kfree_skb_any(priv->desc_ring[i].skb);
723 netif_wake_subqueue(dev, i);
724 break;
725 }
726 #else
727 priv->desc_ring[0].dataflags = 0;
728 if (priv->desc_ring[0].skb)
729 dev_kfree_skb_any(priv->desc_ring[0].skb);
730 netif_wake_queue(dev);
731 #endif
732 }
733
734 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
735 {
736 struct cpmac_priv *priv = netdev_priv(dev);
737 if (!(netif_running(dev)))
738 return -EINVAL;
739 if (!priv->phy)
740 return -EINVAL;
741 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
742 (cmd == SIOCSMIIREG))
743 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
744
745 return -EOPNOTSUPP;
746 }
747
748 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
749 {
750 struct cpmac_priv *priv = netdev_priv(dev);
751
752 if (priv->phy)
753 return phy_ethtool_gset(priv->phy, cmd);
754
755 return -EINVAL;
756 }
757
758 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
759 {
760 struct cpmac_priv *priv = netdev_priv(dev);
761
762 if (!capable(CAP_NET_ADMIN))
763 return -EPERM;
764
765 if (priv->phy)
766 return phy_ethtool_sset(priv->phy, cmd);
767
768 return -EINVAL;
769 }
770
771 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
772 {
773 struct cpmac_priv *priv = netdev_priv(dev);
774
775 ring->rx_max_pending = 1024;
776 ring->rx_mini_max_pending = 1;
777 ring->rx_jumbo_max_pending = 1;
778 ring->tx_max_pending = 1;
779
780 ring->rx_pending = priv->ring_size;
781 ring->rx_mini_pending = 1;
782 ring->rx_jumbo_pending = 1;
783 ring->tx_pending = 1;
784 }
785
786 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
787 {
788 struct cpmac_priv *priv = netdev_priv(dev);
789
790 if (netif_running(dev))
791 return -EBUSY;
792 priv->ring_size = ring->rx_pending;
793 return 0;
794 }
795
796 static void cpmac_get_drvinfo(struct net_device *dev,
797 struct ethtool_drvinfo *info)
798 {
799 strcpy(info->driver, "cpmac");
800 strcpy(info->version, CPMAC_VERSION);
801 info->fw_version[0] = '\0';
802 sprintf(info->bus_info, "%s", "cpmac");
803 info->regdump_len = 0;
804 }
805
806 static const struct ethtool_ops cpmac_ethtool_ops = {
807 .get_settings = cpmac_get_settings,
808 .set_settings = cpmac_set_settings,
809 .get_drvinfo = cpmac_get_drvinfo,
810 .get_link = ethtool_op_get_link,
811 .get_ringparam = cpmac_get_ringparam,
812 .set_ringparam = cpmac_set_ringparam,
813 };
814
815 static void cpmac_adjust_link(struct net_device *dev)
816 {
817 struct cpmac_priv *priv = netdev_priv(dev);
818 int new_state = 0;
819
820 spin_lock(&priv->lock);
821 if (priv->phy->link) {
822 netif_start_queue(dev);
823 if (priv->phy->duplex != priv->oldduplex) {
824 new_state = 1;
825 priv->oldduplex = priv->phy->duplex;
826 }
827
828 if (priv->phy->speed != priv->oldspeed) {
829 new_state = 1;
830 priv->oldspeed = priv->phy->speed;
831 }
832
833 if (!priv->oldlink) {
834 new_state = 1;
835 priv->oldlink = 1;
836 netif_schedule(dev);
837 }
838 } else if (priv->oldlink) {
839 netif_stop_queue(dev);
840 new_state = 1;
841 priv->oldlink = 0;
842 priv->oldspeed = 0;
843 priv->oldduplex = -1;
844 }
845
846 if (new_state && netif_msg_link(priv) && net_ratelimit())
847 phy_print_status(priv->phy);
848
849 spin_unlock(&priv->lock);
850 }
851
852 static int cpmac_open(struct net_device *dev)
853 {
854 int i, size, res;
855 struct cpmac_priv *priv = netdev_priv(dev);
856 struct resource *mem;
857 struct cpmac_desc *desc;
858 struct sk_buff *skb;
859
860 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
861 0, PHY_INTERFACE_MODE_MII);
862 if (IS_ERR(priv->phy)) {
863 if (netif_msg_drv(priv))
864 printk(KERN_ERR "%s: Could not attach to PHY\n",
865 dev->name);
866 return PTR_ERR(priv->phy);
867 }
868
869 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
870 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
871 if (netif_msg_drv(priv))
872 printk(KERN_ERR "%s: failed to request registers\n",
873 dev->name);
874 res = -ENXIO;
875 goto fail_reserve;
876 }
877
878 priv->regs = ioremap(mem->start, mem->end - mem->start);
879 if (!priv->regs) {
880 if (netif_msg_drv(priv))
881 printk(KERN_ERR "%s: failed to remap registers\n",
882 dev->name);
883 res = -ENXIO;
884 goto fail_remap;
885 }
886
887 size = priv->ring_size + CPMAC_QUEUES;
888 priv->desc_ring = dma_alloc_coherent(&dev->dev,
889 sizeof(struct cpmac_desc) * size,
890 &priv->dma_ring,
891 GFP_KERNEL);
892 if (!priv->desc_ring) {
893 res = -ENOMEM;
894 goto fail_alloc;
895 }
896
897 for (i = 0; i < size; i++)
898 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
899
900 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
901 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
902 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
903 if (unlikely(!skb)) {
904 res = -ENOMEM;
905 goto fail_desc;
906 }
907 skb_reserve(skb, 2);
908 desc->skb = skb;
909 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
910 CPMAC_SKB_SIZE,
911 DMA_FROM_DEVICE);
912 desc->hw_data = (u32)desc->data_mapping;
913 desc->buflen = CPMAC_SKB_SIZE;
914 desc->dataflags = CPMAC_OWN;
915 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
916 desc->hw_next = (u32)desc->next->mapping;
917 }
918
919 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
920 dev->name, dev))) {
921 if (netif_msg_drv(priv))
922 printk(KERN_ERR "%s: failed to obtain irq\n",
923 dev->name);
924 goto fail_irq;
925 }
926
927 INIT_WORK(&priv->reset_work, cpmac_hw_error);
928 cpmac_hw_start(dev);
929
930 priv->phy->state = PHY_CHANGELINK;
931 phy_start(priv->phy);
932
933 return 0;
934
935 fail_irq:
936 fail_desc:
937 for (i = 0; i < priv->ring_size; i++) {
938 if (priv->rx_head[i].skb) {
939 dma_unmap_single(&dev->dev,
940 priv->rx_head[i].data_mapping,
941 CPMAC_SKB_SIZE,
942 DMA_FROM_DEVICE);
943 kfree_skb(priv->rx_head[i].skb);
944 }
945 }
946 fail_alloc:
947 kfree(priv->desc_ring);
948 iounmap(priv->regs);
949
950 fail_remap:
951 release_mem_region(mem->start, mem->end - mem->start);
952
953 fail_reserve:
954 phy_disconnect(priv->phy);
955
956 return res;
957 }
958
959 static int cpmac_stop(struct net_device *dev)
960 {
961 int i;
962 struct cpmac_priv *priv = netdev_priv(dev);
963 struct resource *mem;
964
965 netif_stop_queue(dev);
966
967 cancel_work_sync(&priv->reset_work);
968 phy_stop(priv->phy);
969 phy_disconnect(priv->phy);
970 priv->phy = NULL;
971
972 cpmac_hw_stop(dev);
973
974 for (i = 0; i < 8; i++)
975 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
976 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
977 cpmac_write(priv->regs, CPMAC_MBP, 0);
978
979 free_irq(dev->irq, dev);
980 iounmap(priv->regs);
981 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
982 release_mem_region(mem->start, mem->end - mem->start);
983 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
984 for (i = 0; i < priv->ring_size; i++) {
985 if (priv->rx_head[i].skb) {
986 dma_unmap_single(&dev->dev,
987 priv->rx_head[i].data_mapping,
988 CPMAC_SKB_SIZE,
989 DMA_FROM_DEVICE);
990 kfree_skb(priv->rx_head[i].skb);
991 }
992 }
993
994 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
995 (CPMAC_QUEUES + priv->ring_size),
996 priv->desc_ring, priv->dma_ring);
997 return 0;
998 }
999
1000 static int external_switch;
1001
1002 static int __devinit cpmac_probe(struct platform_device *pdev)
1003 {
1004 int rc, phy_id;
1005 struct resource *mem;
1006 struct cpmac_priv *priv;
1007 struct net_device *dev;
1008 struct plat_cpmac_data *pdata;
1009
1010 pdata = pdev->dev.platform_data;
1011
1012 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1013 if (!(pdata->phy_mask & (1 << phy_id)))
1014 continue;
1015 if (!cpmac_mii.phy_map[phy_id])
1016 continue;
1017 break;
1018 }
1019
1020 if (phy_id == PHY_MAX_ADDR) {
1021 if (external_switch || dumb_switch)
1022 phy_id = 0;
1023 else {
1024 printk(KERN_ERR "cpmac: no PHY present\n");
1025 return -ENODEV;
1026 }
1027 }
1028
1029 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1030
1031 if (!dev) {
1032 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1033 return -ENOMEM;
1034 }
1035
1036 platform_set_drvdata(pdev, dev);
1037 priv = netdev_priv(dev);
1038
1039 priv->pdev = pdev;
1040 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1041 if (!mem) {
1042 rc = -ENODEV;
1043 goto fail;
1044 }
1045
1046 dev->irq = platform_get_irq_byname(pdev, "irq");
1047
1048 dev->open = cpmac_open;
1049 dev->stop = cpmac_stop;
1050 dev->set_config = cpmac_config;
1051 dev->hard_start_xmit = cpmac_start_xmit;
1052 dev->do_ioctl = cpmac_ioctl;
1053 dev->set_multicast_list = cpmac_set_multicast_list;
1054 dev->tx_timeout = cpmac_tx_timeout;
1055 dev->ethtool_ops = &cpmac_ethtool_ops;
1056 dev->poll = cpmac_poll;
1057 dev->weight = 64;
1058 dev->features |= NETIF_F_MULTI_QUEUE;
1059
1060 spin_lock_init(&priv->lock);
1061 spin_lock_init(&priv->rx_lock);
1062 priv->dev = dev;
1063 priv->ring_size = 64;
1064 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1065 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1066 if (phy_id == 31) {
1067 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1068 cpmac_mii.id, phy_id);
1069 } else
1070 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1071
1072 if ((rc = register_netdev(dev))) {
1073 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1074 dev->name);
1075 goto fail;
1076 }
1077
1078 if (netif_msg_probe(priv)) {
1079 printk(KERN_INFO
1080 "cpmac: device %s (regs: %p, irq: %d, phy: %s, mac: "
1081 MAC_FMT ")\n", dev->name, (void *)mem->start, dev->irq,
1082 priv->phy_name, MAC_ARG(dev->dev_addr));
1083 }
1084 return 0;
1085
1086 fail:
1087 free_netdev(dev);
1088 return rc;
1089 }
1090
1091 static int __devexit cpmac_remove(struct platform_device *pdev)
1092 {
1093 struct net_device *dev = platform_get_drvdata(pdev);
1094 unregister_netdev(dev);
1095 free_netdev(dev);
1096 return 0;
1097 }
1098
1099 static struct platform_driver cpmac_driver = {
1100 .driver.name = "cpmac",
1101 .probe = cpmac_probe,
1102 .remove = __devexit_p(cpmac_remove),
1103 };
1104
1105 int __devinit cpmac_init(void)
1106 {
1107 u32 mask;
1108 int i, res;
1109
1110 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1111
1112 if (!cpmac_mii.priv) {
1113 printk(KERN_ERR "Can't ioremap mdio registers\n");
1114 return -ENXIO;
1115 }
1116
1117 #warning FIXME: unhardcode gpio&reset bits
1118 ar7_gpio_disable(26);
1119 ar7_gpio_disable(27);
1120 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1121 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1122 ar7_device_reset(AR7_RESET_BIT_EPHY);
1123
1124 cpmac_mii.reset(&cpmac_mii);
1125
1126 for (i = 0; i < 300000; i++)
1127 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1128 break;
1129 else
1130 cpu_relax();
1131
1132 mask &= 0x7fffffff;
1133 if (mask & (mask - 1)) {
1134 external_switch = 1;
1135 mask = 0;
1136 }
1137
1138 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1139
1140 res = mdiobus_register(&cpmac_mii);
1141 if (res)
1142 goto fail_mii;
1143
1144 res = platform_driver_register(&cpmac_driver);
1145 if (res)
1146 goto fail_cpmac;
1147
1148 return 0;
1149
1150 fail_cpmac:
1151 mdiobus_unregister(&cpmac_mii);
1152
1153 fail_mii:
1154 iounmap(cpmac_mii.priv);
1155
1156 return res;
1157 }
1158
1159 void __devexit cpmac_exit(void)
1160 {
1161 platform_driver_unregister(&cpmac_driver);
1162 mdiobus_unregister(&cpmac_mii);
1163 iounmap(cpmac_mii.priv);
1164 }
1165
1166 module_init(cpmac_init);
1167 module_exit(cpmac_exit);