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add AR7240 specific fixes for the ag71xx driver
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ar71xx / devices.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/serial_8250.h>
21 #include <linux/ath9k_platform.h>
22
23 #include <asm/mach-ar71xx/ar71xx.h>
24
25 #include "devices.h"
26
27 static u8 ar71xx_mac_base[ETH_ALEN] __initdata;
28
29 /*
30 * OHCI (USB full speed host controller)
31 */
32 static struct resource ar71xx_ohci_resources[] = {
33 [0] = {
34 .start = AR71XX_OHCI_BASE,
35 .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1,
36 .flags = IORESOURCE_MEM,
37 },
38 [1] = {
39 .start = AR71XX_MISC_IRQ_OHCI,
40 .end = AR71XX_MISC_IRQ_OHCI,
41 .flags = IORESOURCE_IRQ,
42 },
43 };
44
45 static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32);
46 static struct platform_device ar71xx_ohci_device = {
47 .name = "ar71xx-ohci",
48 .id = -1,
49 .resource = ar71xx_ohci_resources,
50 .num_resources = ARRAY_SIZE(ar71xx_ohci_resources),
51 .dev = {
52 .dma_mask = &ar71xx_ohci_dmamask,
53 .coherent_dma_mask = DMA_BIT_MASK(32),
54 },
55 };
56
57 /*
58 * EHCI (USB full speed host controller)
59 */
60 static struct resource ar71xx_ehci_resources[] = {
61 [0] = {
62 .start = AR71XX_EHCI_BASE,
63 .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = AR71XX_CPU_IRQ_USB,
68 .end = AR71XX_CPU_IRQ_USB,
69 .flags = IORESOURCE_IRQ,
70 },
71 };
72
73
74 static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32);
75 static struct ar71xx_ehci_platform_data ar71xx_ehci_data;
76
77 static struct platform_device ar71xx_ehci_device = {
78 .name = "ar71xx-ehci",
79 .id = -1,
80 .resource = ar71xx_ehci_resources,
81 .num_resources = ARRAY_SIZE(ar71xx_ehci_resources),
82 .dev = {
83 .dma_mask = &ar71xx_ehci_dmamask,
84 .coherent_dma_mask = DMA_BIT_MASK(32),
85 .platform_data = &ar71xx_ehci_data,
86 },
87 };
88
89 #define AR71XX_USB_RESET_MASK \
90 (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \
91 | RESET_MODULE_USB_OHCI_DLL)
92
93 static void ar71xx_usb_setup(void)
94 {
95 ar71xx_device_stop(AR71XX_USB_RESET_MASK);
96 mdelay(1000);
97 ar71xx_device_start(AR71XX_USB_RESET_MASK);
98
99 /* Turning on the Buff and Desc swap bits */
100 ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000);
101
102 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
103 ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00);
104
105 mdelay(900);
106 }
107
108 static void ar91xx_usb_setup(void)
109 {
110 ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE);
111 mdelay(10);
112
113 ar71xx_device_start(RESET_MODULE_USB_HOST);
114 mdelay(10);
115
116 ar71xx_device_start(RESET_MODULE_USB_PHY);
117 mdelay(10);
118 }
119
120 void __init ar71xx_add_device_usb(void)
121 {
122 switch (ar71xx_soc) {
123 case AR71XX_SOC_AR7130:
124 case AR71XX_SOC_AR7141:
125 case AR71XX_SOC_AR7161:
126 ar71xx_usb_setup();
127 platform_device_register(&ar71xx_ohci_device);
128 platform_device_register(&ar71xx_ehci_device);
129 break;
130
131 case AR71XX_SOC_AR9130:
132 case AR71XX_SOC_AR9132:
133 ar91xx_usb_setup();
134 ar71xx_ehci_data.is_ar91xx = 1;
135 platform_device_register(&ar71xx_ehci_device);
136 break;
137
138 default:
139 BUG();
140 }
141 }
142
143 #ifndef CONFIG_AR71XX_EARLY_SERIAL
144 static struct resource ar71xx_uart_resources[] = {
145 {
146 .start = AR71XX_UART_BASE,
147 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 };
151
152 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
153 static struct plat_serial8250_port ar71xx_uart_data[] = {
154 {
155 .mapbase = AR71XX_UART_BASE,
156 .irq = AR71XX_MISC_IRQ_UART,
157 .flags = AR71XX_UART_FLAGS,
158 .iotype = UPIO_MEM32,
159 .regshift = 2,
160 }, {
161 /* terminating entry */
162 }
163 };
164
165 static struct platform_device ar71xx_uart_device = {
166 .name = "serial8250",
167 .id = PLAT8250_DEV_PLATFORM,
168 .resource = ar71xx_uart_resources,
169 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
170 .dev = {
171 .platform_data = ar71xx_uart_data
172 },
173 };
174
175 void __init ar71xx_add_device_uart(void)
176 {
177 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
178 platform_device_register(&ar71xx_uart_device);
179 }
180 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
181
182 static struct resource ar71xx_mdio_resources[] = {
183 {
184 .name = "mdio_base",
185 .flags = IORESOURCE_MEM,
186 .start = AR71XX_GE0_BASE + 0x20,
187 .end = AR71XX_GE0_BASE + 0x38 - 1,
188 }
189 };
190
191 static struct ag71xx_mdio_platform_data ar71xx_mdio_data = {
192 .phy_mask = 0xffffffff,
193 };
194
195 static struct platform_device ar71xx_mdio_device = {
196 .name = "ag71xx-mdio",
197 .id = -1,
198 .resource = ar71xx_mdio_resources,
199 .num_resources = ARRAY_SIZE(ar71xx_mdio_resources),
200 .dev = {
201 .platform_data = &ar71xx_mdio_data,
202 },
203 };
204
205 void __init ar71xx_add_device_mdio(u32 phy_mask)
206 {
207 ar71xx_mdio_data.phy_mask = phy_mask;
208 platform_device_register(&ar71xx_mdio_device);
209 }
210
211 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
212 {
213 void __iomem *base;
214 u32 t;
215
216 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
217
218 t = __raw_readl(base + cfg_reg);
219 t &= ~(3 << shift);
220 t |= (2 << shift);
221 __raw_writel(t, base + cfg_reg);
222 udelay(100);
223
224 __raw_writel(pll_val, base + pll_reg);
225
226 t |= (3 << shift);
227 __raw_writel(t, base + cfg_reg);
228 udelay(100);
229
230 t &= ~(3 << shift);
231 __raw_writel(t, base + cfg_reg);
232 udelay(100);
233
234 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
235 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
236
237 iounmap(base);
238 }
239
240 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
241 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
242
243 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
244 {
245 struct ar71xx_eth_pll_data *pll_data;
246 u32 pll_val;
247
248 switch (mac) {
249 case 0:
250 pll_data = &ar71xx_eth0_pll_data;
251 break;
252 case 1:
253 pll_data = &ar71xx_eth1_pll_data;
254 break;
255 default:
256 BUG();
257 }
258
259 switch (speed) {
260 case SPEED_10:
261 pll_val = pll_data->pll_10;
262 break;
263 case SPEED_100:
264 pll_val = pll_data->pll_100;
265 break;
266 case SPEED_1000:
267 pll_val = pll_data->pll_1000;
268 break;
269 default:
270 BUG();
271 }
272
273 return pll_val;
274 }
275
276 static void ar71xx_set_pll_ge0(int speed)
277 {
278 u32 val = ar71xx_get_eth_pll(0, speed);
279
280 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
281 val, AR71XX_ETH0_PLL_SHIFT);
282 }
283
284 static void ar71xx_set_pll_ge1(int speed)
285 {
286 u32 val = ar71xx_get_eth_pll(1, speed);
287
288 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
289 val, AR71XX_ETH1_PLL_SHIFT);
290 }
291
292 static void ar724x_set_pll_ge0(int speed)
293 {
294 /* TODO */
295 }
296
297 static void ar724x_set_pll_ge1(int speed)
298 {
299 /* TODO */
300 }
301
302 static void ar91xx_set_pll_ge0(int speed)
303 {
304 u32 val = ar71xx_get_eth_pll(0, speed);
305
306 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
307 val, AR91XX_ETH0_PLL_SHIFT);
308 }
309
310 static void ar91xx_set_pll_ge1(int speed)
311 {
312 u32 val = ar71xx_get_eth_pll(1, speed);
313
314 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
315 val, AR91XX_ETH1_PLL_SHIFT);
316 }
317
318 static void ar71xx_ddr_flush_ge0(void)
319 {
320 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
321 }
322
323 static void ar71xx_ddr_flush_ge1(void)
324 {
325 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
326 }
327
328 static void ar724x_ddr_flush_ge0(void)
329 {
330 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
331 }
332
333 static void ar724x_ddr_flush_ge1(void)
334 {
335 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
336 }
337
338 static void ar91xx_ddr_flush_ge0(void)
339 {
340 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
341 }
342
343 static void ar91xx_ddr_flush_ge1(void)
344 {
345 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
346 }
347
348 static struct resource ar71xx_eth0_resources[] = {
349 {
350 .name = "mac_base",
351 .flags = IORESOURCE_MEM,
352 .start = AR71XX_GE0_BASE,
353 .end = AR71XX_GE0_BASE + 0x20 - 1,
354 }, {
355 .name = "mac_base2",
356 .flags = IORESOURCE_MEM,
357 .start = AR71XX_GE0_BASE + 0x38,
358 .end = AR71XX_GE0_BASE + 0x200 - 1,
359 }, {
360 .name = "mii_ctrl",
361 .flags = IORESOURCE_MEM,
362 .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
363 .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
364 }, {
365 .name = "mac_irq",
366 .flags = IORESOURCE_IRQ,
367 .start = AR71XX_CPU_IRQ_GE0,
368 .end = AR71XX_CPU_IRQ_GE0,
369 },
370 };
371
372 struct ag71xx_platform_data ar71xx_eth0_data = {
373 .reset_bit = RESET_MODULE_GE0_MAC,
374 };
375
376 static struct platform_device ar71xx_eth0_device = {
377 .name = "ag71xx",
378 .id = 0,
379 .resource = ar71xx_eth0_resources,
380 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
381 .dev = {
382 .platform_data = &ar71xx_eth0_data,
383 },
384 };
385
386 static struct resource ar71xx_eth1_resources[] = {
387 {
388 .name = "mac_base",
389 .flags = IORESOURCE_MEM,
390 .start = AR71XX_GE1_BASE,
391 .end = AR71XX_GE1_BASE + 0x20 - 1,
392 }, {
393 .name = "mac_base2",
394 .flags = IORESOURCE_MEM,
395 .start = AR71XX_GE1_BASE + 0x38,
396 .end = AR71XX_GE1_BASE + 0x200 - 1,
397 }, {
398 .name = "mii_ctrl",
399 .flags = IORESOURCE_MEM,
400 .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
401 .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
402 }, {
403 .name = "mac_irq",
404 .flags = IORESOURCE_IRQ,
405 .start = AR71XX_CPU_IRQ_GE1,
406 .end = AR71XX_CPU_IRQ_GE1,
407 },
408 };
409
410 struct ag71xx_platform_data ar71xx_eth1_data = {
411 .reset_bit = RESET_MODULE_GE1_MAC,
412 };
413
414 static struct platform_device ar71xx_eth1_device = {
415 .name = "ag71xx",
416 .id = 1,
417 .resource = ar71xx_eth1_resources,
418 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
419 .dev = {
420 .platform_data = &ar71xx_eth1_data,
421 },
422 };
423
424 #define AR71XX_PLL_VAL_1000 0x00110000
425 #define AR71XX_PLL_VAL_100 0x00001099
426 #define AR71XX_PLL_VAL_10 0x00991099
427
428 #define AR724X_PLL_VAL_1000 0x00110000
429 #define AR724X_PLL_VAL_100 0x00001099
430 #define AR724X_PLL_VAL_10 0x00991099
431
432 #define AR91XX_PLL_VAL_1000 0x1a000000
433 #define AR91XX_PLL_VAL_100 0x13000a44
434 #define AR91XX_PLL_VAL_10 0x00441099
435
436 static void __init ar71xx_init_eth_pll_data(unsigned int id)
437 {
438 struct ar71xx_eth_pll_data *pll_data;
439 u32 pll_10, pll_100, pll_1000;
440
441 switch (id) {
442 case 0:
443 pll_data = &ar71xx_eth0_pll_data;
444 break;
445 case 1:
446 pll_data = &ar71xx_eth1_pll_data;
447 break;
448 default:
449 BUG();
450 }
451
452 switch (ar71xx_soc) {
453 case AR71XX_SOC_AR7130:
454 case AR71XX_SOC_AR7141:
455 case AR71XX_SOC_AR7161:
456 pll_10 = AR71XX_PLL_VAL_10;
457 pll_100 = AR71XX_PLL_VAL_100;
458 pll_1000 = AR71XX_PLL_VAL_1000;
459 break;
460
461 case AR71XX_SOC_AR7240:
462 pll_10 = AR724X_PLL_VAL_10;
463 pll_100 = AR724X_PLL_VAL_100;
464 pll_1000 = AR724X_PLL_VAL_1000;
465 break;
466
467 case AR71XX_SOC_AR9130:
468 case AR71XX_SOC_AR9132:
469 pll_10 = AR91XX_PLL_VAL_10;
470 pll_100 = AR91XX_PLL_VAL_100;
471 pll_1000 = AR91XX_PLL_VAL_1000;
472 break;
473 default:
474 BUG();
475 }
476
477 if (!pll_data->pll_10)
478 pll_data->pll_10 = pll_10;
479
480 if (!pll_data->pll_100)
481 pll_data->pll_100 = pll_100;
482
483 if (!pll_data->pll_1000)
484 pll_data->pll_1000 = pll_1000;
485 }
486
487 static int ar71xx_eth_instance __initdata;
488 void __init ar71xx_add_device_eth(unsigned int id)
489 {
490 struct platform_device *pdev;
491 struct ag71xx_platform_data *pdata;
492
493 ar71xx_init_eth_pll_data(id);
494
495 switch (id) {
496 case 0:
497 switch (ar71xx_eth0_data.phy_if_mode) {
498 case PHY_INTERFACE_MODE_MII:
499 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
500 break;
501 case PHY_INTERFACE_MODE_GMII:
502 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
503 break;
504 case PHY_INTERFACE_MODE_RGMII:
505 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
506 break;
507 case PHY_INTERFACE_MODE_RMII:
508 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
509 break;
510 default:
511 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
512 "for eth0\n");
513 return;
514 }
515 pdev = &ar71xx_eth0_device;
516 break;
517 case 1:
518 switch (ar71xx_eth1_data.phy_if_mode) {
519 case PHY_INTERFACE_MODE_RMII:
520 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
521 break;
522 case PHY_INTERFACE_MODE_RGMII:
523 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
524 break;
525 default:
526 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
527 "for eth1\n");
528 return;
529 }
530 pdev = &ar71xx_eth1_device;
531 break;
532 default:
533 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
534 return;
535 }
536
537 pdata = pdev->dev.platform_data;
538
539 switch (ar71xx_soc) {
540 case AR71XX_SOC_AR7130:
541 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
542 : ar71xx_ddr_flush_ge0;
543 pdata->set_pll = id ? ar71xx_set_pll_ge1
544 : ar71xx_set_pll_ge0;
545 break;
546
547 case AR71XX_SOC_AR7141:
548 case AR71XX_SOC_AR7161:
549 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
550 : ar71xx_ddr_flush_ge0;
551 pdata->set_pll = id ? ar71xx_set_pll_ge1
552 : ar71xx_set_pll_ge0;
553 pdata->has_gbit = 1;
554 break;
555
556 case AR71XX_SOC_AR7240:
557 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
558 : ar724x_ddr_flush_ge0;
559 pdata->set_pll = id ? ar724x_set_pll_ge1
560 : ar724x_set_pll_ge0;
561 pdata->is_ar724x = 1;
562 break;
563
564 case AR71XX_SOC_AR9130:
565 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
566 : ar91xx_ddr_flush_ge0;
567 pdata->set_pll = id ? ar91xx_set_pll_ge1
568 : ar91xx_set_pll_ge0;
569 pdata->is_ar91xx = 1;
570 break;
571
572 case AR71XX_SOC_AR9132:
573 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
574 : ar91xx_ddr_flush_ge0;
575 pdata->set_pll = id ? ar91xx_set_pll_ge1
576 : ar91xx_set_pll_ge0;
577 pdata->is_ar91xx = 1;
578 pdata->has_gbit = 1;
579 break;
580
581 default:
582 BUG();
583 }
584
585 switch (pdata->phy_if_mode) {
586 case PHY_INTERFACE_MODE_GMII:
587 case PHY_INTERFACE_MODE_RGMII:
588 if (!pdata->has_gbit) {
589 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
590 id);
591 return;
592 }
593 /* fallthrough */
594 default:
595 break;
596 }
597
598 if (is_valid_ether_addr(ar71xx_mac_base)) {
599 memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN);
600 pdata->mac_addr[5] += ar71xx_eth_instance;
601 } else {
602 random_ether_addr(pdata->mac_addr);
603 printk(KERN_DEBUG
604 "ar71xx: using random MAC address for eth%d\n",
605 ar71xx_eth_instance);
606 }
607
608 platform_device_register(pdev);
609 ar71xx_eth_instance++;
610 }
611
612 static struct resource ar71xx_spi_resources[] = {
613 [0] = {
614 .start = AR71XX_SPI_BASE,
615 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
616 .flags = IORESOURCE_MEM,
617 },
618 };
619
620 static struct platform_device ar71xx_spi_device = {
621 .name = "ar71xx-spi",
622 .id = -1,
623 .resource = ar71xx_spi_resources,
624 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
625 };
626
627 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
628 struct spi_board_info const *info,
629 unsigned n)
630 {
631 spi_register_board_info(info, n);
632 ar71xx_spi_device.dev.platform_data = pdata;
633 platform_device_register(&ar71xx_spi_device);
634 }
635
636 void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds,
637 struct gpio_led *leds)
638 {
639 struct platform_device *pdev;
640 struct gpio_led_platform_data pdata;
641 struct gpio_led *p;
642 int err;
643
644 p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
645 if (!p)
646 return;
647
648 memcpy(p, leds, num_leds * sizeof(*p));
649
650 pdev = platform_device_alloc("leds-gpio", id);
651 if (!pdev)
652 goto err_free_leds;
653
654 memset(&pdata, 0, sizeof(pdata));
655 pdata.num_leds = num_leds;
656 pdata.leds = p;
657
658 err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
659 if (err)
660 goto err_put_pdev;
661
662 err = platform_device_add(pdev);
663 if (err)
664 goto err_put_pdev;
665
666 return;
667
668 err_put_pdev:
669 platform_device_put(pdev);
670
671 err_free_leds:
672 kfree(p);
673 }
674
675 void __init ar71xx_add_device_gpio_buttons(int id,
676 unsigned poll_interval,
677 unsigned nbuttons,
678 struct gpio_button *buttons)
679 {
680 struct platform_device *pdev;
681 struct gpio_buttons_platform_data pdata;
682 struct gpio_button *p;
683 int err;
684
685 p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
686 if (!p)
687 return;
688
689 memcpy(p, buttons, nbuttons * sizeof(*p));
690
691 pdev = platform_device_alloc("gpio-buttons", id);
692 if (!pdev)
693 goto err_free_buttons;
694
695 memset(&pdata, 0, sizeof(pdata));
696 pdata.poll_interval = poll_interval;
697 pdata.nbuttons = nbuttons;
698 pdata.buttons = p;
699
700 err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
701 if (err)
702 goto err_put_pdev;
703
704
705 err = platform_device_add(pdev);
706 if (err)
707 goto err_put_pdev;
708
709 return;
710
711 err_put_pdev:
712 platform_device_put(pdev);
713
714 err_free_buttons:
715 kfree(p);
716 }
717
718 void __init ar71xx_add_device_wdt(void)
719 {
720 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
721 }
722
723 void __init ar71xx_set_mac_base(unsigned char *mac)
724 {
725 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
726 }
727
728 void __init ar71xx_parse_mac_addr(char *mac_str)
729 {
730 u8 tmp[ETH_ALEN];
731 int t;
732
733 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
734 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
735
736 if (t != ETH_ALEN)
737 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
738 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
739
740 if (t == ETH_ALEN)
741 ar71xx_set_mac_base(tmp);
742 else
743 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
744 "\"%s\"\n", mac_str);
745 }
746
747 static struct resource ar91xx_wmac_resources[] = {
748 {
749 .start = AR91XX_WMAC_BASE,
750 .end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1,
751 .flags = IORESOURCE_MEM,
752 }, {
753 .start = AR71XX_CPU_IRQ_WMAC,
754 .end = AR71XX_CPU_IRQ_WMAC,
755 .flags = IORESOURCE_IRQ,
756 },
757 };
758
759 static struct ath9k_platform_data ar91xx_wmac_data;
760
761 static struct platform_device ar91xx_wmac_device = {
762 .name = "ath9k",
763 .id = -1,
764 .resource = ar91xx_wmac_resources,
765 .num_resources = ARRAY_SIZE(ar91xx_wmac_resources),
766 .dev = {
767 .platform_data = &ar91xx_wmac_data,
768 },
769 };
770
771 void __init ar91xx_add_device_wmac(void)
772 {
773 u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
774
775 memcpy(ar91xx_wmac_data.eeprom_data, ee,
776 sizeof(ar91xx_wmac_data.eeprom_data));
777
778 ar71xx_device_stop(RESET_MODULE_AMBA2WMAC);
779 mdelay(10);
780
781 ar71xx_device_start(RESET_MODULE_AMBA2WMAC);
782 mdelay(10);
783
784 platform_device_register(&ar91xx_wmac_device);
785 }
786
787 static struct platform_device ar71xx_dsa_switch_device = {
788 .name = "dsa",
789 .id = 0,
790 };
791
792 void __init ar71xx_add_device_dsa(unsigned int id,
793 struct dsa_platform_data *d)
794 {
795 switch (id) {
796 case 0:
797 d->netdev = &ar71xx_eth0_device.dev;
798 break;
799 case 1:
800 d->netdev = &ar71xx_eth1_device.dev;
801 break;
802 default:
803 printk(KERN_ERR
804 "ar71xx: invalid ethernet id %d for DSA switch\n",
805 id);
806 return;
807 }
808 d->mii_bus = &ar71xx_mdio_device.dev;
809 ar71xx_dsa_switch_device.dev.platform_data = d;
810
811 platform_device_register(&ar71xx_dsa_switch_device);
812 }
OpenWrt Source Repository