target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/traps.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  26
  27 #include <asm/mach-ar71xx/ar71xx.h>
  28 #include <asm/mach-ar71xx/pci.h>
  29 #include <asm/mach-ar71xx/platform.h>
  30
  31 #define AR71XX_SYS_TYPE_LEN     64
  32 #define AR71XX_BASE_FREQ        40000000
  33
  34 #define AR71XX_MEM_SIZE_MIN     0x0200000
  35 #define AR71XX_MEM_SIZE_MAX     0x8000000
  36
  37 u32 ar71xx_cpu_freq;
  38 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  39
  40 u32 ar71xx_ahb_freq;
  41 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  42
  43 u32 ar71xx_ddr_freq;
  44 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  45
  46 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
  47                              struct ar71xx_pci_irq *map) __initdata;
  48
  49 int (*ar71xx_pci_be_handler)(int is_fixup);
  50
  51 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  52
  53 static void ar71xx_restart(char *command)
  54 {
  55         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  56         for (;;)
  57                 if (cpu_wait)
  58                         cpu_wait();
  59 }
  60
  61 static void ar71xx_halt(void)
  62 {
  63         while (1)
  64                 cpu_wait();
  65 }
  66
  67 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
  68 {
  69         int err = 0;
  70
  71         if (ar71xx_pci_be_handler)
  72                 err = ar71xx_pci_be_handler(is_fixup);
  73
  74         return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  75 }
  76
  77 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
  78 {
  79         if (!ar71xx_pci_bios_init)
  80                 return 0;
  81
  82         return ar71xx_pci_bios_init(nr_irqs, map);
  83 }
  84
  85 static void __init ar71xx_detect_mem_size(void)
  86 {
  87         volatile u8 *p;
  88         u8 memsave;
  89         u32 size;
  90
  91         p = (volatile u8 *) KSEG1ADDR(0);
  92         memsave = *p;
  93         for (size = AR71XX_MEM_SIZE_MIN;
  94              size <= (AR71XX_MEM_SIZE_MAX >> 1); size <<= 1) {
  95                 volatile u8 *r;
  96
  97                 r = (p + size);
  98                 *p = 0x55;
  99                 if (*r == 0x55) {
 100                         /* Mirrored data found, try another pattern */
 101                         *p = 0xAA;
 102                         if (*r == 0xAA) {
 103                                 /* Mirrored data found again, stop detection */
 104                                 break;
 105                         }
 106                 }
 107         }
 108         *p = memsave;
 109
 110         add_memory_region(0, size, BOOT_MEM_RAM);
 111 }
 112
 113 static void __init ar71xx_detect_sys_type(void)
 114 {
 115         char *chip;
 116         u32 id;
 117         u32 rev;
 118
 119         id = ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK;
 120         rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
 121         switch (id & REV_ID_CHIP_MASK) {
 122         case REV_ID_CHIP_AR7130:
 123                 chip = "7130";
 124                 break;
 125         case REV_ID_CHIP_AR7141:
 126                 chip = "7141";
 127                 break;
 128         case REV_ID_CHIP_AR7161:
 129                 chip = "7161";
 130                 break;
 131         default:
 132                 chip = "71xx";
 133         }
 134
 135         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
 136                 chip, rev, id);
 137 }
 138
 139 static void __init ar71xx_detect_sys_frequency(void)
 140 {
 141         u32 pll;
 142         u32 freq;
 143         u32 div;
 144
 145         pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
 146
 147         div = ((pll >> PLL_DIV_SHIFT) & PLL_DIV_MASK) + 1;
 148         freq = div * AR71XX_BASE_FREQ;
 149
 150         div = ((pll >> CPU_DIV_SHIFT) & CPU_DIV_MASK) + 1;
 151         ar71xx_cpu_freq = freq / div;
 152
 153         div = ((pll >> DDR_DIV_SHIFT) & DDR_DIV_MASK) + 1;
 154         ar71xx_ddr_freq = freq / div;
 155
 156         div = (((pll >> AHB_DIV_SHIFT) & AHB_DIV_MASK) + 1) * 2;
 157         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 158 }
 159
 160 #ifdef CONFIG_AR71XX_EARLY_SERIAL
 161 static void __init ar71xx_early_serial_setup(void)
 162 {
 163         struct uart_port p;
 164
 165         memset(&p, 0, sizeof(p));
 166
 167         p.flags         = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
 168         p.iotype        = UPIO_MEM32;
 169         p.uartclk       = ar71xx_ahb_freq;
 170         p.irq           = AR71XX_MISC_IRQ_UART;
 171         p.regshift      = 2;
 172         p.mapbase       = AR71XX_UART_BASE;
 173
 174         early_serial_setup(&p);
 175 }
 176 #else
 177 static inline void ar71xx_early_serial_setup(void) {};
 178 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
 179
 180 const char *get_system_type(void)
 181 {
 182         return ar71xx_sys_type;
 183 }
 184
 185 unsigned int __cpuinit get_c0_compare_irq(void)
 186 {
 187         return CP0_LEGACY_COMPARE_IRQ;
 188 }
 189
 190 void __init plat_mem_setup(void)
 191 {
 192         set_io_port_base(KSEG1);
 193
 194         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 195                                                 AR71XX_DDR_CTRL_SIZE);
 196
 197         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 198                                                 AR71XX_PLL_SIZE);
 199
 200         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 201                                                 AR71XX_RESET_SIZE);
 202
 203         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 204
 205         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 206                                                 AR71XX_USB_CTRL_SIZE);
 207
 208         ar71xx_detect_mem_size();
 209         ar71xx_detect_sys_type();
 210         ar71xx_detect_sys_frequency();
 211
 212         _machine_restart = ar71xx_restart;
 213         _machine_halt = ar71xx_halt;
 214         pm_power_off = ar71xx_halt;
 215
 216         board_be_handler = ar71xx_be_handler;
 217
 218         ar71xx_print_cmdline();
 219
 220         ar71xx_early_serial_setup();
 221 }
 222
 223 void __init plat_time_init(void)
 224 {
 225         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 226 }