d70347041ac5853c2b5814c5f8aae11ba215e1a2
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ar71xx / setup.c
1 /*
2 * Atheros AR71xx SoC specific setup
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
19
20 #include <asm/bootinfo.h>
21 #include <asm/time.h> /* for mips_hpt_frequency */
22 #include <asm/reboot.h> /* for _machine_{restart,halt} */
23 #include <asm/mips_machine.h>
24
25 #include <asm/mach-ar71xx/ar71xx.h>
26
27 #include "machtype.h"
28 #include "devices.h"
29
30 #define AR71XX_SYS_TYPE_LEN 64
31
32 u32 ar71xx_cpu_freq;
33 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
34
35 u32 ar71xx_ahb_freq;
36 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
37
38 u32 ar71xx_ddr_freq;
39 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
40
41 u32 ar71xx_ref_freq;
42 EXPORT_SYMBOL_GPL(ar71xx_ref_freq);
43
44 enum ar71xx_soc_type ar71xx_soc;
45 EXPORT_SYMBOL_GPL(ar71xx_soc);
46
47 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
48
49 static void ar71xx_restart(char *command)
50 {
51 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
52 for (;;)
53 if (cpu_wait)
54 cpu_wait();
55 }
56
57 static void ar71xx_halt(void)
58 {
59 while (1)
60 cpu_wait();
61 }
62
63 static void __init ar71xx_detect_mem_size(void)
64 {
65 unsigned long size;
66
67 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
68 size <<= 1) {
69 if (!memcmp(ar71xx_detect_mem_size,
70 ar71xx_detect_mem_size + size, 1024))
71 break;
72 }
73
74 add_memory_region(0, size, BOOT_MEM_RAM);
75 }
76
77 static void __init ar71xx_detect_sys_type(void)
78 {
79 char *chip = "????";
80 u32 id;
81 u32 major;
82 u32 minor;
83 u32 rev = 0;
84
85 id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
86 major = id & REV_ID_MAJOR_MASK;
87
88 switch (major) {
89 case REV_ID_MAJOR_AR71XX:
90 minor = id & AR71XX_REV_ID_MINOR_MASK;
91 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
92 rev &= AR71XX_REV_ID_REVISION_MASK;
93 switch (minor) {
94 case AR71XX_REV_ID_MINOR_AR7130:
95 ar71xx_soc = AR71XX_SOC_AR7130;
96 chip = "7130";
97 break;
98
99 case AR71XX_REV_ID_MINOR_AR7141:
100 ar71xx_soc = AR71XX_SOC_AR7141;
101 chip = "7141";
102 break;
103
104 case AR71XX_REV_ID_MINOR_AR7161:
105 ar71xx_soc = AR71XX_SOC_AR7161;
106 chip = "7161";
107 break;
108 }
109 break;
110
111 case REV_ID_MAJOR_AR7240:
112 ar71xx_soc = AR71XX_SOC_AR7240;
113 chip = "7240";
114 rev = id & AR724X_REV_ID_REVISION_MASK;
115 break;
116
117 case REV_ID_MAJOR_AR7241:
118 ar71xx_soc = AR71XX_SOC_AR7241;
119 chip = "7241";
120 rev = id & AR724X_REV_ID_REVISION_MASK;
121 break;
122
123 case REV_ID_MAJOR_AR7242:
124 ar71xx_soc = AR71XX_SOC_AR7242;
125 chip = "7242";
126 rev = id & AR724X_REV_ID_REVISION_MASK;
127 break;
128
129 case REV_ID_MAJOR_AR913X:
130 minor = id & AR91XX_REV_ID_MINOR_MASK;
131 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
132 rev &= AR91XX_REV_ID_REVISION_MASK;
133 switch (minor) {
134 case AR91XX_REV_ID_MINOR_AR9130:
135 ar71xx_soc = AR71XX_SOC_AR9130;
136 chip = "9130";
137 break;
138
139 case AR91XX_REV_ID_MINOR_AR9132:
140 ar71xx_soc = AR71XX_SOC_AR9132;
141 chip = "9132";
142 break;
143 }
144 break;
145
146 case REV_ID_MAJOR_AR9330:
147 ar71xx_soc = AR71XX_SOC_AR9330;
148 chip = "9330";
149 rev = id & AR933X_REV_ID_REVISION_MASK;
150 break;
151
152 case REV_ID_MAJOR_AR9331:
153 ar71xx_soc = AR71XX_SOC_AR9331;
154 chip = "9331";
155 rev = id & AR933X_REV_ID_REVISION_MASK;
156 break;
157
158 case REV_ID_MAJOR_AR9342:
159 ar71xx_soc = AR71XX_SOC_AR9342;
160 chip = "9342";
161 rev = id & AR934X_REV_ID_REVISION_MASK;
162 break;
163
164 case REV_ID_MAJOR_AR9344:
165 ar71xx_soc = AR71XX_SOC_AR9344;
166 chip = "9344";
167 rev = id & AR934X_REV_ID_REVISION_MASK;
168 break;
169
170 default:
171 panic("ar71xx: unknown chip id:0x%08x\n", id);
172 }
173
174 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
175 pr_info("SoC: %s\n", ar71xx_sys_type);
176 }
177
178 static void __init ar934x_detect_sys_frequency(void)
179 {
180 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
181
182 if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
183 ar71xx_ref_freq = 40 * 1000 * 1000;
184 else
185 ar71xx_ref_freq = 25 * 1000 * 1000;
186
187 clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
188
189 pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
190 out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
191 ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
192 nint = AR934X_CPU_PLL_CFG_NINT_GET(pll);
193 frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
194 postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
195 ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
196 (postdiv + 1);
197
198 out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
199 ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
200 nint = AR934X_DDR_PLL_CFG_NINT_GET(pll);
201 frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
202 postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
203 ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
204 (postdiv + 1);
205
206 postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
207
208 if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
209 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
210 } else {
211 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
212 }
213
214 }
215
216 static void __init ar91xx_detect_sys_frequency(void)
217 {
218 u32 pll;
219 u32 freq;
220 u32 div;
221
222 ar71xx_ref_freq = 5 * 1000 * 1000;
223
224 pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
225
226 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
227 freq = div * ar71xx_ref_freq;
228
229 ar71xx_cpu_freq = freq;
230
231 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
232 ar71xx_ddr_freq = freq / div;
233
234 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
235 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
236 }
237
238 static void __init ar71xx_detect_sys_frequency(void)
239 {
240 u32 pll;
241 u32 freq;
242 u32 div;
243
244 ar71xx_ref_freq = 40 * 1000 * 1000;
245
246 pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
247
248 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
249 freq = div * ar71xx_ref_freq;
250
251 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
252 ar71xx_cpu_freq = freq / div;
253
254 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
255 ar71xx_ddr_freq = freq / div;
256
257 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
258 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
259 }
260
261 static void __init ar724x_detect_sys_frequency(void)
262 {
263 u32 pll;
264 u32 freq;
265 u32 div;
266
267 ar71xx_ref_freq = 5 * 1000 * 1000;
268
269 pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
270
271 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
272 freq = div * ar71xx_ref_freq;
273
274 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
275 freq *= div;
276
277 ar71xx_cpu_freq = freq;
278
279 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
280 ar71xx_ddr_freq = freq / div;
281
282 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
283 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
284 }
285
286 static void __init detect_sys_frequency(void)
287 {
288 switch (ar71xx_soc) {
289 case AR71XX_SOC_AR7130:
290 case AR71XX_SOC_AR7141:
291 case AR71XX_SOC_AR7161:
292 ar71xx_detect_sys_frequency();
293 break;
294
295 case AR71XX_SOC_AR7240:
296 case AR71XX_SOC_AR7241:
297 case AR71XX_SOC_AR7242:
298 ar724x_detect_sys_frequency();
299 break;
300
301 case AR71XX_SOC_AR9130:
302 case AR71XX_SOC_AR9132:
303 ar91xx_detect_sys_frequency();
304 break;
305
306 case AR71XX_SOC_AR9341:
307 case AR71XX_SOC_AR9342:
308 case AR71XX_SOC_AR9344:
309 ar934x_detect_sys_frequency();
310 break;
311 default:
312 BUG();
313 }
314 }
315
316 const char *get_system_type(void)
317 {
318 return ar71xx_sys_type;
319 }
320
321 unsigned int __cpuinit get_c0_compare_irq(void)
322 {
323 return CP0_LEGACY_COMPARE_IRQ;
324 }
325
326 void __init plat_mem_setup(void)
327 {
328 set_io_port_base(KSEG1);
329
330 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
331 AR71XX_DDR_CTRL_SIZE);
332
333 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
334 AR71XX_PLL_SIZE);
335
336 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
337 AR71XX_RESET_SIZE);
338
339 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
340
341 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
342 AR71XX_USB_CTRL_SIZE);
343
344 ar71xx_detect_mem_size();
345 ar71xx_detect_sys_type();
346 detect_sys_frequency();
347
348 pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
349 "Ref:%u.%03uMHz",
350 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
351 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000,
352 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
353 ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000);
354
355 _machine_restart = ar71xx_restart;
356 _machine_halt = ar71xx_halt;
357 pm_power_off = ar71xx_halt;
358 }
359
360 void __init plat_time_init(void)
361 {
362 mips_hpt_frequency = ar71xx_cpu_freq / 2;
363 }
364
365 __setup("board=", mips_machtype_setup);
366
367 static int __init ar71xx_machine_setup(void)
368 {
369 ar71xx_gpio_init();
370
371 ar71xx_add_device_uart();
372 ar71xx_add_device_wdt();
373
374 mips_machine_setup();
375 return 0;
376 }
377
378 arch_initcall(ar71xx_machine_setup);
379
380 static void __init ar71xx_generic_init(void)
381 {
382 /* Nothing to do */
383 }
384
385 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
386 ar71xx_generic_init);