043300c18802683561c55fccf6a8dcbfb0b23d83
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
26 #include <asm/mach-ath79/irq.h>
27
28 #include "common.h"
29 #include "dev-eth.h"
30
31 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32
33 static struct resource ath79_mdio0_resources[] = {
34 {
35 .name = "mdio_base",
36 .flags = IORESOURCE_MEM,
37 .start = AR71XX_GE0_BASE,
38 .end = AR71XX_GE0_BASE + 0x200 - 1,
39 }
40 };
41
42 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43
44 struct platform_device ath79_mdio0_device = {
45 .name = "ag71xx-mdio",
46 .id = 0,
47 .resource = ath79_mdio0_resources,
48 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .dev = {
50 .platform_data = &ath79_mdio0_data,
51 },
52 };
53
54 static struct resource ath79_mdio1_resources[] = {
55 {
56 .name = "mdio_base",
57 .flags = IORESOURCE_MEM,
58 .start = AR71XX_GE1_BASE,
59 .end = AR71XX_GE1_BASE + 0x200 - 1,
60 }
61 };
62
63 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64
65 struct platform_device ath79_mdio1_device = {
66 .name = "ag71xx-mdio",
67 .id = 1,
68 .resource = ath79_mdio1_resources,
69 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .dev = {
71 .platform_data = &ath79_mdio1_data,
72 },
73 };
74
75 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
76 {
77 void __iomem *base;
78 u32 t;
79
80 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81
82 t = __raw_readl(base + cfg_reg);
83 t &= ~(3 << shift);
84 t |= (2 << shift);
85 __raw_writel(t, base + cfg_reg);
86 udelay(100);
87
88 __raw_writel(pll_val, base + pll_reg);
89
90 t |= (3 << shift);
91 __raw_writel(t, base + cfg_reg);
92 udelay(100);
93
94 t &= ~(3 << shift);
95 __raw_writel(t, base + cfg_reg);
96 udelay(100);
97
98 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
99 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
100
101 iounmap(base);
102 }
103
104 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
105 unsigned int mii_if)
106 {
107 void __iomem *base;
108 u32 t;
109
110 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111
112 t = __raw_readl(base + reg);
113 t &= ~(AR71XX_MII_CTRL_IF_MASK);
114 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
115 __raw_writel(t, base + reg);
116
117 iounmap(base);
118 }
119
120 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
121 {
122 void __iomem *base;
123 unsigned int mii_speed;
124 u32 t;
125
126 switch (speed) {
127 case SPEED_10:
128 mii_speed = AR71XX_MII_CTRL_SPEED_10;
129 break;
130 case SPEED_100:
131 mii_speed = AR71XX_MII_CTRL_SPEED_100;
132 break;
133 case SPEED_1000:
134 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
135 break;
136 default:
137 BUG();
138 }
139
140 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141
142 t = __raw_readl(base + reg);
143 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
144 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
145 __raw_writel(t, base + reg);
146
147 iounmap(base);
148 }
149
150 static unsigned long ar934x_get_mdio_ref_clock(void)
151 {
152 void __iomem *base;
153 unsigned long ret;
154 u32 t;
155
156 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
157
158 ret = 0;
159 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
160 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
161 ret = 100 * 1000 * 1000;
162 } else {
163 struct clk *clk;
164
165 clk = clk_get(NULL, "ref");
166 if (!IS_ERR(clk))
167 ret = clk_get_rate(clk);
168 }
169
170 iounmap(base);
171
172 return ret;
173 }
174
175 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
176 {
177 struct platform_device *mdio_dev;
178 struct ag71xx_mdio_platform_data *mdio_data;
179 unsigned int max_id;
180
181 if (ath79_soc == ATH79_SOC_AR9341 ||
182 ath79_soc == ATH79_SOC_AR9342 ||
183 ath79_soc == ATH79_SOC_AR9344 ||
184 ath79_soc == ATH79_SOC_QCA9558)
185 max_id = 1;
186 else
187 max_id = 0;
188
189 if (id > max_id) {
190 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
191 return;
192 }
193
194 switch (ath79_soc) {
195 case ATH79_SOC_AR7241:
196 case ATH79_SOC_AR9330:
197 case ATH79_SOC_AR9331:
198 mdio_dev = &ath79_mdio1_device;
199 mdio_data = &ath79_mdio1_data;
200 break;
201
202 case ATH79_SOC_AR9341:
203 case ATH79_SOC_AR9342:
204 case ATH79_SOC_AR9344:
205 case ATH79_SOC_QCA9558:
206 if (id == 0) {
207 mdio_dev = &ath79_mdio0_device;
208 mdio_data = &ath79_mdio0_data;
209 } else {
210 mdio_dev = &ath79_mdio1_device;
211 mdio_data = &ath79_mdio1_data;
212 }
213 break;
214
215 case ATH79_SOC_AR7242:
216 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
217 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
218 AR71XX_ETH0_PLL_SHIFT);
219 /* fall through */
220 default:
221 mdio_dev = &ath79_mdio0_device;
222 mdio_data = &ath79_mdio0_data;
223 break;
224 }
225
226 mdio_data->phy_mask = phy_mask;
227
228 switch (ath79_soc) {
229 case ATH79_SOC_AR7240:
230 mdio_data->is_ar7240 = 1;
231 /* fall through */
232 case ATH79_SOC_AR7241:
233 mdio_data->builtin_switch = 1;
234 break;
235
236 case ATH79_SOC_AR9330:
237 mdio_data->is_ar9330 = 1;
238 /* fall through */
239 case ATH79_SOC_AR9331:
240 mdio_data->builtin_switch = 1;
241 break;
242
243 case ATH79_SOC_AR9341:
244 case ATH79_SOC_AR9342:
245 case ATH79_SOC_AR9344:
246 if (id == 1) {
247 mdio_data->builtin_switch = 1;
248 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
249 mdio_data->mdio_clock = 6250000;
250 }
251 mdio_data->is_ar934x = 1;
252 break;
253 case ATH79_SOC_QCA9558:
254 if (id == 1)
255 mdio_data->builtin_switch = 1;
256 mdio_data->is_ar934x = 1;
257 break;
258
259 default:
260 break;
261 }
262
263 platform_device_register(mdio_dev);
264 }
265
266 struct ath79_eth_pll_data ath79_eth0_pll_data;
267 struct ath79_eth_pll_data ath79_eth1_pll_data;
268
269 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
270 {
271 struct ath79_eth_pll_data *pll_data;
272 u32 pll_val;
273
274 switch (mac) {
275 case 0:
276 pll_data = &ath79_eth0_pll_data;
277 break;
278 case 1:
279 pll_data = &ath79_eth1_pll_data;
280 break;
281 default:
282 BUG();
283 }
284
285 switch (speed) {
286 case SPEED_10:
287 pll_val = pll_data->pll_10;
288 break;
289 case SPEED_100:
290 pll_val = pll_data->pll_100;
291 break;
292 case SPEED_1000:
293 pll_val = pll_data->pll_1000;
294 break;
295 default:
296 BUG();
297 }
298
299 return pll_val;
300 }
301
302 static void ath79_set_speed_ge0(int speed)
303 {
304 u32 val = ath79_get_eth_pll(0, speed);
305
306 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
307 val, AR71XX_ETH0_PLL_SHIFT);
308 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
309 }
310
311 static void ath79_set_speed_ge1(int speed)
312 {
313 u32 val = ath79_get_eth_pll(1, speed);
314
315 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
316 val, AR71XX_ETH1_PLL_SHIFT);
317 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
318 }
319
320 static void ar7242_set_speed_ge0(int speed)
321 {
322 u32 val = ath79_get_eth_pll(0, speed);
323 void __iomem *base;
324
325 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
326 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
327 iounmap(base);
328 }
329
330 static void ar91xx_set_speed_ge0(int speed)
331 {
332 u32 val = ath79_get_eth_pll(0, speed);
333
334 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
335 val, AR913X_ETH0_PLL_SHIFT);
336 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
337 }
338
339 static void ar91xx_set_speed_ge1(int speed)
340 {
341 u32 val = ath79_get_eth_pll(1, speed);
342
343 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
344 val, AR913X_ETH1_PLL_SHIFT);
345 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
346 }
347
348 static void ar934x_set_speed_ge0(int speed)
349 {
350 void __iomem *base;
351 u32 val = ath79_get_eth_pll(0, speed);
352
353 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
354 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
355 iounmap(base);
356 }
357
358 static void qca955x_set_speed_xmii(int speed)
359 {
360 void __iomem *base;
361 u32 val = ath79_get_eth_pll(0, speed);
362
363 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
364 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
365 iounmap(base);
366 }
367
368 static void qca955x_set_speed_sgmii(int speed)
369 {
370 void __iomem *base;
371 u32 val = ath79_get_eth_pll(1, speed);
372
373 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
374 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
375 iounmap(base);
376 }
377
378 static void ath79_set_speed_dummy(int speed)
379 {
380 }
381
382 static void ath79_ddr_no_flush(void)
383 {
384 }
385
386 static void ath79_ddr_flush_ge0(void)
387 {
388 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
389 }
390
391 static void ath79_ddr_flush_ge1(void)
392 {
393 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
394 }
395
396 static void ar724x_ddr_flush_ge0(void)
397 {
398 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
399 }
400
401 static void ar724x_ddr_flush_ge1(void)
402 {
403 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
404 }
405
406 static void ar91xx_ddr_flush_ge0(void)
407 {
408 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
409 }
410
411 static void ar91xx_ddr_flush_ge1(void)
412 {
413 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
414 }
415
416 static void ar933x_ddr_flush_ge0(void)
417 {
418 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
419 }
420
421 static void ar933x_ddr_flush_ge1(void)
422 {
423 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
424 }
425
426 static struct resource ath79_eth0_resources[] = {
427 {
428 .name = "mac_base",
429 .flags = IORESOURCE_MEM,
430 .start = AR71XX_GE0_BASE,
431 .end = AR71XX_GE0_BASE + 0x200 - 1,
432 }, {
433 .name = "mac_irq",
434 .flags = IORESOURCE_IRQ,
435 .start = ATH79_CPU_IRQ_GE0,
436 .end = ATH79_CPU_IRQ_GE0,
437 },
438 };
439
440 struct ag71xx_platform_data ath79_eth0_data = {
441 .reset_bit = AR71XX_RESET_GE0_MAC,
442 };
443
444 struct platform_device ath79_eth0_device = {
445 .name = "ag71xx",
446 .id = 0,
447 .resource = ath79_eth0_resources,
448 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
449 .dev = {
450 .platform_data = &ath79_eth0_data,
451 },
452 };
453
454 static struct resource ath79_eth1_resources[] = {
455 {
456 .name = "mac_base",
457 .flags = IORESOURCE_MEM,
458 .start = AR71XX_GE1_BASE,
459 .end = AR71XX_GE1_BASE + 0x200 - 1,
460 }, {
461 .name = "mac_irq",
462 .flags = IORESOURCE_IRQ,
463 .start = ATH79_CPU_IRQ_GE1,
464 .end = ATH79_CPU_IRQ_GE1,
465 },
466 };
467
468 struct ag71xx_platform_data ath79_eth1_data = {
469 .reset_bit = AR71XX_RESET_GE1_MAC,
470 };
471
472 struct platform_device ath79_eth1_device = {
473 .name = "ag71xx",
474 .id = 1,
475 .resource = ath79_eth1_resources,
476 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
477 .dev = {
478 .platform_data = &ath79_eth1_data,
479 },
480 };
481
482 struct ag71xx_switch_platform_data ath79_switch_data;
483
484 #define AR71XX_PLL_VAL_1000 0x00110000
485 #define AR71XX_PLL_VAL_100 0x00001099
486 #define AR71XX_PLL_VAL_10 0x00991099
487
488 #define AR724X_PLL_VAL_1000 0x00110000
489 #define AR724X_PLL_VAL_100 0x00001099
490 #define AR724X_PLL_VAL_10 0x00991099
491
492 #define AR7242_PLL_VAL_1000 0x16000000
493 #define AR7242_PLL_VAL_100 0x00000101
494 #define AR7242_PLL_VAL_10 0x00001616
495
496 #define AR913X_PLL_VAL_1000 0x1a000000
497 #define AR913X_PLL_VAL_100 0x13000a44
498 #define AR913X_PLL_VAL_10 0x00441099
499
500 #define AR933X_PLL_VAL_1000 0x00110000
501 #define AR933X_PLL_VAL_100 0x00001099
502 #define AR933X_PLL_VAL_10 0x00991099
503
504 #define AR934X_PLL_VAL_1000 0x16000000
505 #define AR934X_PLL_VAL_100 0x00000101
506 #define AR934X_PLL_VAL_10 0x00001616
507
508 static void __init ath79_init_eth_pll_data(unsigned int id)
509 {
510 struct ath79_eth_pll_data *pll_data;
511 u32 pll_10, pll_100, pll_1000;
512
513 switch (id) {
514 case 0:
515 pll_data = &ath79_eth0_pll_data;
516 break;
517 case 1:
518 pll_data = &ath79_eth1_pll_data;
519 break;
520 default:
521 BUG();
522 }
523
524 switch (ath79_soc) {
525 case ATH79_SOC_AR7130:
526 case ATH79_SOC_AR7141:
527 case ATH79_SOC_AR7161:
528 pll_10 = AR71XX_PLL_VAL_10;
529 pll_100 = AR71XX_PLL_VAL_100;
530 pll_1000 = AR71XX_PLL_VAL_1000;
531 break;
532
533 case ATH79_SOC_AR7240:
534 case ATH79_SOC_AR7241:
535 pll_10 = AR724X_PLL_VAL_10;
536 pll_100 = AR724X_PLL_VAL_100;
537 pll_1000 = AR724X_PLL_VAL_1000;
538 break;
539
540 case ATH79_SOC_AR7242:
541 pll_10 = AR7242_PLL_VAL_10;
542 pll_100 = AR7242_PLL_VAL_100;
543 pll_1000 = AR7242_PLL_VAL_1000;
544 break;
545
546 case ATH79_SOC_AR9130:
547 case ATH79_SOC_AR9132:
548 pll_10 = AR913X_PLL_VAL_10;
549 pll_100 = AR913X_PLL_VAL_100;
550 pll_1000 = AR913X_PLL_VAL_1000;
551 break;
552
553 case ATH79_SOC_AR9330:
554 case ATH79_SOC_AR9331:
555 pll_10 = AR933X_PLL_VAL_10;
556 pll_100 = AR933X_PLL_VAL_100;
557 pll_1000 = AR933X_PLL_VAL_1000;
558 break;
559
560 case ATH79_SOC_AR9341:
561 case ATH79_SOC_AR9342:
562 case ATH79_SOC_AR9344:
563 case ATH79_SOC_QCA9558:
564 pll_10 = AR934X_PLL_VAL_10;
565 pll_100 = AR934X_PLL_VAL_100;
566 pll_1000 = AR934X_PLL_VAL_1000;
567 break;
568
569 default:
570 BUG();
571 }
572
573 if (!pll_data->pll_10)
574 pll_data->pll_10 = pll_10;
575
576 if (!pll_data->pll_100)
577 pll_data->pll_100 = pll_100;
578
579 if (!pll_data->pll_1000)
580 pll_data->pll_1000 = pll_1000;
581 }
582
583 static int __init ath79_setup_phy_if_mode(unsigned int id,
584 struct ag71xx_platform_data *pdata)
585 {
586 unsigned int mii_if;
587
588 switch (id) {
589 case 0:
590 switch (ath79_soc) {
591 case ATH79_SOC_AR7130:
592 case ATH79_SOC_AR7141:
593 case ATH79_SOC_AR7161:
594 case ATH79_SOC_AR9130:
595 case ATH79_SOC_AR9132:
596 switch (pdata->phy_if_mode) {
597 case PHY_INTERFACE_MODE_MII:
598 mii_if = AR71XX_MII0_CTRL_IF_MII;
599 break;
600 case PHY_INTERFACE_MODE_GMII:
601 mii_if = AR71XX_MII0_CTRL_IF_GMII;
602 break;
603 case PHY_INTERFACE_MODE_RGMII:
604 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
605 break;
606 case PHY_INTERFACE_MODE_RMII:
607 mii_if = AR71XX_MII0_CTRL_IF_RMII;
608 break;
609 default:
610 return -EINVAL;
611 }
612 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
613 break;
614
615 case ATH79_SOC_AR7240:
616 case ATH79_SOC_AR7241:
617 case ATH79_SOC_AR9330:
618 case ATH79_SOC_AR9331:
619 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
620 break;
621
622 case ATH79_SOC_AR7242:
623 /* FIXME */
624
625 case ATH79_SOC_AR9341:
626 case ATH79_SOC_AR9342:
627 case ATH79_SOC_AR9344:
628 switch (pdata->phy_if_mode) {
629 case PHY_INTERFACE_MODE_MII:
630 case PHY_INTERFACE_MODE_GMII:
631 case PHY_INTERFACE_MODE_RGMII:
632 case PHY_INTERFACE_MODE_RMII:
633 break;
634 default:
635 return -EINVAL;
636 }
637 break;
638
639 case ATH79_SOC_QCA9558:
640 switch (pdata->phy_if_mode) {
641 case PHY_INTERFACE_MODE_MII:
642 case PHY_INTERFACE_MODE_RGMII:
643 case PHY_INTERFACE_MODE_SGMII:
644 break;
645 default:
646 return -EINVAL;
647 }
648 break;
649
650 default:
651 BUG();
652 }
653 break;
654 case 1:
655 switch (ath79_soc) {
656 case ATH79_SOC_AR7130:
657 case ATH79_SOC_AR7141:
658 case ATH79_SOC_AR7161:
659 case ATH79_SOC_AR9130:
660 case ATH79_SOC_AR9132:
661 switch (pdata->phy_if_mode) {
662 case PHY_INTERFACE_MODE_RMII:
663 mii_if = AR71XX_MII1_CTRL_IF_RMII;
664 break;
665 case PHY_INTERFACE_MODE_RGMII:
666 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
667 break;
668 default:
669 return -EINVAL;
670 }
671 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
672 break;
673
674 case ATH79_SOC_AR7240:
675 case ATH79_SOC_AR7241:
676 case ATH79_SOC_AR9330:
677 case ATH79_SOC_AR9331:
678 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
679 break;
680
681 case ATH79_SOC_AR7242:
682 /* FIXME */
683
684 case ATH79_SOC_AR9341:
685 case ATH79_SOC_AR9342:
686 case ATH79_SOC_AR9344:
687 switch (pdata->phy_if_mode) {
688 case PHY_INTERFACE_MODE_MII:
689 case PHY_INTERFACE_MODE_GMII:
690 break;
691 default:
692 return -EINVAL;
693 }
694 break;
695
696 case ATH79_SOC_QCA9558:
697 switch (pdata->phy_if_mode) {
698 case PHY_INTERFACE_MODE_MII:
699 case PHY_INTERFACE_MODE_RGMII:
700 case PHY_INTERFACE_MODE_SGMII:
701 break;
702 default:
703 return -EINVAL;
704 }
705 break;
706
707 default:
708 BUG();
709 }
710 break;
711 }
712
713 return 0;
714 }
715
716 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
717 {
718 void __iomem *base;
719 u32 t;
720
721 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
722
723 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
724 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
725 if (mac)
726 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
727 if (mdio)
728 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
729 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
730
731 iounmap(base);
732 }
733
734 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
735 {
736 void __iomem *base;
737 u32 t;
738
739 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
740
741 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
742
743 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
744 AR934X_ETH_CFG_MII_GMAC0 |
745 AR934X_ETH_CFG_GMII_GMAC0 |
746 AR934X_ETH_CFG_SW_ONLY_MODE |
747 AR934X_ETH_CFG_SW_PHY_SWAP);
748
749 t |= mask;
750
751 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
752 /* flush write */
753 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
754
755 iounmap(base);
756 }
757
758 static int ath79_eth_instance __initdata;
759 void __init ath79_register_eth(unsigned int id)
760 {
761 struct platform_device *pdev;
762 struct ag71xx_platform_data *pdata;
763 int err;
764
765 if (id > 1) {
766 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
767 return;
768 }
769
770 ath79_init_eth_pll_data(id);
771
772 if (id == 0)
773 pdev = &ath79_eth0_device;
774 else
775 pdev = &ath79_eth1_device;
776
777 pdata = pdev->dev.platform_data;
778
779 err = ath79_setup_phy_if_mode(id, pdata);
780 if (err) {
781 printk(KERN_ERR
782 "ar71xx: invalid PHY interface mode for GE%u\n", id);
783 return;
784 }
785
786 switch (ath79_soc) {
787 case ATH79_SOC_AR7130:
788 if (id == 0) {
789 pdata->ddr_flush = ath79_ddr_flush_ge0;
790 pdata->set_speed = ath79_set_speed_ge0;
791 } else {
792 pdata->ddr_flush = ath79_ddr_flush_ge1;
793 pdata->set_speed = ath79_set_speed_ge1;
794 }
795 break;
796
797 case ATH79_SOC_AR7141:
798 case ATH79_SOC_AR7161:
799 if (id == 0) {
800 pdata->ddr_flush = ath79_ddr_flush_ge0;
801 pdata->set_speed = ath79_set_speed_ge0;
802 } else {
803 pdata->ddr_flush = ath79_ddr_flush_ge1;
804 pdata->set_speed = ath79_set_speed_ge1;
805 }
806 pdata->has_gbit = 1;
807 break;
808
809 case ATH79_SOC_AR7242:
810 if (id == 0) {
811 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
812 AR71XX_RESET_GE0_PHY;
813 pdata->ddr_flush = ar724x_ddr_flush_ge0;
814 pdata->set_speed = ar7242_set_speed_ge0;
815 } else {
816 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
817 AR71XX_RESET_GE1_PHY;
818 pdata->ddr_flush = ar724x_ddr_flush_ge1;
819 pdata->set_speed = ath79_set_speed_dummy;
820 }
821 pdata->has_gbit = 1;
822 pdata->is_ar724x = 1;
823
824 if (!pdata->fifo_cfg1)
825 pdata->fifo_cfg1 = 0x0010ffff;
826 if (!pdata->fifo_cfg2)
827 pdata->fifo_cfg2 = 0x015500aa;
828 if (!pdata->fifo_cfg3)
829 pdata->fifo_cfg3 = 0x01f00140;
830 break;
831
832 case ATH79_SOC_AR7241:
833 if (id == 0)
834 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
835 else
836 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
837 /* fall through */
838 case ATH79_SOC_AR7240:
839 if (id == 0) {
840 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
841 pdata->ddr_flush = ar724x_ddr_flush_ge0;
842 pdata->set_speed = ath79_set_speed_dummy;
843
844 pdata->phy_mask = BIT(4);
845 } else {
846 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
847 pdata->ddr_flush = ar724x_ddr_flush_ge1;
848 pdata->set_speed = ath79_set_speed_dummy;
849
850 pdata->speed = SPEED_1000;
851 pdata->duplex = DUPLEX_FULL;
852 pdata->switch_data = &ath79_switch_data;
853
854 ath79_switch_data.phy_poll_mask |= BIT(4);
855 }
856 pdata->has_gbit = 1;
857 pdata->is_ar724x = 1;
858 if (ath79_soc == ATH79_SOC_AR7240)
859 pdata->is_ar7240 = 1;
860
861 if (!pdata->fifo_cfg1)
862 pdata->fifo_cfg1 = 0x0010ffff;
863 if (!pdata->fifo_cfg2)
864 pdata->fifo_cfg2 = 0x015500aa;
865 if (!pdata->fifo_cfg3)
866 pdata->fifo_cfg3 = 0x01f00140;
867 break;
868
869 case ATH79_SOC_AR9130:
870 if (id == 0) {
871 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
872 pdata->set_speed = ar91xx_set_speed_ge0;
873 } else {
874 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
875 pdata->set_speed = ar91xx_set_speed_ge1;
876 }
877 pdata->is_ar91xx = 1;
878 break;
879
880 case ATH79_SOC_AR9132:
881 if (id == 0) {
882 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
883 pdata->set_speed = ar91xx_set_speed_ge0;
884 } else {
885 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
886 pdata->set_speed = ar91xx_set_speed_ge1;
887 }
888 pdata->is_ar91xx = 1;
889 pdata->has_gbit = 1;
890 break;
891
892 case ATH79_SOC_AR9330:
893 case ATH79_SOC_AR9331:
894 if (id == 0) {
895 pdata->reset_bit = AR933X_RESET_GE0_MAC |
896 AR933X_RESET_GE0_MDIO;
897 pdata->ddr_flush = ar933x_ddr_flush_ge0;
898 pdata->set_speed = ath79_set_speed_dummy;
899
900 pdata->phy_mask = BIT(4);
901 } else {
902 pdata->reset_bit = AR933X_RESET_GE1_MAC |
903 AR933X_RESET_GE1_MDIO;
904 pdata->ddr_flush = ar933x_ddr_flush_ge1;
905 pdata->set_speed = ath79_set_speed_dummy;
906
907 pdata->speed = SPEED_1000;
908 pdata->duplex = DUPLEX_FULL;
909 pdata->switch_data = &ath79_switch_data;
910
911 ath79_switch_data.phy_poll_mask |= BIT(4);
912 }
913
914 pdata->has_gbit = 1;
915 pdata->is_ar724x = 1;
916
917 if (!pdata->fifo_cfg1)
918 pdata->fifo_cfg1 = 0x0010ffff;
919 if (!pdata->fifo_cfg2)
920 pdata->fifo_cfg2 = 0x015500aa;
921 if (!pdata->fifo_cfg3)
922 pdata->fifo_cfg3 = 0x01f00140;
923 break;
924
925 case ATH79_SOC_AR9341:
926 case ATH79_SOC_AR9342:
927 case ATH79_SOC_AR9344:
928 if (id == 0) {
929 pdata->reset_bit = AR934X_RESET_GE0_MAC |
930 AR934X_RESET_GE0_MDIO;
931 pdata->set_speed = ar934x_set_speed_ge0;
932 } else {
933 pdata->reset_bit = AR934X_RESET_GE1_MAC |
934 AR934X_RESET_GE1_MDIO;
935 pdata->set_speed = ath79_set_speed_dummy;
936
937 pdata->switch_data = &ath79_switch_data;
938
939 /* reset the built-in switch */
940 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
941 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
942 }
943
944 pdata->ddr_flush = ath79_ddr_no_flush;
945 pdata->has_gbit = 1;
946 pdata->is_ar724x = 1;
947
948 if (!pdata->fifo_cfg1)
949 pdata->fifo_cfg1 = 0x0010ffff;
950 if (!pdata->fifo_cfg2)
951 pdata->fifo_cfg2 = 0x015500aa;
952 if (!pdata->fifo_cfg3)
953 pdata->fifo_cfg3 = 0x01f00140;
954 break;
955
956 case ATH79_SOC_QCA9558:
957 if (id == 0) {
958 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
959 QCA955X_RESET_GE0_MDIO;
960 pdata->set_speed = qca955x_set_speed_xmii;
961 } else {
962 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
963 QCA955X_RESET_GE1_MDIO;
964 pdata->set_speed = qca955x_set_speed_sgmii;
965 }
966
967 pdata->ddr_flush = ath79_ddr_no_flush;
968 pdata->has_gbit = 1;
969 pdata->is_ar724x = 1;
970
971 if (!pdata->fifo_cfg1)
972 pdata->fifo_cfg1 = 0x0010ffff;
973 if (!pdata->fifo_cfg2)
974 pdata->fifo_cfg2 = 0x015500aa;
975 if (!pdata->fifo_cfg3)
976 pdata->fifo_cfg3 = 0x01f00140;
977 break;
978
979 default:
980 BUG();
981 }
982
983 switch (pdata->phy_if_mode) {
984 case PHY_INTERFACE_MODE_GMII:
985 case PHY_INTERFACE_MODE_RGMII:
986 case PHY_INTERFACE_MODE_SGMII:
987 if (!pdata->has_gbit) {
988 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
989 id);
990 return;
991 }
992 /* fallthrough */
993 default:
994 break;
995 }
996
997 if (!is_valid_ether_addr(pdata->mac_addr)) {
998 random_ether_addr(pdata->mac_addr);
999 printk(KERN_DEBUG
1000 "ar71xx: using random MAC address for eth%d\n",
1001 ath79_eth_instance);
1002 }
1003
1004 if (pdata->mii_bus_dev == NULL) {
1005 switch (ath79_soc) {
1006 case ATH79_SOC_AR9341:
1007 case ATH79_SOC_AR9342:
1008 case ATH79_SOC_AR9344:
1009 if (id == 0)
1010 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1011 else
1012 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1013 break;
1014
1015 case ATH79_SOC_AR7241:
1016 case ATH79_SOC_AR9330:
1017 case ATH79_SOC_AR9331:
1018 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1019 break;
1020
1021 case ATH79_SOC_QCA9558:
1022 /* don't assign any MDIO device by default */
1023 break;
1024
1025 default:
1026 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1027 break;
1028 }
1029 }
1030
1031 /* Reset the device */
1032 ath79_device_reset_set(pdata->reset_bit);
1033 mdelay(100);
1034
1035 ath79_device_reset_clear(pdata->reset_bit);
1036 mdelay(100);
1037
1038 platform_device_register(pdev);
1039 ath79_eth_instance++;
1040 }
1041
1042 void __init ath79_set_mac_base(unsigned char *mac)
1043 {
1044 memcpy(ath79_mac_base, mac, ETH_ALEN);
1045 }
1046
1047 void __init ath79_parse_mac_addr(char *mac_str)
1048 {
1049 u8 tmp[ETH_ALEN];
1050 int t;
1051
1052 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1053 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1054
1055 if (t != ETH_ALEN)
1056 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1057 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1058
1059 if (t == ETH_ALEN)
1060 ath79_set_mac_base(tmp);
1061 else
1062 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1063 "\"%s\"\n", mac_str);
1064 }
1065
1066 static int __init ath79_ethaddr_setup(char *str)
1067 {
1068 ath79_parse_mac_addr(str);
1069 return 1;
1070 }
1071 __setup("ethaddr=", ath79_ethaddr_setup);
1072
1073 static int __init ath79_kmac_setup(char *str)
1074 {
1075 ath79_parse_mac_addr(str);
1076 return 1;
1077 }
1078 __setup("kmac=", ath79_kmac_setup);
1079
1080 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1081 int offset)
1082 {
1083 int t;
1084
1085 if (!dst)
1086 return;
1087
1088 if (!src || !is_valid_ether_addr(src)) {
1089 memset(dst, '\0', ETH_ALEN);
1090 return;
1091 }
1092
1093 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1094 t += offset;
1095
1096 dst[0] = src[0];
1097 dst[1] = src[1];
1098 dst[2] = src[2];
1099 dst[3] = (t >> 16) & 0xff;
1100 dst[4] = (t >> 8) & 0xff;
1101 dst[5] = t & 0xff;
1102 }
1103
1104 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1105 {
1106 int i;
1107
1108 if (!dst)
1109 return;
1110
1111 if (!src || !is_valid_ether_addr(src)) {
1112 memset(dst, '\0', ETH_ALEN);
1113 return;
1114 }
1115
1116 for (i = 0; i < ETH_ALEN; i++)
1117 dst[i] = src[i];
1118 dst[0] |= 0x02;
1119 }