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ar71xx: add a helper function for setting up ETH_CFG register on QCA955x
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
28
29 #include "common.h"
30 #include "dev-eth.h"
31
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33
34 static struct resource ath79_mdio0_resources[] = {
35 {
36 .name = "mdio_base",
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
40 }
41 };
42
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
44
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
47 .id = 0,
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .dev = {
51 .platform_data = &ath79_mdio0_data,
52 },
53 };
54
55 static struct resource ath79_mdio1_resources[] = {
56 {
57 .name = "mdio_base",
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
61 }
62 };
63
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
65
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
68 .id = 1,
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .dev = {
72 .platform_data = &ath79_mdio1_data,
73 },
74 };
75
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
77 {
78 void __iomem *base;
79 u32 t;
80
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82
83 t = __raw_readl(base + cfg_reg);
84 t &= ~(3 << shift);
85 t |= (2 << shift);
86 __raw_writel(t, base + cfg_reg);
87 udelay(100);
88
89 __raw_writel(pll_val, base + pll_reg);
90
91 t |= (3 << shift);
92 __raw_writel(t, base + cfg_reg);
93 udelay(100);
94
95 t &= ~(3 << shift);
96 __raw_writel(t, base + cfg_reg);
97 udelay(100);
98
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
101
102 iounmap(base);
103 }
104
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
106 unsigned int mii_if)
107 {
108 void __iomem *base;
109 u32 t;
110
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
117
118 iounmap(base);
119 }
120
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 {
123 void __iomem *base;
124 unsigned int mii_speed;
125 u32 t;
126
127 switch (speed) {
128 case SPEED_10:
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 break;
131 case SPEED_100:
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 break;
134 case SPEED_1000:
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
136 break;
137 default:
138 BUG();
139 }
140
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
147
148 iounmap(base);
149 }
150
151 static unsigned long ar934x_get_mdio_ref_clock(void)
152 {
153 void __iomem *base;
154 unsigned long ret;
155 u32 t;
156
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
158
159 ret = 0;
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
163 } else {
164 struct clk *clk;
165
166 clk = clk_get(NULL, "ref");
167 if (!IS_ERR(clk))
168 ret = clk_get_rate(clk);
169 }
170
171 iounmap(base);
172
173 return ret;
174 }
175
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 {
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
180 unsigned int max_id;
181
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558)
187 max_id = 1;
188 else
189 max_id = 0;
190
191 if (id > max_id) {
192 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
193 return;
194 }
195
196 switch (ath79_soc) {
197 case ATH79_SOC_AR7241:
198 case ATH79_SOC_AR9330:
199 case ATH79_SOC_AR9331:
200 case ATH79_SOC_QCA9533:
201 mdio_dev = &ath79_mdio1_device;
202 mdio_data = &ath79_mdio1_data;
203 break;
204
205 case ATH79_SOC_AR9341:
206 case ATH79_SOC_AR9342:
207 case ATH79_SOC_AR9344:
208 case ATH79_SOC_QCA9556:
209 case ATH79_SOC_QCA9558:
210 if (id == 0) {
211 mdio_dev = &ath79_mdio0_device;
212 mdio_data = &ath79_mdio0_data;
213 } else {
214 mdio_dev = &ath79_mdio1_device;
215 mdio_data = &ath79_mdio1_data;
216 }
217 break;
218
219 case ATH79_SOC_AR7242:
220 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
221 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
222 AR71XX_ETH0_PLL_SHIFT);
223 /* fall through */
224 default:
225 mdio_dev = &ath79_mdio0_device;
226 mdio_data = &ath79_mdio0_data;
227 break;
228 }
229
230 mdio_data->phy_mask = phy_mask;
231
232 switch (ath79_soc) {
233 case ATH79_SOC_AR7240:
234 mdio_data->is_ar7240 = 1;
235 /* fall through */
236 case ATH79_SOC_AR7241:
237 mdio_data->builtin_switch = 1;
238 break;
239
240 case ATH79_SOC_AR9330:
241 mdio_data->is_ar9330 = 1;
242 /* fall through */
243 case ATH79_SOC_AR9331:
244 mdio_data->builtin_switch = 1;
245 break;
246
247 case ATH79_SOC_AR9341:
248 case ATH79_SOC_AR9342:
249 case ATH79_SOC_AR9344:
250 if (id == 1) {
251 mdio_data->builtin_switch = 1;
252 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
253 mdio_data->mdio_clock = 6250000;
254 }
255 mdio_data->is_ar934x = 1;
256 break;
257
258 case ATH79_SOC_QCA9533:
259 mdio_data->builtin_switch = 1;
260 break;
261
262 case ATH79_SOC_QCA9556:
263 case ATH79_SOC_QCA9558:
264 mdio_data->is_ar934x = 1;
265 break;
266
267 default:
268 break;
269 }
270
271 platform_device_register(mdio_dev);
272 }
273
274 struct ath79_eth_pll_data ath79_eth0_pll_data;
275 struct ath79_eth_pll_data ath79_eth1_pll_data;
276
277 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
278 {
279 struct ath79_eth_pll_data *pll_data;
280 u32 pll_val;
281
282 switch (mac) {
283 case 0:
284 pll_data = &ath79_eth0_pll_data;
285 break;
286 case 1:
287 pll_data = &ath79_eth1_pll_data;
288 break;
289 default:
290 BUG();
291 }
292
293 switch (speed) {
294 case SPEED_10:
295 pll_val = pll_data->pll_10;
296 break;
297 case SPEED_100:
298 pll_val = pll_data->pll_100;
299 break;
300 case SPEED_1000:
301 pll_val = pll_data->pll_1000;
302 break;
303 default:
304 BUG();
305 }
306
307 return pll_val;
308 }
309
310 static void ath79_set_speed_ge0(int speed)
311 {
312 u32 val = ath79_get_eth_pll(0, speed);
313
314 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
315 val, AR71XX_ETH0_PLL_SHIFT);
316 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
317 }
318
319 static void ath79_set_speed_ge1(int speed)
320 {
321 u32 val = ath79_get_eth_pll(1, speed);
322
323 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
324 val, AR71XX_ETH1_PLL_SHIFT);
325 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
326 }
327
328 static void ar7242_set_speed_ge0(int speed)
329 {
330 u32 val = ath79_get_eth_pll(0, speed);
331 void __iomem *base;
332
333 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
334 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
335 iounmap(base);
336 }
337
338 static void ar91xx_set_speed_ge0(int speed)
339 {
340 u32 val = ath79_get_eth_pll(0, speed);
341
342 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
343 val, AR913X_ETH0_PLL_SHIFT);
344 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
345 }
346
347 static void ar91xx_set_speed_ge1(int speed)
348 {
349 u32 val = ath79_get_eth_pll(1, speed);
350
351 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
352 val, AR913X_ETH1_PLL_SHIFT);
353 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
354 }
355
356 static void ar934x_set_speed_ge0(int speed)
357 {
358 void __iomem *base;
359 u32 val = ath79_get_eth_pll(0, speed);
360
361 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
362 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
363 iounmap(base);
364 }
365
366 static void qca955x_set_speed_xmii(int speed)
367 {
368 void __iomem *base;
369 u32 val = ath79_get_eth_pll(0, speed);
370
371 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
372 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
373 iounmap(base);
374 }
375
376 static void qca955x_set_speed_sgmii(int speed)
377 {
378 void __iomem *base;
379 u32 val = ath79_get_eth_pll(1, speed);
380
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
383 iounmap(base);
384 }
385
386 static void ath79_set_speed_dummy(int speed)
387 {
388 }
389
390 static void ath79_ddr_no_flush(void)
391 {
392 }
393
394 static void ath79_ddr_flush_ge0(void)
395 {
396 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
397 }
398
399 static void ath79_ddr_flush_ge1(void)
400 {
401 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
402 }
403
404 static void ar724x_ddr_flush_ge0(void)
405 {
406 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
407 }
408
409 static void ar724x_ddr_flush_ge1(void)
410 {
411 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
412 }
413
414 static void ar91xx_ddr_flush_ge0(void)
415 {
416 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
417 }
418
419 static void ar91xx_ddr_flush_ge1(void)
420 {
421 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
422 }
423
424 static void ar933x_ddr_flush_ge0(void)
425 {
426 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
427 }
428
429 static void ar933x_ddr_flush_ge1(void)
430 {
431 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
432 }
433
434 static struct resource ath79_eth0_resources[] = {
435 {
436 .name = "mac_base",
437 .flags = IORESOURCE_MEM,
438 .start = AR71XX_GE0_BASE,
439 .end = AR71XX_GE0_BASE + 0x200 - 1,
440 }, {
441 .name = "mac_irq",
442 .flags = IORESOURCE_IRQ,
443 .start = ATH79_CPU_IRQ(4),
444 .end = ATH79_CPU_IRQ(4),
445 },
446 };
447
448 struct ag71xx_platform_data ath79_eth0_data = {
449 .reset_bit = AR71XX_RESET_GE0_MAC,
450 };
451
452 struct platform_device ath79_eth0_device = {
453 .name = "ag71xx",
454 .id = 0,
455 .resource = ath79_eth0_resources,
456 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
457 .dev = {
458 .platform_data = &ath79_eth0_data,
459 },
460 };
461
462 static struct resource ath79_eth1_resources[] = {
463 {
464 .name = "mac_base",
465 .flags = IORESOURCE_MEM,
466 .start = AR71XX_GE1_BASE,
467 .end = AR71XX_GE1_BASE + 0x200 - 1,
468 }, {
469 .name = "mac_irq",
470 .flags = IORESOURCE_IRQ,
471 .start = ATH79_CPU_IRQ(5),
472 .end = ATH79_CPU_IRQ(5),
473 },
474 };
475
476 struct ag71xx_platform_data ath79_eth1_data = {
477 .reset_bit = AR71XX_RESET_GE1_MAC,
478 };
479
480 struct platform_device ath79_eth1_device = {
481 .name = "ag71xx",
482 .id = 1,
483 .resource = ath79_eth1_resources,
484 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
485 .dev = {
486 .platform_data = &ath79_eth1_data,
487 },
488 };
489
490 struct ag71xx_switch_platform_data ath79_switch_data;
491
492 #define AR71XX_PLL_VAL_1000 0x00110000
493 #define AR71XX_PLL_VAL_100 0x00001099
494 #define AR71XX_PLL_VAL_10 0x00991099
495
496 #define AR724X_PLL_VAL_1000 0x00110000
497 #define AR724X_PLL_VAL_100 0x00001099
498 #define AR724X_PLL_VAL_10 0x00991099
499
500 #define AR7242_PLL_VAL_1000 0x16000000
501 #define AR7242_PLL_VAL_100 0x00000101
502 #define AR7242_PLL_VAL_10 0x00001616
503
504 #define AR913X_PLL_VAL_1000 0x1a000000
505 #define AR913X_PLL_VAL_100 0x13000a44
506 #define AR913X_PLL_VAL_10 0x00441099
507
508 #define AR933X_PLL_VAL_1000 0x00110000
509 #define AR933X_PLL_VAL_100 0x00001099
510 #define AR933X_PLL_VAL_10 0x00991099
511
512 #define AR934X_PLL_VAL_1000 0x16000000
513 #define AR934X_PLL_VAL_100 0x00000101
514 #define AR934X_PLL_VAL_10 0x00001616
515
516 static void __init ath79_init_eth_pll_data(unsigned int id)
517 {
518 struct ath79_eth_pll_data *pll_data;
519 u32 pll_10, pll_100, pll_1000;
520
521 switch (id) {
522 case 0:
523 pll_data = &ath79_eth0_pll_data;
524 break;
525 case 1:
526 pll_data = &ath79_eth1_pll_data;
527 break;
528 default:
529 BUG();
530 }
531
532 switch (ath79_soc) {
533 case ATH79_SOC_AR7130:
534 case ATH79_SOC_AR7141:
535 case ATH79_SOC_AR7161:
536 pll_10 = AR71XX_PLL_VAL_10;
537 pll_100 = AR71XX_PLL_VAL_100;
538 pll_1000 = AR71XX_PLL_VAL_1000;
539 break;
540
541 case ATH79_SOC_AR7240:
542 case ATH79_SOC_AR7241:
543 pll_10 = AR724X_PLL_VAL_10;
544 pll_100 = AR724X_PLL_VAL_100;
545 pll_1000 = AR724X_PLL_VAL_1000;
546 break;
547
548 case ATH79_SOC_AR7242:
549 pll_10 = AR7242_PLL_VAL_10;
550 pll_100 = AR7242_PLL_VAL_100;
551 pll_1000 = AR7242_PLL_VAL_1000;
552 break;
553
554 case ATH79_SOC_AR9130:
555 case ATH79_SOC_AR9132:
556 pll_10 = AR913X_PLL_VAL_10;
557 pll_100 = AR913X_PLL_VAL_100;
558 pll_1000 = AR913X_PLL_VAL_1000;
559 break;
560
561 case ATH79_SOC_AR9330:
562 case ATH79_SOC_AR9331:
563 pll_10 = AR933X_PLL_VAL_10;
564 pll_100 = AR933X_PLL_VAL_100;
565 pll_1000 = AR933X_PLL_VAL_1000;
566 break;
567
568 case ATH79_SOC_AR9341:
569 case ATH79_SOC_AR9342:
570 case ATH79_SOC_AR9344:
571 case ATH79_SOC_QCA9533:
572 case ATH79_SOC_QCA9556:
573 case ATH79_SOC_QCA9558:
574 pll_10 = AR934X_PLL_VAL_10;
575 pll_100 = AR934X_PLL_VAL_100;
576 pll_1000 = AR934X_PLL_VAL_1000;
577 break;
578
579 default:
580 BUG();
581 }
582
583 if (!pll_data->pll_10)
584 pll_data->pll_10 = pll_10;
585
586 if (!pll_data->pll_100)
587 pll_data->pll_100 = pll_100;
588
589 if (!pll_data->pll_1000)
590 pll_data->pll_1000 = pll_1000;
591 }
592
593 static int __init ath79_setup_phy_if_mode(unsigned int id,
594 struct ag71xx_platform_data *pdata)
595 {
596 unsigned int mii_if;
597
598 switch (id) {
599 case 0:
600 switch (ath79_soc) {
601 case ATH79_SOC_AR7130:
602 case ATH79_SOC_AR7141:
603 case ATH79_SOC_AR7161:
604 case ATH79_SOC_AR9130:
605 case ATH79_SOC_AR9132:
606 switch (pdata->phy_if_mode) {
607 case PHY_INTERFACE_MODE_MII:
608 mii_if = AR71XX_MII0_CTRL_IF_MII;
609 break;
610 case PHY_INTERFACE_MODE_GMII:
611 mii_if = AR71XX_MII0_CTRL_IF_GMII;
612 break;
613 case PHY_INTERFACE_MODE_RGMII:
614 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
615 break;
616 case PHY_INTERFACE_MODE_RMII:
617 mii_if = AR71XX_MII0_CTRL_IF_RMII;
618 break;
619 default:
620 return -EINVAL;
621 }
622 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
623 break;
624
625 case ATH79_SOC_AR7240:
626 case ATH79_SOC_AR7241:
627 case ATH79_SOC_AR9330:
628 case ATH79_SOC_AR9331:
629 case ATH79_SOC_QCA9533:
630 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
631 break;
632
633 case ATH79_SOC_AR7242:
634 /* FIXME */
635
636 case ATH79_SOC_AR9341:
637 case ATH79_SOC_AR9342:
638 case ATH79_SOC_AR9344:
639 switch (pdata->phy_if_mode) {
640 case PHY_INTERFACE_MODE_MII:
641 case PHY_INTERFACE_MODE_GMII:
642 case PHY_INTERFACE_MODE_RGMII:
643 case PHY_INTERFACE_MODE_RMII:
644 break;
645 default:
646 return -EINVAL;
647 }
648 break;
649
650 case ATH79_SOC_QCA9556:
651 case ATH79_SOC_QCA9558:
652 switch (pdata->phy_if_mode) {
653 case PHY_INTERFACE_MODE_MII:
654 case PHY_INTERFACE_MODE_RGMII:
655 case PHY_INTERFACE_MODE_SGMII:
656 break;
657 default:
658 return -EINVAL;
659 }
660 break;
661
662 default:
663 BUG();
664 }
665 break;
666 case 1:
667 switch (ath79_soc) {
668 case ATH79_SOC_AR7130:
669 case ATH79_SOC_AR7141:
670 case ATH79_SOC_AR7161:
671 case ATH79_SOC_AR9130:
672 case ATH79_SOC_AR9132:
673 switch (pdata->phy_if_mode) {
674 case PHY_INTERFACE_MODE_RMII:
675 mii_if = AR71XX_MII1_CTRL_IF_RMII;
676 break;
677 case PHY_INTERFACE_MODE_RGMII:
678 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
679 break;
680 default:
681 return -EINVAL;
682 }
683 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
684 break;
685
686 case ATH79_SOC_AR7240:
687 case ATH79_SOC_AR7241:
688 case ATH79_SOC_AR9330:
689 case ATH79_SOC_AR9331:
690 case ATH79_SOC_QCA9533:
691 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
692 break;
693
694 case ATH79_SOC_AR7242:
695 /* FIXME */
696
697 case ATH79_SOC_AR9341:
698 case ATH79_SOC_AR9342:
699 case ATH79_SOC_AR9344:
700 switch (pdata->phy_if_mode) {
701 case PHY_INTERFACE_MODE_MII:
702 case PHY_INTERFACE_MODE_GMII:
703 break;
704 default:
705 return -EINVAL;
706 }
707 break;
708
709 case ATH79_SOC_QCA9556:
710 case ATH79_SOC_QCA9558:
711 switch (pdata->phy_if_mode) {
712 case PHY_INTERFACE_MODE_MII:
713 case PHY_INTERFACE_MODE_RGMII:
714 case PHY_INTERFACE_MODE_SGMII:
715 break;
716 default:
717 return -EINVAL;
718 }
719 break;
720
721 default:
722 BUG();
723 }
724 break;
725 }
726
727 return 0;
728 }
729
730 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
731 {
732 void __iomem *base;
733 u32 t;
734
735 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
736
737 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
738 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
739 if (mac)
740 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
741 if (mdio)
742 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
743 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
744
745 iounmap(base);
746 }
747
748 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
749 {
750 void __iomem *base;
751 u32 t;
752
753 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
754
755 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
756
757 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
758 AR934X_ETH_CFG_MII_GMAC0 |
759 AR934X_ETH_CFG_GMII_GMAC0 |
760 AR934X_ETH_CFG_SW_ONLY_MODE |
761 AR934X_ETH_CFG_SW_PHY_SWAP);
762
763 t |= mask;
764
765 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
766 /* flush write */
767 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
768
769 iounmap(base);
770 }
771
772 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
773 {
774 void __iomem *base;
775 u32 t;
776
777 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
778
779 t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
780
781 t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
782
783 t |= mask;
784
785 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
786
787 iounmap(base);
788 }
789
790 static int ath79_eth_instance __initdata;
791 void __init ath79_register_eth(unsigned int id)
792 {
793 struct platform_device *pdev;
794 struct ag71xx_platform_data *pdata;
795 int err;
796
797 if (id > 1) {
798 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
799 return;
800 }
801
802 ath79_init_eth_pll_data(id);
803
804 if (id == 0)
805 pdev = &ath79_eth0_device;
806 else
807 pdev = &ath79_eth1_device;
808
809 pdata = pdev->dev.platform_data;
810
811 pdata->max_frame_len = 1540;
812 pdata->desc_pktlen_mask = 0xfff;
813
814 err = ath79_setup_phy_if_mode(id, pdata);
815 if (err) {
816 printk(KERN_ERR
817 "ar71xx: invalid PHY interface mode for GE%u\n", id);
818 return;
819 }
820
821 switch (ath79_soc) {
822 case ATH79_SOC_AR7130:
823 if (id == 0) {
824 pdata->ddr_flush = ath79_ddr_flush_ge0;
825 pdata->set_speed = ath79_set_speed_ge0;
826 } else {
827 pdata->ddr_flush = ath79_ddr_flush_ge1;
828 pdata->set_speed = ath79_set_speed_ge1;
829 }
830 break;
831
832 case ATH79_SOC_AR7141:
833 case ATH79_SOC_AR7161:
834 if (id == 0) {
835 pdata->ddr_flush = ath79_ddr_flush_ge0;
836 pdata->set_speed = ath79_set_speed_ge0;
837 } else {
838 pdata->ddr_flush = ath79_ddr_flush_ge1;
839 pdata->set_speed = ath79_set_speed_ge1;
840 }
841 pdata->has_gbit = 1;
842 break;
843
844 case ATH79_SOC_AR7242:
845 if (id == 0) {
846 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
847 AR71XX_RESET_GE0_PHY;
848 pdata->ddr_flush = ar724x_ddr_flush_ge0;
849 pdata->set_speed = ar7242_set_speed_ge0;
850 } else {
851 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
852 AR71XX_RESET_GE1_PHY;
853 pdata->ddr_flush = ar724x_ddr_flush_ge1;
854 pdata->set_speed = ath79_set_speed_dummy;
855 }
856 pdata->has_gbit = 1;
857 pdata->is_ar724x = 1;
858
859 if (!pdata->fifo_cfg1)
860 pdata->fifo_cfg1 = 0x0010ffff;
861 if (!pdata->fifo_cfg2)
862 pdata->fifo_cfg2 = 0x015500aa;
863 if (!pdata->fifo_cfg3)
864 pdata->fifo_cfg3 = 0x01f00140;
865 break;
866
867 case ATH79_SOC_AR7241:
868 if (id == 0)
869 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
870 else
871 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
872 /* fall through */
873 case ATH79_SOC_AR7240:
874 if (id == 0) {
875 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
876 pdata->ddr_flush = ar724x_ddr_flush_ge0;
877 pdata->set_speed = ath79_set_speed_dummy;
878
879 pdata->phy_mask = BIT(4);
880 } else {
881 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
882 pdata->ddr_flush = ar724x_ddr_flush_ge1;
883 pdata->set_speed = ath79_set_speed_dummy;
884
885 pdata->speed = SPEED_1000;
886 pdata->duplex = DUPLEX_FULL;
887 pdata->switch_data = &ath79_switch_data;
888
889 ath79_switch_data.phy_poll_mask |= BIT(4);
890 }
891 pdata->has_gbit = 1;
892 pdata->is_ar724x = 1;
893 if (ath79_soc == ATH79_SOC_AR7240)
894 pdata->is_ar7240 = 1;
895
896 if (!pdata->fifo_cfg1)
897 pdata->fifo_cfg1 = 0x0010ffff;
898 if (!pdata->fifo_cfg2)
899 pdata->fifo_cfg2 = 0x015500aa;
900 if (!pdata->fifo_cfg3)
901 pdata->fifo_cfg3 = 0x01f00140;
902 break;
903
904 case ATH79_SOC_AR9130:
905 if (id == 0) {
906 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
907 pdata->set_speed = ar91xx_set_speed_ge0;
908 } else {
909 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
910 pdata->set_speed = ar91xx_set_speed_ge1;
911 }
912 pdata->is_ar91xx = 1;
913 break;
914
915 case ATH79_SOC_AR9132:
916 if (id == 0) {
917 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
918 pdata->set_speed = ar91xx_set_speed_ge0;
919 } else {
920 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
921 pdata->set_speed = ar91xx_set_speed_ge1;
922 }
923 pdata->is_ar91xx = 1;
924 pdata->has_gbit = 1;
925 break;
926
927 case ATH79_SOC_AR9330:
928 case ATH79_SOC_AR9331:
929 if (id == 0) {
930 pdata->reset_bit = AR933X_RESET_GE0_MAC |
931 AR933X_RESET_GE0_MDIO;
932 pdata->ddr_flush = ar933x_ddr_flush_ge0;
933 pdata->set_speed = ath79_set_speed_dummy;
934
935 pdata->phy_mask = BIT(4);
936 } else {
937 pdata->reset_bit = AR933X_RESET_GE1_MAC |
938 AR933X_RESET_GE1_MDIO;
939 pdata->ddr_flush = ar933x_ddr_flush_ge1;
940 pdata->set_speed = ath79_set_speed_dummy;
941
942 pdata->speed = SPEED_1000;
943 pdata->duplex = DUPLEX_FULL;
944 pdata->switch_data = &ath79_switch_data;
945
946 ath79_switch_data.phy_poll_mask |= BIT(4);
947 }
948
949 pdata->has_gbit = 1;
950 pdata->is_ar724x = 1;
951
952 if (!pdata->fifo_cfg1)
953 pdata->fifo_cfg1 = 0x0010ffff;
954 if (!pdata->fifo_cfg2)
955 pdata->fifo_cfg2 = 0x015500aa;
956 if (!pdata->fifo_cfg3)
957 pdata->fifo_cfg3 = 0x01f00140;
958 break;
959
960 case ATH79_SOC_AR9341:
961 case ATH79_SOC_AR9342:
962 case ATH79_SOC_AR9344:
963 if (id == 0) {
964 pdata->reset_bit = AR934X_RESET_GE0_MAC |
965 AR934X_RESET_GE0_MDIO;
966 pdata->set_speed = ar934x_set_speed_ge0;
967 } else {
968 pdata->reset_bit = AR934X_RESET_GE1_MAC |
969 AR934X_RESET_GE1_MDIO;
970 pdata->set_speed = ath79_set_speed_dummy;
971
972 pdata->switch_data = &ath79_switch_data;
973
974 /* reset the built-in switch */
975 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
976 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
977 }
978
979 pdata->ddr_flush = ath79_ddr_no_flush;
980 pdata->has_gbit = 1;
981 pdata->is_ar724x = 1;
982
983 pdata->max_frame_len = SZ_16K - 1;
984 pdata->desc_pktlen_mask = SZ_16K - 1;
985
986 if (!pdata->fifo_cfg1)
987 pdata->fifo_cfg1 = 0x0010ffff;
988 if (!pdata->fifo_cfg2)
989 pdata->fifo_cfg2 = 0x015500aa;
990 if (!pdata->fifo_cfg3)
991 pdata->fifo_cfg3 = 0x01f00140;
992 break;
993
994 case ATH79_SOC_QCA9533:
995 if (id == 0) {
996 pdata->reset_bit = AR933X_RESET_GE0_MAC |
997 AR933X_RESET_GE0_MDIO;
998 pdata->set_speed = ath79_set_speed_dummy;
999
1000 pdata->phy_mask = BIT(4);
1001 } else {
1002 pdata->reset_bit = AR933X_RESET_GE1_MAC |
1003 AR933X_RESET_GE1_MDIO;
1004 pdata->set_speed = ath79_set_speed_dummy;
1005
1006 pdata->speed = SPEED_1000;
1007 pdata->duplex = DUPLEX_FULL;
1008 pdata->switch_data = &ath79_switch_data;
1009
1010 ath79_switch_data.phy_poll_mask |= BIT(4);
1011 }
1012
1013 pdata->ddr_flush = ath79_ddr_no_flush;
1014 pdata->has_gbit = 1;
1015 pdata->is_ar724x = 1;
1016
1017 if (!pdata->fifo_cfg1)
1018 pdata->fifo_cfg1 = 0x0010ffff;
1019 if (!pdata->fifo_cfg2)
1020 pdata->fifo_cfg2 = 0x015500aa;
1021 if (!pdata->fifo_cfg3)
1022 pdata->fifo_cfg3 = 0x01f00140;
1023 break;
1024
1025 case ATH79_SOC_QCA9556:
1026 case ATH79_SOC_QCA9558:
1027 if (id == 0) {
1028 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1029 QCA955X_RESET_GE0_MDIO;
1030 pdata->set_speed = qca955x_set_speed_xmii;
1031 } else {
1032 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1033 QCA955X_RESET_GE1_MDIO;
1034 pdata->set_speed = qca955x_set_speed_sgmii;
1035 }
1036
1037 pdata->ddr_flush = ath79_ddr_no_flush;
1038 pdata->has_gbit = 1;
1039 pdata->is_ar724x = 1;
1040
1041 /*
1042 * Limit the maximum frame length to 4095 bytes.
1043 * Although the documentation says that the hardware
1044 * limit is 16383 bytes but that does not work in
1045 * practice. It seems that the hardware only updates
1046 * the lowest 12 bits of the packet length field
1047 * in the RX descriptor.
1048 */
1049 pdata->max_frame_len = SZ_4K - 1;
1050 pdata->desc_pktlen_mask = SZ_16K - 1;
1051
1052 if (!pdata->fifo_cfg1)
1053 pdata->fifo_cfg1 = 0x0010ffff;
1054 if (!pdata->fifo_cfg2)
1055 pdata->fifo_cfg2 = 0x015500aa;
1056 if (!pdata->fifo_cfg3)
1057 pdata->fifo_cfg3 = 0x01f00140;
1058 break;
1059
1060 default:
1061 BUG();
1062 }
1063
1064 switch (pdata->phy_if_mode) {
1065 case PHY_INTERFACE_MODE_GMII:
1066 case PHY_INTERFACE_MODE_RGMII:
1067 case PHY_INTERFACE_MODE_SGMII:
1068 if (!pdata->has_gbit) {
1069 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1070 id);
1071 return;
1072 }
1073 /* fallthrough */
1074 default:
1075 break;
1076 }
1077
1078 if (!is_valid_ether_addr(pdata->mac_addr)) {
1079 random_ether_addr(pdata->mac_addr);
1080 printk(KERN_DEBUG
1081 "ar71xx: using random MAC address for eth%d\n",
1082 ath79_eth_instance);
1083 }
1084
1085 if (pdata->mii_bus_dev == NULL) {
1086 switch (ath79_soc) {
1087 case ATH79_SOC_AR9341:
1088 case ATH79_SOC_AR9342:
1089 case ATH79_SOC_AR9344:
1090 if (id == 0)
1091 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1092 else
1093 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1094 break;
1095
1096 case ATH79_SOC_AR7241:
1097 case ATH79_SOC_AR9330:
1098 case ATH79_SOC_AR9331:
1099 case ATH79_SOC_QCA9533:
1100 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1101 break;
1102
1103 case ATH79_SOC_QCA9556:
1104 case ATH79_SOC_QCA9558:
1105 /* don't assign any MDIO device by default */
1106 break;
1107
1108 default:
1109 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1110 break;
1111 }
1112 }
1113
1114 /* Reset the device */
1115 ath79_device_reset_set(pdata->reset_bit);
1116 mdelay(100);
1117
1118 ath79_device_reset_clear(pdata->reset_bit);
1119 mdelay(100);
1120
1121 platform_device_register(pdev);
1122 ath79_eth_instance++;
1123 }
1124
1125 void __init ath79_set_mac_base(unsigned char *mac)
1126 {
1127 memcpy(ath79_mac_base, mac, ETH_ALEN);
1128 }
1129
1130 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1131 {
1132 int t;
1133
1134 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1135 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1136
1137 if (t != ETH_ALEN)
1138 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1139 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1140
1141 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1142 memset(mac, 0, ETH_ALEN);
1143 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1144 mac_str);
1145 }
1146 }
1147
1148 static void __init ath79_set_mac_base_ascii(char *str)
1149 {
1150 u8 mac[ETH_ALEN];
1151
1152 ath79_parse_ascii_mac(str, mac);
1153 ath79_set_mac_base(mac);
1154 }
1155
1156 static int __init ath79_ethaddr_setup(char *str)
1157 {
1158 ath79_set_mac_base_ascii(str);
1159 return 1;
1160 }
1161 __setup("ethaddr=", ath79_ethaddr_setup);
1162
1163 static int __init ath79_kmac_setup(char *str)
1164 {
1165 ath79_set_mac_base_ascii(str);
1166 return 1;
1167 }
1168 __setup("kmac=", ath79_kmac_setup);
1169
1170 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1171 int offset)
1172 {
1173 int t;
1174
1175 if (!dst)
1176 return;
1177
1178 if (!src || !is_valid_ether_addr(src)) {
1179 memset(dst, '\0', ETH_ALEN);
1180 return;
1181 }
1182
1183 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1184 t += offset;
1185
1186 dst[0] = src[0];
1187 dst[1] = src[1];
1188 dst[2] = src[2];
1189 dst[3] = (t >> 16) & 0xff;
1190 dst[4] = (t >> 8) & 0xff;
1191 dst[5] = t & 0xff;
1192 }
1193
1194 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1195 {
1196 int i;
1197
1198 if (!dst)
1199 return;
1200
1201 if (!src || !is_valid_ether_addr(src)) {
1202 memset(dst, '\0', ETH_ALEN);
1203 return;
1204 }
1205
1206 for (i = 0; i < ETH_ALEN; i++)
1207 dst[i] = src[i];
1208 dst[0] |= 0x02;
1209 }
OpenWrt Source Repository