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[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
28
29 #include "common.h"
30 #include "dev-eth.h"
31
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33
34 static struct resource ath79_mdio0_resources[] = {
35 {
36 .name = "mdio_base",
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
40 }
41 };
42
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
44
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
47 .id = 0,
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .dev = {
51 .platform_data = &ath79_mdio0_data,
52 },
53 };
54
55 static struct resource ath79_mdio1_resources[] = {
56 {
57 .name = "mdio_base",
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
61 }
62 };
63
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
65
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
68 .id = 1,
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .dev = {
72 .platform_data = &ath79_mdio1_data,
73 },
74 };
75
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
77 {
78 void __iomem *base;
79 u32 t;
80
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82
83 t = __raw_readl(base + cfg_reg);
84 t &= ~(3 << shift);
85 t |= (2 << shift);
86 __raw_writel(t, base + cfg_reg);
87 udelay(100);
88
89 __raw_writel(pll_val, base + pll_reg);
90
91 t |= (3 << shift);
92 __raw_writel(t, base + cfg_reg);
93 udelay(100);
94
95 t &= ~(3 << shift);
96 __raw_writel(t, base + cfg_reg);
97 udelay(100);
98
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
101
102 iounmap(base);
103 }
104
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
106 unsigned int mii_if)
107 {
108 void __iomem *base;
109 u32 t;
110
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
117
118 iounmap(base);
119 }
120
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 {
123 void __iomem *base;
124 unsigned int mii_speed;
125 u32 t;
126
127 switch (speed) {
128 case SPEED_10:
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 break;
131 case SPEED_100:
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 break;
134 case SPEED_1000:
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
136 break;
137 default:
138 BUG();
139 }
140
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
147
148 iounmap(base);
149 }
150
151 static unsigned long ar934x_get_mdio_ref_clock(void)
152 {
153 void __iomem *base;
154 unsigned long ret;
155 u32 t;
156
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
158
159 ret = 0;
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
163 } else {
164 struct clk *clk;
165
166 clk = clk_get(NULL, "ref");
167 if (!IS_ERR(clk))
168 ret = clk_get_rate(clk);
169 }
170
171 iounmap(base);
172
173 return ret;
174 }
175
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 {
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
180 unsigned int max_id;
181
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558 ||
187 ath79_soc == ATH79_SOC_QCA956X)
188 max_id = 1;
189 else
190 max_id = 0;
191
192 if (id > max_id) {
193 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
194 return;
195 }
196
197 switch (ath79_soc) {
198 case ATH79_SOC_AR7241:
199 case ATH79_SOC_AR9330:
200 case ATH79_SOC_AR9331:
201 case ATH79_SOC_QCA9533:
202 case ATH79_SOC_TP9343:
203 mdio_dev = &ath79_mdio1_device;
204 mdio_data = &ath79_mdio1_data;
205 break;
206
207 case ATH79_SOC_AR9341:
208 case ATH79_SOC_AR9342:
209 case ATH79_SOC_AR9344:
210 case ATH79_SOC_QCA9556:
211 case ATH79_SOC_QCA9558:
212 case ATH79_SOC_QCA956X:
213 if (id == 0) {
214 mdio_dev = &ath79_mdio0_device;
215 mdio_data = &ath79_mdio0_data;
216 } else {
217 mdio_dev = &ath79_mdio1_device;
218 mdio_data = &ath79_mdio1_data;
219 }
220 break;
221
222 case ATH79_SOC_AR7242:
223 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
224 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
225 AR71XX_ETH0_PLL_SHIFT);
226 /* fall through */
227 default:
228 mdio_dev = &ath79_mdio0_device;
229 mdio_data = &ath79_mdio0_data;
230 break;
231 }
232
233 mdio_data->phy_mask = phy_mask;
234
235 switch (ath79_soc) {
236 case ATH79_SOC_AR7240:
237 mdio_data->is_ar7240 = 1;
238 /* fall through */
239 case ATH79_SOC_AR7241:
240 mdio_data->builtin_switch = 1;
241 break;
242
243 case ATH79_SOC_AR9330:
244 mdio_data->is_ar9330 = 1;
245 /* fall through */
246 case ATH79_SOC_AR9331:
247 mdio_data->builtin_switch = 1;
248 break;
249
250 case ATH79_SOC_AR9341:
251 case ATH79_SOC_AR9342:
252 case ATH79_SOC_AR9344:
253 if (id == 1) {
254 mdio_data->builtin_switch = 1;
255 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
256 mdio_data->mdio_clock = 6250000;
257 }
258 mdio_data->is_ar934x = 1;
259 break;
260
261 case ATH79_SOC_QCA9533:
262 case ATH79_SOC_TP9343:
263 mdio_data->builtin_switch = 1;
264 break;
265
266 case ATH79_SOC_QCA9556:
267 case ATH79_SOC_QCA9558:
268 mdio_data->is_ar934x = 1;
269 break;
270
271 case ATH79_SOC_QCA956X:
272 if (id == 1)
273 mdio_data->builtin_switch = 1;
274 mdio_data->is_ar934x = 1;
275 break;
276
277 default:
278 break;
279 }
280
281 platform_device_register(mdio_dev);
282 }
283
284 struct ath79_eth_pll_data ath79_eth0_pll_data;
285 struct ath79_eth_pll_data ath79_eth1_pll_data;
286
287 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
288 {
289 struct ath79_eth_pll_data *pll_data;
290 u32 pll_val;
291
292 switch (mac) {
293 case 0:
294 pll_data = &ath79_eth0_pll_data;
295 break;
296 case 1:
297 pll_data = &ath79_eth1_pll_data;
298 break;
299 default:
300 BUG();
301 }
302
303 switch (speed) {
304 case SPEED_10:
305 pll_val = pll_data->pll_10;
306 break;
307 case SPEED_100:
308 pll_val = pll_data->pll_100;
309 break;
310 case SPEED_1000:
311 pll_val = pll_data->pll_1000;
312 break;
313 default:
314 BUG();
315 }
316
317 return pll_val;
318 }
319
320 static void ath79_set_speed_ge0(int speed)
321 {
322 u32 val = ath79_get_eth_pll(0, speed);
323
324 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
325 val, AR71XX_ETH0_PLL_SHIFT);
326 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
327 }
328
329 static void ath79_set_speed_ge1(int speed)
330 {
331 u32 val = ath79_get_eth_pll(1, speed);
332
333 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
334 val, AR71XX_ETH1_PLL_SHIFT);
335 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
336 }
337
338 static void ar7242_set_speed_ge0(int speed)
339 {
340 u32 val = ath79_get_eth_pll(0, speed);
341 void __iomem *base;
342
343 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
344 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
345 iounmap(base);
346 }
347
348 static void ar91xx_set_speed_ge0(int speed)
349 {
350 u32 val = ath79_get_eth_pll(0, speed);
351
352 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
353 val, AR913X_ETH0_PLL_SHIFT);
354 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
355 }
356
357 static void ar91xx_set_speed_ge1(int speed)
358 {
359 u32 val = ath79_get_eth_pll(1, speed);
360
361 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
362 val, AR913X_ETH1_PLL_SHIFT);
363 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
364 }
365
366 static void ar934x_set_speed_ge0(int speed)
367 {
368 void __iomem *base;
369 u32 val = ath79_get_eth_pll(0, speed);
370
371 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
372 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
373 iounmap(base);
374 }
375
376 static void qca955x_set_speed_xmii(int speed)
377 {
378 void __iomem *base;
379 u32 val = ath79_get_eth_pll(0, speed);
380
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
383 iounmap(base);
384 }
385
386 static void qca955x_set_speed_sgmii(int speed)
387 {
388 void __iomem *base;
389 u32 val = ath79_get_eth_pll(1, speed);
390
391 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
392 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
393 iounmap(base);
394 }
395
396 static void qca956x_set_speed_sgmii(int speed)
397 {
398 void __iomem *base;
399 u32 val = ath79_get_eth_pll(0, speed);
400
401 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
402 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
403 iounmap(base);
404 }
405
406 static void ath79_set_speed_dummy(int speed)
407 {
408 }
409
410 static void ath79_ddr_no_flush(void)
411 {
412 }
413
414 static void ath79_ddr_flush_ge0(void)
415 {
416 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
417 }
418
419 static void ath79_ddr_flush_ge1(void)
420 {
421 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
422 }
423
424 static void ar724x_ddr_flush_ge0(void)
425 {
426 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
427 }
428
429 static void ar724x_ddr_flush_ge1(void)
430 {
431 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
432 }
433
434 static void ar91xx_ddr_flush_ge0(void)
435 {
436 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
437 }
438
439 static void ar91xx_ddr_flush_ge1(void)
440 {
441 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
442 }
443
444 static void ar933x_ddr_flush_ge0(void)
445 {
446 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
447 }
448
449 static void ar933x_ddr_flush_ge1(void)
450 {
451 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
452 }
453
454 static struct resource ath79_eth0_resources[] = {
455 {
456 .name = "mac_base",
457 .flags = IORESOURCE_MEM,
458 .start = AR71XX_GE0_BASE,
459 .end = AR71XX_GE0_BASE + 0x200 - 1,
460 }, {
461 .name = "mac_irq",
462 .flags = IORESOURCE_IRQ,
463 .start = ATH79_CPU_IRQ(4),
464 .end = ATH79_CPU_IRQ(4),
465 },
466 };
467
468 struct ag71xx_platform_data ath79_eth0_data = {
469 .reset_bit = AR71XX_RESET_GE0_MAC,
470 };
471
472 struct platform_device ath79_eth0_device = {
473 .name = "ag71xx",
474 .id = 0,
475 .resource = ath79_eth0_resources,
476 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
477 .dev = {
478 .platform_data = &ath79_eth0_data,
479 },
480 };
481
482 static struct resource ath79_eth1_resources[] = {
483 {
484 .name = "mac_base",
485 .flags = IORESOURCE_MEM,
486 .start = AR71XX_GE1_BASE,
487 .end = AR71XX_GE1_BASE + 0x200 - 1,
488 }, {
489 .name = "mac_irq",
490 .flags = IORESOURCE_IRQ,
491 .start = ATH79_CPU_IRQ(5),
492 .end = ATH79_CPU_IRQ(5),
493 },
494 };
495
496 struct ag71xx_platform_data ath79_eth1_data = {
497 .reset_bit = AR71XX_RESET_GE1_MAC,
498 };
499
500 struct platform_device ath79_eth1_device = {
501 .name = "ag71xx",
502 .id = 1,
503 .resource = ath79_eth1_resources,
504 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
505 .dev = {
506 .platform_data = &ath79_eth1_data,
507 },
508 };
509
510 struct ag71xx_switch_platform_data ath79_switch_data;
511
512 #define AR71XX_PLL_VAL_1000 0x00110000
513 #define AR71XX_PLL_VAL_100 0x00001099
514 #define AR71XX_PLL_VAL_10 0x00991099
515
516 #define AR724X_PLL_VAL_1000 0x00110000
517 #define AR724X_PLL_VAL_100 0x00001099
518 #define AR724X_PLL_VAL_10 0x00991099
519
520 #define AR7242_PLL_VAL_1000 0x16000000
521 #define AR7242_PLL_VAL_100 0x00000101
522 #define AR7242_PLL_VAL_10 0x00001616
523
524 #define AR913X_PLL_VAL_1000 0x1a000000
525 #define AR913X_PLL_VAL_100 0x13000a44
526 #define AR913X_PLL_VAL_10 0x00441099
527
528 #define AR933X_PLL_VAL_1000 0x00110000
529 #define AR933X_PLL_VAL_100 0x00001099
530 #define AR933X_PLL_VAL_10 0x00991099
531
532 #define AR934X_PLL_VAL_1000 0x16000000
533 #define AR934X_PLL_VAL_100 0x00000101
534 #define AR934X_PLL_VAL_10 0x00001616
535
536 #define QCA956X_PLL_VAL_1000 0x03000000
537 #define QCA956X_PLL_VAL_100 0x00000101
538 #define QCA956X_PLL_VAL_10 0x00001919
539
540 static void __init ath79_init_eth_pll_data(unsigned int id)
541 {
542 struct ath79_eth_pll_data *pll_data;
543 u32 pll_10, pll_100, pll_1000;
544
545 switch (id) {
546 case 0:
547 pll_data = &ath79_eth0_pll_data;
548 break;
549 case 1:
550 pll_data = &ath79_eth1_pll_data;
551 break;
552 default:
553 BUG();
554 }
555
556 switch (ath79_soc) {
557 case ATH79_SOC_AR7130:
558 case ATH79_SOC_AR7141:
559 case ATH79_SOC_AR7161:
560 pll_10 = AR71XX_PLL_VAL_10;
561 pll_100 = AR71XX_PLL_VAL_100;
562 pll_1000 = AR71XX_PLL_VAL_1000;
563 break;
564
565 case ATH79_SOC_AR7240:
566 case ATH79_SOC_AR7241:
567 pll_10 = AR724X_PLL_VAL_10;
568 pll_100 = AR724X_PLL_VAL_100;
569 pll_1000 = AR724X_PLL_VAL_1000;
570 break;
571
572 case ATH79_SOC_AR7242:
573 pll_10 = AR7242_PLL_VAL_10;
574 pll_100 = AR7242_PLL_VAL_100;
575 pll_1000 = AR7242_PLL_VAL_1000;
576 break;
577
578 case ATH79_SOC_AR9130:
579 case ATH79_SOC_AR9132:
580 pll_10 = AR913X_PLL_VAL_10;
581 pll_100 = AR913X_PLL_VAL_100;
582 pll_1000 = AR913X_PLL_VAL_1000;
583 break;
584
585 case ATH79_SOC_AR9330:
586 case ATH79_SOC_AR9331:
587 pll_10 = AR933X_PLL_VAL_10;
588 pll_100 = AR933X_PLL_VAL_100;
589 pll_1000 = AR933X_PLL_VAL_1000;
590 break;
591
592 case ATH79_SOC_AR9341:
593 case ATH79_SOC_AR9342:
594 case ATH79_SOC_AR9344:
595 case ATH79_SOC_QCA9533:
596 case ATH79_SOC_QCA9556:
597 case ATH79_SOC_QCA9558:
598 case ATH79_SOC_TP9343:
599 pll_10 = AR934X_PLL_VAL_10;
600 pll_100 = AR934X_PLL_VAL_100;
601 pll_1000 = AR934X_PLL_VAL_1000;
602 break;
603
604 case ATH79_SOC_QCA956X:
605 pll_10 = QCA956X_PLL_VAL_10;
606 pll_100 = QCA956X_PLL_VAL_100;
607 pll_1000 = QCA956X_PLL_VAL_1000;
608 break;
609
610 default:
611 BUG();
612 }
613
614 if (!pll_data->pll_10)
615 pll_data->pll_10 = pll_10;
616
617 if (!pll_data->pll_100)
618 pll_data->pll_100 = pll_100;
619
620 if (!pll_data->pll_1000)
621 pll_data->pll_1000 = pll_1000;
622 }
623
624 static int __init ath79_setup_phy_if_mode(unsigned int id,
625 struct ag71xx_platform_data *pdata)
626 {
627 unsigned int mii_if;
628
629 switch (id) {
630 case 0:
631 switch (ath79_soc) {
632 case ATH79_SOC_AR7130:
633 case ATH79_SOC_AR7141:
634 case ATH79_SOC_AR7161:
635 case ATH79_SOC_AR9130:
636 case ATH79_SOC_AR9132:
637 switch (pdata->phy_if_mode) {
638 case PHY_INTERFACE_MODE_MII:
639 mii_if = AR71XX_MII0_CTRL_IF_MII;
640 break;
641 case PHY_INTERFACE_MODE_GMII:
642 mii_if = AR71XX_MII0_CTRL_IF_GMII;
643 break;
644 case PHY_INTERFACE_MODE_RGMII:
645 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
646 break;
647 case PHY_INTERFACE_MODE_RMII:
648 mii_if = AR71XX_MII0_CTRL_IF_RMII;
649 break;
650 default:
651 return -EINVAL;
652 }
653 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
654 break;
655
656 case ATH79_SOC_AR7240:
657 case ATH79_SOC_AR7241:
658 case ATH79_SOC_AR9330:
659 case ATH79_SOC_AR9331:
660 case ATH79_SOC_QCA9533:
661 case ATH79_SOC_TP9343:
662 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
663 break;
664
665 case ATH79_SOC_AR7242:
666 /* FIXME */
667
668 case ATH79_SOC_AR9341:
669 case ATH79_SOC_AR9342:
670 case ATH79_SOC_AR9344:
671 switch (pdata->phy_if_mode) {
672 case PHY_INTERFACE_MODE_MII:
673 case PHY_INTERFACE_MODE_GMII:
674 case PHY_INTERFACE_MODE_RGMII:
675 case PHY_INTERFACE_MODE_RMII:
676 break;
677 default:
678 return -EINVAL;
679 }
680 break;
681
682 case ATH79_SOC_QCA9556:
683 case ATH79_SOC_QCA9558:
684 case ATH79_SOC_QCA956X:
685 switch (pdata->phy_if_mode) {
686 case PHY_INTERFACE_MODE_MII:
687 case PHY_INTERFACE_MODE_RGMII:
688 case PHY_INTERFACE_MODE_SGMII:
689 break;
690 default:
691 return -EINVAL;
692 }
693 break;
694
695 default:
696 BUG();
697 }
698 break;
699 case 1:
700 switch (ath79_soc) {
701 case ATH79_SOC_AR7130:
702 case ATH79_SOC_AR7141:
703 case ATH79_SOC_AR7161:
704 case ATH79_SOC_AR9130:
705 case ATH79_SOC_AR9132:
706 switch (pdata->phy_if_mode) {
707 case PHY_INTERFACE_MODE_RMII:
708 mii_if = AR71XX_MII1_CTRL_IF_RMII;
709 break;
710 case PHY_INTERFACE_MODE_RGMII:
711 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
712 break;
713 default:
714 return -EINVAL;
715 }
716 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
717 break;
718
719 case ATH79_SOC_AR7240:
720 case ATH79_SOC_AR7241:
721 case ATH79_SOC_AR9330:
722 case ATH79_SOC_AR9331:
723 case ATH79_SOC_QCA956X:
724 case ATH79_SOC_TP9343:
725 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
726 break;
727
728 case ATH79_SOC_AR7242:
729 /* FIXME */
730
731 case ATH79_SOC_AR9341:
732 case ATH79_SOC_AR9342:
733 case ATH79_SOC_AR9344:
734 case ATH79_SOC_QCA9533:
735 switch (pdata->phy_if_mode) {
736 case PHY_INTERFACE_MODE_MII:
737 case PHY_INTERFACE_MODE_GMII:
738 break;
739 default:
740 return -EINVAL;
741 }
742 break;
743
744 case ATH79_SOC_QCA9556:
745 case ATH79_SOC_QCA9558:
746 switch (pdata->phy_if_mode) {
747 case PHY_INTERFACE_MODE_MII:
748 case PHY_INTERFACE_MODE_RGMII:
749 case PHY_INTERFACE_MODE_SGMII:
750 break;
751 default:
752 return -EINVAL;
753 }
754 break;
755
756 default:
757 BUG();
758 }
759 break;
760 }
761
762 return 0;
763 }
764
765 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
766 {
767 void __iomem *base;
768 u32 t;
769
770 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
771
772 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
773 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
774 if (mac)
775 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
776 if (mdio)
777 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
778 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
779
780 iounmap(base);
781 }
782
783 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
784 {
785 void __iomem *base;
786 u32 t;
787
788 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
789
790 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
791
792 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
793 AR934X_ETH_CFG_MII_GMAC0 |
794 AR934X_ETH_CFG_GMII_GMAC0 |
795 AR934X_ETH_CFG_SW_ONLY_MODE |
796 AR934X_ETH_CFG_SW_PHY_SWAP);
797
798 t |= mask;
799
800 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
801 /* flush write */
802 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
803
804 iounmap(base);
805 }
806
807 void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
808 unsigned int rxdv)
809 {
810 void __iomem *base;
811 u32 t;
812
813 rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
814 rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
815
816 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
817
818 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
819
820 t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
821 AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
822
823 t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
824 rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
825
826 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
827 /* flush write */
828 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
829
830 iounmap(base);
831 }
832
833 void __init ath79_setup_qca955x_eth_cfg(u32 mask,
834 unsigned int rxd, unsigned int rxdv,
835 unsigned int txd, unsigned int txe)
836 {
837 void __iomem *base;
838 u32 t, m;
839
840 m = QCA955X_ETH_CFG_RGMII_EN |
841 QCA955X_ETH_CFG_MII_GE0 |
842 QCA955X_ETH_CFG_GMII_GE0 |
843 QCA955X_ETH_CFG_MII_GE0_MASTER |
844 QCA955X_ETH_CFG_MII_GE0_SLAVE |
845 QCA955X_ETH_CFG_GE0_ERR_EN |
846 QCA955X_ETH_CFG_GE0_SGMII |
847 QCA955X_ETH_CFG_RMII_GE0 |
848 QCA955X_ETH_CFG_MII_CNTL_SPEED |
849 QCA955X_ETH_CFG_RMII_GE0_MASTER;
850 m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
851 m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
852 m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
853 m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
854
855 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
856
857 t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
858
859 t &= ~m;
860 t |= mask;
861 t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
862 t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
863 t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
864 t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
865
866 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
867
868 iounmap(base);
869 }
870
871 static int ath79_eth_instance __initdata;
872 void __init ath79_register_eth(unsigned int id)
873 {
874 struct platform_device *pdev;
875 struct ag71xx_platform_data *pdata;
876 int err;
877
878 if (id > 1) {
879 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
880 return;
881 }
882
883 ath79_init_eth_pll_data(id);
884
885 if (id == 0)
886 pdev = &ath79_eth0_device;
887 else
888 pdev = &ath79_eth1_device;
889
890 pdata = pdev->dev.platform_data;
891
892 pdata->max_frame_len = 1540;
893 pdata->desc_pktlen_mask = 0xfff;
894
895 err = ath79_setup_phy_if_mode(id, pdata);
896 if (err) {
897 printk(KERN_ERR
898 "ar71xx: invalid PHY interface mode for GE%u\n", id);
899 return;
900 }
901
902 switch (ath79_soc) {
903 case ATH79_SOC_AR7130:
904 if (id == 0) {
905 pdata->ddr_flush = ath79_ddr_flush_ge0;
906 pdata->set_speed = ath79_set_speed_ge0;
907 } else {
908 pdata->ddr_flush = ath79_ddr_flush_ge1;
909 pdata->set_speed = ath79_set_speed_ge1;
910 }
911 break;
912
913 case ATH79_SOC_AR7141:
914 case ATH79_SOC_AR7161:
915 if (id == 0) {
916 pdata->ddr_flush = ath79_ddr_flush_ge0;
917 pdata->set_speed = ath79_set_speed_ge0;
918 } else {
919 pdata->ddr_flush = ath79_ddr_flush_ge1;
920 pdata->set_speed = ath79_set_speed_ge1;
921 }
922 pdata->has_gbit = 1;
923 break;
924
925 case ATH79_SOC_AR7242:
926 if (id == 0) {
927 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
928 AR71XX_RESET_GE0_PHY;
929 pdata->ddr_flush = ar724x_ddr_flush_ge0;
930 pdata->set_speed = ar7242_set_speed_ge0;
931 } else {
932 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
933 AR71XX_RESET_GE1_PHY;
934 pdata->ddr_flush = ar724x_ddr_flush_ge1;
935 pdata->set_speed = ath79_set_speed_dummy;
936 }
937 pdata->has_gbit = 1;
938 pdata->is_ar724x = 1;
939
940 if (!pdata->fifo_cfg1)
941 pdata->fifo_cfg1 = 0x0010ffff;
942 if (!pdata->fifo_cfg2)
943 pdata->fifo_cfg2 = 0x015500aa;
944 if (!pdata->fifo_cfg3)
945 pdata->fifo_cfg3 = 0x01f00140;
946 break;
947
948 case ATH79_SOC_AR7241:
949 if (id == 0)
950 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
951 else
952 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
953 /* fall through */
954 case ATH79_SOC_AR7240:
955 if (id == 0) {
956 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
957 pdata->ddr_flush = ar724x_ddr_flush_ge0;
958 pdata->set_speed = ath79_set_speed_dummy;
959
960 pdata->phy_mask = BIT(4);
961 } else {
962 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
963 pdata->ddr_flush = ar724x_ddr_flush_ge1;
964 pdata->set_speed = ath79_set_speed_dummy;
965
966 pdata->speed = SPEED_1000;
967 pdata->duplex = DUPLEX_FULL;
968 pdata->switch_data = &ath79_switch_data;
969
970 ath79_switch_data.phy_poll_mask |= BIT(4);
971 }
972 pdata->has_gbit = 1;
973 pdata->is_ar724x = 1;
974 if (ath79_soc == ATH79_SOC_AR7240)
975 pdata->is_ar7240 = 1;
976
977 if (!pdata->fifo_cfg1)
978 pdata->fifo_cfg1 = 0x0010ffff;
979 if (!pdata->fifo_cfg2)
980 pdata->fifo_cfg2 = 0x015500aa;
981 if (!pdata->fifo_cfg3)
982 pdata->fifo_cfg3 = 0x01f00140;
983 break;
984
985 case ATH79_SOC_AR9130:
986 if (id == 0) {
987 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
988 pdata->set_speed = ar91xx_set_speed_ge0;
989 } else {
990 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
991 pdata->set_speed = ar91xx_set_speed_ge1;
992 }
993 pdata->is_ar91xx = 1;
994 break;
995
996 case ATH79_SOC_AR9132:
997 if (id == 0) {
998 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
999 pdata->set_speed = ar91xx_set_speed_ge0;
1000 } else {
1001 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
1002 pdata->set_speed = ar91xx_set_speed_ge1;
1003 }
1004 pdata->is_ar91xx = 1;
1005 pdata->has_gbit = 1;
1006 break;
1007
1008 case ATH79_SOC_AR9330:
1009 case ATH79_SOC_AR9331:
1010 if (id == 0) {
1011 pdata->reset_bit = AR933X_RESET_GE0_MAC |
1012 AR933X_RESET_GE0_MDIO;
1013 pdata->ddr_flush = ar933x_ddr_flush_ge0;
1014 pdata->set_speed = ath79_set_speed_dummy;
1015
1016 pdata->phy_mask = BIT(4);
1017 } else {
1018 pdata->reset_bit = AR933X_RESET_GE1_MAC |
1019 AR933X_RESET_GE1_MDIO;
1020 pdata->ddr_flush = ar933x_ddr_flush_ge1;
1021 pdata->set_speed = ath79_set_speed_dummy;
1022
1023 pdata->speed = SPEED_1000;
1024 pdata->has_gbit = 1;
1025 pdata->duplex = DUPLEX_FULL;
1026 pdata->switch_data = &ath79_switch_data;
1027
1028 ath79_switch_data.phy_poll_mask |= BIT(4);
1029 }
1030
1031 pdata->is_ar724x = 1;
1032
1033 if (!pdata->fifo_cfg1)
1034 pdata->fifo_cfg1 = 0x0010ffff;
1035 if (!pdata->fifo_cfg2)
1036 pdata->fifo_cfg2 = 0x015500aa;
1037 if (!pdata->fifo_cfg3)
1038 pdata->fifo_cfg3 = 0x01f00140;
1039 break;
1040
1041 case ATH79_SOC_AR9341:
1042 case ATH79_SOC_AR9342:
1043 case ATH79_SOC_AR9344:
1044 case ATH79_SOC_QCA9533:
1045 if (id == 0) {
1046 pdata->reset_bit = AR934X_RESET_GE0_MAC |
1047 AR934X_RESET_GE0_MDIO;
1048 pdata->set_speed = ar934x_set_speed_ge0;
1049 } else {
1050 pdata->reset_bit = AR934X_RESET_GE1_MAC |
1051 AR934X_RESET_GE1_MDIO;
1052 pdata->set_speed = ath79_set_speed_dummy;
1053
1054 pdata->switch_data = &ath79_switch_data;
1055
1056 /* reset the built-in switch */
1057 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1058 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1059 }
1060
1061 pdata->ddr_flush = ath79_ddr_no_flush;
1062 pdata->has_gbit = 1;
1063 pdata->is_ar724x = 1;
1064
1065 pdata->max_frame_len = SZ_16K - 1;
1066 pdata->desc_pktlen_mask = SZ_16K - 1;
1067
1068 if (!pdata->fifo_cfg1)
1069 pdata->fifo_cfg1 = 0x0010ffff;
1070 if (!pdata->fifo_cfg2)
1071 pdata->fifo_cfg2 = 0x015500aa;
1072 if (!pdata->fifo_cfg3)
1073 pdata->fifo_cfg3 = 0x01f00140;
1074 break;
1075
1076 case ATH79_SOC_TP9343:
1077 if (id == 0) {
1078 pdata->reset_bit = AR933X_RESET_GE0_MAC |
1079 AR933X_RESET_GE0_MDIO;
1080 pdata->set_speed = ath79_set_speed_dummy;
1081
1082 if (!pdata->phy_mask)
1083 pdata->phy_mask = BIT(4);
1084 } else {
1085 pdata->reset_bit = AR933X_RESET_GE1_MAC |
1086 AR933X_RESET_GE1_MDIO;
1087 pdata->set_speed = ath79_set_speed_dummy;
1088
1089 pdata->speed = SPEED_1000;
1090 pdata->duplex = DUPLEX_FULL;
1091 pdata->switch_data = &ath79_switch_data;
1092
1093 ath79_switch_data.phy_poll_mask |= BIT(4);
1094 }
1095
1096 pdata->ddr_flush = ath79_ddr_no_flush;
1097 pdata->has_gbit = 1;
1098 pdata->is_ar724x = 1;
1099
1100 if (!pdata->fifo_cfg1)
1101 pdata->fifo_cfg1 = 0x0010ffff;
1102 if (!pdata->fifo_cfg2)
1103 pdata->fifo_cfg2 = 0x015500aa;
1104 if (!pdata->fifo_cfg3)
1105 pdata->fifo_cfg3 = 0x01f00140;
1106 break;
1107
1108 case ATH79_SOC_QCA9556:
1109 case ATH79_SOC_QCA9558:
1110 if (id == 0) {
1111 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1112 QCA955X_RESET_GE0_MDIO;
1113 pdata->set_speed = qca955x_set_speed_xmii;
1114 } else {
1115 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1116 QCA955X_RESET_GE1_MDIO;
1117 pdata->set_speed = qca955x_set_speed_sgmii;
1118 }
1119
1120 pdata->ddr_flush = ath79_ddr_no_flush;
1121 pdata->has_gbit = 1;
1122 pdata->is_ar724x = 1;
1123
1124 /*
1125 * Limit the maximum frame length to 4095 bytes.
1126 * Although the documentation says that the hardware
1127 * limit is 16383 bytes but that does not work in
1128 * practice. It seems that the hardware only updates
1129 * the lowest 12 bits of the packet length field
1130 * in the RX descriptor.
1131 */
1132 pdata->max_frame_len = SZ_4K - 1;
1133 pdata->desc_pktlen_mask = SZ_16K - 1;
1134
1135 if (!pdata->fifo_cfg1)
1136 pdata->fifo_cfg1 = 0x0010ffff;
1137 if (!pdata->fifo_cfg2)
1138 pdata->fifo_cfg2 = 0x015500aa;
1139 if (!pdata->fifo_cfg3)
1140 pdata->fifo_cfg3 = 0x01f00140;
1141 break;
1142
1143 case ATH79_SOC_QCA956X:
1144 if (id == 0) {
1145 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1146 QCA955X_RESET_GE0_MDIO;
1147
1148 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1149 pdata->set_speed = qca956x_set_speed_sgmii;
1150 else
1151 pdata->set_speed = ath79_set_speed_ge0;
1152 } else {
1153 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1154 QCA955X_RESET_GE1_MDIO;
1155
1156 pdata->set_speed = ath79_set_speed_dummy;
1157
1158 pdata->switch_data = &ath79_switch_data;
1159
1160 pdata->speed = SPEED_1000;
1161 pdata->duplex = DUPLEX_FULL;
1162
1163 /* reset the built-in switch */
1164 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1165 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1166 }
1167
1168 pdata->ddr_flush = ath79_ddr_no_flush;
1169 pdata->has_gbit = 1;
1170 pdata->is_ar724x = 1;
1171
1172 if (!pdata->fifo_cfg1)
1173 pdata->fifo_cfg1 = 0x0010ffff;
1174 if (!pdata->fifo_cfg2)
1175 pdata->fifo_cfg2 = 0x015500aa;
1176 if (!pdata->fifo_cfg3)
1177 pdata->fifo_cfg3 = 0x01f00140;
1178 break;
1179
1180 default:
1181 BUG();
1182 }
1183
1184 switch (pdata->phy_if_mode) {
1185 case PHY_INTERFACE_MODE_GMII:
1186 case PHY_INTERFACE_MODE_RGMII:
1187 case PHY_INTERFACE_MODE_SGMII:
1188 if (!pdata->has_gbit) {
1189 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1190 id);
1191 return;
1192 }
1193 /* fallthrough */
1194 default:
1195 break;
1196 }
1197
1198 if (!is_valid_ether_addr(pdata->mac_addr)) {
1199 random_ether_addr(pdata->mac_addr);
1200 printk(KERN_DEBUG
1201 "ar71xx: using random MAC address for eth%d\n",
1202 ath79_eth_instance);
1203 }
1204
1205 if (pdata->mii_bus_dev == NULL) {
1206 switch (ath79_soc) {
1207 case ATH79_SOC_AR9341:
1208 case ATH79_SOC_AR9342:
1209 case ATH79_SOC_AR9344:
1210 if (id == 0)
1211 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1212 else
1213 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1214 break;
1215
1216 case ATH79_SOC_AR7241:
1217 case ATH79_SOC_AR9330:
1218 case ATH79_SOC_AR9331:
1219 case ATH79_SOC_QCA9533:
1220 case ATH79_SOC_TP9343:
1221 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1222 break;
1223
1224 case ATH79_SOC_QCA9556:
1225 case ATH79_SOC_QCA9558:
1226 /* don't assign any MDIO device by default */
1227 break;
1228
1229 case ATH79_SOC_QCA956X:
1230 if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII)
1231 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1232 break;
1233
1234 default:
1235 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1236 break;
1237 }
1238 }
1239
1240 /* Reset the device */
1241 ath79_device_reset_set(pdata->reset_bit);
1242 msleep(100);
1243
1244 ath79_device_reset_clear(pdata->reset_bit);
1245 msleep(100);
1246
1247 platform_device_register(pdev);
1248 ath79_eth_instance++;
1249 }
1250
1251 void __init ath79_set_mac_base(unsigned char *mac)
1252 {
1253 memcpy(ath79_mac_base, mac, ETH_ALEN);
1254 }
1255
1256 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1257 {
1258 int t;
1259
1260 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1261 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1262
1263 if (t != ETH_ALEN)
1264 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1265 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1266
1267 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1268 memset(mac, 0, ETH_ALEN);
1269 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1270 mac_str);
1271 }
1272 }
1273
1274 static void __init ath79_set_mac_base_ascii(char *str)
1275 {
1276 u8 mac[ETH_ALEN];
1277
1278 ath79_parse_ascii_mac(str, mac);
1279 ath79_set_mac_base(mac);
1280 }
1281
1282 static int __init ath79_ethaddr_setup(char *str)
1283 {
1284 ath79_set_mac_base_ascii(str);
1285 return 1;
1286 }
1287 __setup("ethaddr=", ath79_ethaddr_setup);
1288
1289 static int __init ath79_kmac_setup(char *str)
1290 {
1291 ath79_set_mac_base_ascii(str);
1292 return 1;
1293 }
1294 __setup("kmac=", ath79_kmac_setup);
1295
1296 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1297 int offset)
1298 {
1299 int t;
1300
1301 if (!dst)
1302 return;
1303
1304 if (!src || !is_valid_ether_addr(src)) {
1305 memset(dst, '\0', ETH_ALEN);
1306 return;
1307 }
1308
1309 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1310 t += offset;
1311
1312 dst[0] = src[0];
1313 dst[1] = src[1];
1314 dst[2] = src[2];
1315 dst[3] = (t >> 16) & 0xff;
1316 dst[4] = (t >> 8) & 0xff;
1317 dst[5] = t & 0xff;
1318 }
1319
1320 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1321 {
1322 int i;
1323
1324 if (!dst)
1325 return;
1326
1327 if (!src || !is_valid_ether_addr(src)) {
1328 memset(dst, '\0', ETH_ALEN);
1329 return;
1330 }
1331
1332 for (i = 0; i < ETH_ALEN; i++)
1333 dst[i] = src[i];
1334 dst[0] |= 0x02;
1335 }
OpenWrt Source Repository