target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c

   1 /*
   2  *  ALFA Network AP96 board support
   3  *
   4  *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/bitops.h>
  13 #include <linux/gpio.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/spi/mmc_spi.h>
  18
  19 #include <asm/mach-ath79/ath79.h>
  20 #include <asm/mach-ath79/ar71xx_regs.h>
  21
  22 #include "common.h"
  23 #include "dev-eth.h"
  24 #include "dev-gpio-buttons.h"
  25 #include "dev-spi.h"
  26 #include "dev-usb.h"
  27 #include "machtypes.h"
  28 #include "pci.h"
  29
  30 #define ALFA_AP96_GPIO_PCIE_RESET       2
  31 #define ALFA_AP96_GPIO_SIM_DETECT       3
  32 #define ALFA_AP96_GPIO_MICROSD_CD       4
  33 #define ALFA_AP96_GPIO_PCIE_W_DISABLE   5
  34
  35 #define ALFA_AP96_GPIO_BUTTON_RESET     11
  36
  37 #define ALFA_AP96_KEYS_POLL_INTERVAL            20      /* msecs */
  38 #define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL        (3 * ALFA_AP96_KEYS_POLL_INTERVAL)
  39
  40 static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = {
  41         {
  42                 .desc           = "Reset button",
  43                 .type           = EV_KEY,
  44                 .code           = KEY_RESTART,
  45                 .debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL,
  46                 .gpio           = ALFA_AP96_GPIO_BUTTON_RESET,
  47                 .active_low     = 1,
  48         }
  49 };
  50
  51 static struct mmc_spi_platform_data alfa_ap96_mmc_data = {
  52         .flags          = MMC_SPI_USE_CD_GPIO,
  53         .cd_gpio        = ALFA_AP96_GPIO_MICROSD_CD,
  54         .cd_debounce    = 1,
  55         .caps           = MMC_CAP_NEEDS_POLL,
  56         .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
  57 };
  58
  59 static struct spi_board_info alfa_ap96_spi_info[] = {
  60         {
  61                 .bus_num        = 0,
  62                 .chip_select    = 0,
  63                 .max_speed_hz   = 25000000,
  64                 .modalias       = "m25p80",
  65         }, {
  66                 .bus_num        = 0,
  67                 .chip_select    = 1,
  68                 .max_speed_hz   = 25000000,
  69                 .modalias       = "mmc_spi",
  70                 .platform_data  = &alfa_ap96_mmc_data,
  71         }, {
  72                 .bus_num        = 0,
  73                 .chip_select    = 2,
  74                 .max_speed_hz   = 6250000,
  75                 .modalias       = "rtc-pcf2123",
  76         },
  77 };
  78
  79 static struct ath79_spi_platform_data alfa_ap96_spi_data = {
  80         .bus_num                = 0,
  81         .num_chipselect         = 3,
  82 };
  83
  84 static void __init alfa_ap96_gpio_setup(void)
  85 {
  86         ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
  87                                    AR71XX_GPIO_FUNC_SPI_CS2_EN);
  88
  89         gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD");
  90         gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD);
  91         gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset");
  92         gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1);
  93         gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable");
  94         gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1);
  95 }
  96
  97 #define ALFA_AP96_WAN_PHYMASK   BIT(4)
  98 #define ALFA_AP96_LAN_PHYMASK   BIT(5)
  99 #define ALFA_AP96_MDIO_PHYMASK  (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK)
 100
 101 static void __init alfa_ap96_init(void)
 102 {
 103         alfa_ap96_gpio_setup();
 104
 105         ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK);
 106
 107         ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 108         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 109         ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK;
 110         ath79_eth1_pll_data.pll_1000 = 0x110000;
 111
 112         ath79_register_eth(0);
 113
 114         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
 115         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 116         ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK;
 117         ath79_eth1_pll_data.pll_1000 = 0x110000;
 118
 119         ath79_register_eth(1);
 120
 121         ath79_register_pci();
 122         ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info,
 123                            ARRAY_SIZE(alfa_ap96_spi_info));
 124
 125         ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL,
 126                                          ARRAY_SIZE(alfa_ap96_gpio_keys),
 127                                          alfa_ap96_gpio_keys);
 128         ath79_register_usb();
 129 }
 130
 131 MIPS_MACHINE(ATH79_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96",
 132              alfa_ap96_init);