ar71xx: Add support for the OMYlink OMY-X1
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-cap4200ag.c
1 /*
2 * Senao CAP4200AG board support
3 *
4 * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/phy.h>
13 #include <linux/platform_device.h>
14 #include <linux/ath9k_platform.h>
15
16 #include <asm/mach-ath79/ar71xx_regs.h>
17
18 #include "common.h"
19 #include "dev-ap9x-pci.h"
20 #include "dev-eth.h"
21 #include "dev-gpio-buttons.h"
22 #include "dev-leds-gpio.h"
23 #include "dev-m25p80.h"
24 #include "dev-spi.h"
25 #include "dev-usb.h"
26 #include "dev-wmac.h"
27 #include "machtypes.h"
28
29 #define CAP4200AG_GPIO_LED_PWR_GREEN 12
30 #define CAP4200AG_GPIO_LED_PWR_AMBER 13
31 #define CAP4200AG_GPIO_LED_LAN_GREEN 14
32 #define CAP4200AG_GPIO_LED_LAN_AMBER 15
33 #define CAP4200AG_GPIO_LED_WLAN_GREEN 18
34 #define CAP4200AG_GPIO_LED_WLAN_AMBER 19
35
36 #define CAP4200AG_GPIO_BTN_RESET 17
37
38 #define CAP4200AG_KEYS_POLL_INTERVAL 20 /* msecs */
39 #define CAP4200AG_KEYS_DEBOUNCE_INTERVAL (3 * CAP4200AG_KEYS_POLL_INTERVAL)
40
41 #define CAP4200AG_MAC_OFFSET 0
42 #define CAP4200AG_WMAC_CALDATA_OFFSET 0x1000
43 #define CAP4200AG_PCIE_CALDATA_OFFSET 0x5000
44
45 static struct gpio_led cap4200ag_leds_gpio[] __initdata = {
46 {
47 .name = "senao:green:pwr",
48 .gpio = CAP4200AG_GPIO_LED_PWR_GREEN,
49 .active_low = 1,
50 },
51 {
52 .name = "senao:amber:pwr",
53 .gpio = CAP4200AG_GPIO_LED_PWR_AMBER,
54 .active_low = 1,
55 },
56 {
57 .name = "senao:green:lan",
58 .gpio = CAP4200AG_GPIO_LED_LAN_GREEN,
59 .active_low = 1,
60 },
61 {
62 .name = "senao:amber:lan",
63 .gpio = CAP4200AG_GPIO_LED_LAN_AMBER,
64 .active_low = 1,
65 },
66 {
67 .name = "senao:green:wlan",
68 .gpio = CAP4200AG_GPIO_LED_WLAN_GREEN,
69 .active_low = 1,
70 },
71 {
72 .name = "senao:amber:wlan",
73 .gpio = CAP4200AG_GPIO_LED_WLAN_AMBER,
74 .active_low = 1,
75 },
76 };
77
78 static struct gpio_keys_button cap4200ag_gpio_keys[] __initdata = {
79 {
80 .desc = "Reset button",
81 .type = EV_KEY,
82 .code = KEY_RESTART,
83 .debounce_interval = CAP4200AG_KEYS_DEBOUNCE_INTERVAL,
84 .gpio = CAP4200AG_GPIO_BTN_RESET,
85 .active_low = 1,
86 },
87 };
88
89 static void __init cap4200ag_setup(void)
90 {
91 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
92 u8 mac[6];
93
94 ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_GREEN,
95 AR934X_GPIO_OUT_GPIO);
96 ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_AMBER,
97 AR934X_GPIO_OUT_GPIO);
98
99 ath79_register_m25p80(NULL);
100
101 ath79_register_leds_gpio(-1, ARRAY_SIZE(cap4200ag_leds_gpio),
102 cap4200ag_leds_gpio);
103 ath79_register_gpio_keys_polled(-1, CAP4200AG_KEYS_POLL_INTERVAL,
104 ARRAY_SIZE(cap4200ag_gpio_keys),
105 cap4200ag_gpio_keys);
106
107 ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -1);
108 ath79_wmac_disable_2ghz();
109 ath79_register_wmac(art + CAP4200AG_WMAC_CALDATA_OFFSET, mac);
110
111 ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -2);
112 ap91_pci_init(art + CAP4200AG_PCIE_CALDATA_OFFSET, mac);
113
114 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
115 AR934X_ETH_CFG_SW_ONLY_MODE);
116
117 ath79_register_mdio(0, 0x0);
118
119 ath79_init_mac(ath79_eth0_data.mac_addr,
120 art + CAP4200AG_MAC_OFFSET, -2);
121
122 /* GMAC0 is connected to an external PHY */
123 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
124 ath79_eth0_data.phy_mask = BIT(0);
125 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
126 ath79_eth0_pll_data.pll_1000 = 0x06000000;
127 ath79_register_eth(0);
128 }
129
130 MIPS_MACHINE(ATH79_MACH_CAP4200AG, "CAP4200AG", "Senao CAP4200AG",
131 cap4200ag_setup);