target/linux/ar71xx/files/arch/mips/ath79/mach-dgl-5500-a1.c

   1 /*
   2  *  D-Link DGL-5500 board support
   3  *
   4  *  Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/gpio.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/ar8216_platform.h>
  15
  16 #include <asm/mach-ath79/ar71xx_regs.h>
  17
  18 #include "common.h"
  19 #include "pci.h"
  20 #include "dev-gpio-buttons.h"
  21 #include "dev-eth.h"
  22 #include "dev-leds-gpio.h"
  23 #include "dev-m25p80.h"
  24 #include "dev-usb.h"
  25 #include "dev-wmac.h"
  26 #include "machtypes.h"
  27
  28 #define DGL_5500_A1_GPIO_LED_POWER_ORANGE       14
  29 #define DGL_5500_A1_GPIO_LED_POWER_GREEN        19
  30 #define DGL_5500_A1_GPIO_LED_PLANET_GREEN       22
  31 #define DGL_5500_A1_GPIO_LED_PLANET_ORANGE      23
  32
  33 #define DGL_5500_A1_GPIO_BTN_WPS                16
  34 #define DGL_5500_A1_GPIO_BTN_RESET              17
  35
  36 #define DGL_5500_A1_KEYS_POLL_INTERVAL          20      /* msecs */
  37 #define DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL      \
  38                                         (3 * DGL_5500_A1_KEYS_POLL_INTERVAL)
  39
  40 #define DGL_5500_A1_WMAC_CALDATA_OFFSET         0x1000
  41
  42 #define DGL_5500_A1_LAN_MAC_OFFSET      0x04
  43 #define DGL_5500_A1_WAN_MAC_OFFSET      0x16
  44
  45 static struct gpio_led dgl_5500_a1_leds_gpio[] __initdata = {
  46         {
  47                 .name           = "d-link:green:power",
  48                 .gpio           = DGL_5500_A1_GPIO_LED_POWER_GREEN,
  49                 .active_low     = 1,
  50         },
  51         {
  52                 .name           = "d-link:orange:power",
  53                 .gpio           = DGL_5500_A1_GPIO_LED_POWER_ORANGE,
  54                 .active_low     = 1,
  55         },
  56         {
  57                 .name           = "d-link:green:planet",
  58                 .gpio           = DGL_5500_A1_GPIO_LED_PLANET_GREEN,
  59                 .active_low     = 1,
  60         },
  61         {
  62                 .name           = "d-link:orange:planet",
  63                 .gpio           = DGL_5500_A1_GPIO_LED_PLANET_ORANGE,
  64                 .active_low     = 1,
  65         },
  66 };
  67
  68 static struct gpio_keys_button dgl_5500_a1_gpio_keys[] __initdata = {
  69         {
  70                 .desc           = "Reset button",
  71                 .type           = EV_KEY,
  72                 .code           = KEY_RESTART,
  73                 .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL,
  74                 .gpio           = DGL_5500_A1_GPIO_BTN_RESET,
  75                 .active_low     = 1,
  76         },
  77         {
  78                 .desc           = "WPS button",
  79                 .type           = EV_KEY,
  80                 .code           = KEY_WPS_BUTTON,
  81                 .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL,
  82                 .gpio           = DGL_5500_A1_GPIO_BTN_WPS,
  83                 .active_low     = 1,
  84         },
  85 };
  86
  87 static struct ar8327_pad_cfg dgl_5500_a1_ar8327_pad0_cfg = {
  88         /* Use the SGMII interface for the GMAC0 of the AR8327 switch */
  89         .mode = AR8327_PAD_MAC_SGMII,
  90         .sgmii_delay_en = true,
  91 };
  92
  93 static struct ar8327_platform_data dgl_5500_a1_ar8327_data = {
  94         .pad0_cfg = &dgl_5500_a1_ar8327_pad0_cfg,
  95         .port0_cfg = {
  96                 .force_link = 1,
  97                 .speed = AR8327_PORT_SPEED_1000,
  98                 .duplex = 1,
  99                 .txpause = 1,
 100                 .rxpause = 1,
 101         },
 102 };
 103
 104 static struct mdio_board_info dgl_5500_a1_mdio0_info[] = {
 105         {
 106                 .bus_id = "ag71xx-mdio.0",
 107                 .phy_addr = 0,
 108                 .platform_data = &dgl_5500_a1_ar8327_data,
 109         },
 110 };
 111
 112 static void __init dgl_5500_a1_setup(void)
 113 {
 114         u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
 115         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 116         u8 lan_mac[ETH_ALEN];
 117
 118         ath79_parse_ascii_mac(mac + DGL_5500_A1_LAN_MAC_OFFSET, lan_mac);
 119
 120         ath79_register_m25p80(NULL);
 121
 122         ath79_register_leds_gpio(-1, ARRAY_SIZE(dgl_5500_a1_leds_gpio),
 123                                  dgl_5500_a1_leds_gpio);
 124         ath79_register_gpio_keys_polled(-1, DGL_5500_A1_KEYS_POLL_INTERVAL,
 125                                         ARRAY_SIZE(dgl_5500_a1_gpio_keys),
 126                                         dgl_5500_a1_gpio_keys);
 127
 128         ath79_register_wmac(art + DGL_5500_A1_WMAC_CALDATA_OFFSET, lan_mac);
 129
 130         ath79_register_mdio(0, 0x0);
 131         mdiobus_register_board_info(dgl_5500_a1_mdio0_info,
 132                                     ARRAY_SIZE(dgl_5500_a1_mdio0_info));
 133
 134         ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
 135
 136         /* GMAC1 is connected to an AR8327N switch via the SMGII interface */
 137         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 138         ath79_eth1_data.phy_mask = BIT(0);
 139         ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev;
 140
 141         ath79_eth1_pll_data.pll_1000 = 0x03000101;
 142
 143         ath79_register_eth(1);
 144
 145         ath79_register_usb();
 146         ath79_register_pci();
 147 }
 148
 149 MIPS_MACHINE(ATH79_MACH_DGL_5500_A1, "DGL-5500-A1", "D-Link DGL-5500 rev. A1",
 150              dgl_5500_a1_setup);