ar71xx: add v4.14 support
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-domywifi-dw33d.c
1 /*
2 * DomyWifi DW33D support
3 *
4 * Copyright (c) 2012 Qualcomm Atheros
5 * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include <linux/platform_device.h>
22 #include <linux/ar8216_platform.h>
23 #include <linux/mtd/mtd.h>
24 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
25 #include <linux/mtd/nand.h>
26 #else
27 #include <linux/mtd/rawnand.h>
28 #endif
29 #include <linux/platform/ar934x_nfc.h>
30
31 #include <asm/mach-ath79/ar71xx_regs.h>
32
33 #include "common.h"
34 #include "pci.h"
35 #include "dev-ap9x-pci.h"
36 #include "dev-gpio-buttons.h"
37 #include "dev-eth.h"
38 #include "dev-leds-gpio.h"
39 #include "dev-m25p80.h"
40 #include "dev-nfc.h"
41 #include "dev-usb.h"
42 #include "dev-wmac.h"
43 #include "machtypes.h"
44
45 #define DW33D_GPIO_LED_MMC 4
46 #define DW33D_GPIO_LED_WLAN_2G 13
47 #define DW33D_GPIO_LED_STATUS 14
48 #define DW33D_GPIO_LED_USB 15
49 #define DW33D_GPIO_LED_INTERNET 22
50
51 #define DW33D_GPIO_BTN_RESET 17
52
53 #define DW33D_KEYS_POLL_INTERVAL 20 /* msecs */
54 #define DW33D_KEYS_DEBOUNCE_INTERVAL (3 * DW33D_KEYS_POLL_INTERVAL)
55
56 #define DW33D_MAC0_OFFSET 0
57 #define DW33D_MAC1_OFFSET 6
58 #define DW33D_WMAC_OFFSET 12
59 #define DW33D_WMAC_CALDATA_OFFSET 0x1000
60 #define DW33D_PCIE_CALDATA_OFFSET 0x5000
61
62 static struct gpio_led dw33d_leds_gpio[] __initdata = {
63 {
64 .name = "dw33d:blue:status",
65 .gpio = DW33D_GPIO_LED_STATUS,
66 .active_low = 1,
67 },
68 {
69 .name = "dw33d:blue:mmc",
70 .gpio = DW33D_GPIO_LED_MMC,
71 .active_low = 1,
72 },
73 {
74 .name = "dw33d:blue:usb",
75 .gpio = DW33D_GPIO_LED_USB,
76 .active_low = 1,
77 },
78 {
79 .name = "dw33d:blue:wlan-2g",
80 .gpio = DW33D_GPIO_LED_WLAN_2G,
81 .active_low = 1,
82 },
83 {
84 .name = "dw33d:blue:internet",
85 .gpio = DW33D_GPIO_LED_INTERNET,
86 .active_low = 1,
87 }
88 };
89
90 static struct gpio_keys_button dw33d_gpio_keys[] __initdata = {
91 {
92 .desc = "Reset button",
93 .type = EV_KEY,
94 .code = KEY_RESTART,
95 .debounce_interval = DW33D_KEYS_DEBOUNCE_INTERVAL,
96 .gpio = DW33D_GPIO_BTN_RESET,
97 .active_low = 1,
98 }
99 };
100
101 /* GMAC6 of the QCA8337 switch is connected to the QCA9558 SoC via SGMII */
102 static struct ar8327_pad_cfg dw33d_qca8337_pad6_cfg = {
103 .mode = AR8327_PAD_MAC_SGMII,
104 .sgmii_delay_en = true,
105 };
106
107 /* GMAC0 of the QCA8337 switch is connected to the QCA9558 SoC via RGMII */
108 static struct ar8327_pad_cfg dw33d_qca8337_pad0_cfg = {
109 .mode = AR8327_PAD_MAC_RGMII,
110 .txclk_delay_en = true,
111 .rxclk_delay_en = true,
112 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
113 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
114 };
115
116 static struct ar8327_platform_data dw33d_qca8337_data = {
117 .pad0_cfg = &dw33d_qca8337_pad0_cfg,
118 .pad6_cfg = &dw33d_qca8337_pad6_cfg,
119 .port0_cfg = {
120 .force_link = 1,
121 .speed = AR8327_PORT_SPEED_1000,
122 .duplex = 1,
123 .txpause = 1,
124 .rxpause = 1,
125 },
126 .port6_cfg = {
127 .force_link = 1,
128 .speed = AR8327_PORT_SPEED_1000,
129 .duplex = 1,
130 .txpause = 1,
131 .rxpause = 1,
132 },
133 };
134
135 static struct mdio_board_info dw33d_mdio0_info[] = {
136 {
137 .bus_id = "ag71xx-mdio.0",
138 .mdio_addr = 0,
139 .platform_data = &dw33d_qca8337_data,
140 },
141 };
142
143 static void __init dw33d_setup(void)
144 {
145 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
146
147 ath79_register_m25p80(NULL);
148
149 ath79_register_leds_gpio(-1, ARRAY_SIZE(dw33d_leds_gpio),
150 dw33d_leds_gpio);
151 ath79_register_gpio_keys_polled(-1, DW33D_KEYS_POLL_INTERVAL,
152 ARRAY_SIZE(dw33d_gpio_keys),
153 dw33d_gpio_keys);
154
155 ath79_register_usb();
156 ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
157 ath79_register_nfc();
158 ath79_register_pci();
159
160 ath79_register_wmac(art + DW33D_WMAC_CALDATA_OFFSET, art + DW33D_WMAC_OFFSET);
161
162 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
163
164 ath79_register_mdio(0, 0x0);
165
166 ath79_init_mac(ath79_eth0_data.mac_addr, art + DW33D_MAC0_OFFSET, 0);
167 ath79_init_mac(ath79_eth1_data.mac_addr, art + DW33D_MAC1_OFFSET, 0);
168
169 mdiobus_register_board_info(dw33d_mdio0_info,
170 ARRAY_SIZE(dw33d_mdio0_info));
171
172 /* GMAC0 is connected to the RMGII interface */
173 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
174 ath79_eth0_data.phy_mask = BIT(0);
175 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
176 ath79_eth0_pll_data.pll_1000 = 0x56000000;
177
178 ath79_register_eth(0);
179
180 /* GMAC1 is connected tot eh SGMII interface */
181 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
182 ath79_eth1_data.speed = SPEED_1000;
183 ath79_eth1_data.duplex = DUPLEX_FULL;
184 ath79_eth1_pll_data.pll_1000 = 0x03000101;
185
186 ath79_register_eth(1);
187 }
188
189 MIPS_MACHINE(ATH79_MACH_DOMYWIFI_DW33D, "DW33D",
190 "DomyWifi DW33D",
191 dw33d_setup);