target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c

   1 /*
   2  * Wallys DR342/DR344 boards support
   3  *
   4  * Copyright (c) 2011 Qualcomm Atheros
   5  * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  * Copyright (c) 2015 Philippe Duchein <wireless-dev@duchein.net>
   7  * Copyright (c) 2017 Piotr Dymacz <pepe2k@gmail.com>
   8  *
   9  * Permission to use, copy, modify, and/or distribute this software for any
  10  * purpose with or without fee is hereby granted, provided that the above
  11  * copyright notice and this permission notice appear in all copies.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20  *
  21  */
  22
  23 #include <linux/gpio.h>
  24 #include <linux/phy.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/ath9k_platform.h>
  27 #include <linux/platform_data/phy-at803x.h>
  28
  29 #include <asm/mach-ath79/ar71xx_regs.h>
  30
  31 #include "common.h"
  32 #include "pci.h"
  33 #include "dev-ap9x-pci.h"
  34 #include "dev-gpio-buttons.h"
  35 #include "dev-eth.h"
  36 #include "dev-usb.h"
  37 #include "dev-leds-gpio.h"
  38 #include "dev-m25p80.h"
  39 #include "dev-spi.h"
  40 #include "dev-wmac.h"
  41 #include "machtypes.h"
  42
  43 #define DR34X_GPIO_LED_SIG1             12
  44 #define DR34X_GPIO_LED_SIG2             13
  45 #define DR34X_GPIO_LED_SIG3             14
  46 #define DR34X_GPIO_LED_SIG4             15
  47 #define DR34X_GPIO_LED_STATUS           11
  48 #define DR344_GPIO_LED_LAN              17
  49 #define DR344_GPIO_EXTERNAL_LNA0        18
  50 #define DR344_GPIO_EXTERNAL_LNA1        19
  51
  52 #define DR34X_GPIO_BTN_RESET            16
  53
  54 #define DR344_KEYS_POLL_INTERVAL        20      /* msecs */
  55 #define DR344_KEYS_DEBOUNCE_INTERVAL    (3 * DR344_KEYS_POLL_INTERVAL)
  56
  57 #define DR34X_MAC0_OFFSET               0
  58 #define DR34X_MAC1_OFFSET               8
  59 #define DR34X_WMAC_CALDATA_OFFSET       0x1000
  60
  61 static struct gpio_led dr342_leds_gpio[] __initdata = {
  62         {
  63                 .name           = "dr342:green:status",
  64                 .gpio           = DR34X_GPIO_LED_STATUS,
  65                 .active_low     = 1,
  66         },
  67         {
  68                 .name           = "dr342:green:sig1",
  69                 .gpio           = DR34X_GPIO_LED_SIG1,
  70                 .active_low     = 1,
  71         },
  72         {
  73                 .name           = "dr342:green:sig2",
  74                 .gpio           = DR34X_GPIO_LED_SIG2,
  75                 .active_low     = 1,
  76         },
  77         {
  78                 .name           = "dr342:green:sig3",
  79                 .gpio           = DR34X_GPIO_LED_SIG3,
  80                 .active_low     = 1,
  81         },
  82         {
  83                 .name           = "dr342:green:sig4",
  84                 .gpio           = DR34X_GPIO_LED_SIG4,
  85                 .active_low     = 1,
  86         }
  87 };
  88
  89 static struct gpio_led dr344_leds_gpio[] __initdata = {
  90         {
  91                 .name           = "dr344:green:lan",
  92                 .gpio           = DR344_GPIO_LED_LAN,
  93                 .active_low     = 1,
  94         },
  95         {
  96                 .name           = "dr344:green:status",
  97                 .gpio           = DR34X_GPIO_LED_STATUS,
  98                 .active_low     = 1,
  99         },
 100         {
 101                 .name           = "dr344:green:sig1",
 102                 .gpio           = DR34X_GPIO_LED_SIG1,
 103                 .active_low     = 1,
 104         },
 105         {
 106                 .name           = "dr344:green:sig2",
 107                 .gpio           = DR34X_GPIO_LED_SIG2,
 108                 .active_low     = 1,
 109         },
 110         {
 111                 .name           = "dr344:green:sig3",
 112                 .gpio           = DR34X_GPIO_LED_SIG3,
 113                 .active_low     = 1,
 114         },
 115         {
 116                 .name           = "dr344:green:sig4",
 117                 .gpio           = DR34X_GPIO_LED_SIG4,
 118                 .active_low     = 1,
 119         }
 120 };
 121
 122 static struct gpio_keys_button dr34x_gpio_keys[] __initdata = {
 123         {
 124                 .desc           = "reset",
 125                 .type           = EV_KEY,
 126                 .code           = KEY_RESTART,
 127                 .debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL,
 128                 .gpio           = DR34X_GPIO_BTN_RESET,
 129                 .active_low     = 1,
 130         },
 131 };
 132
 133 static struct at803x_platform_data dr34x_at803x_data = {
 134         .disable_smarteee = 1,
 135         .enable_rgmii_rx_delay = 1,
 136         .enable_rgmii_tx_delay = 1,
 137 };
 138
 139 static struct mdio_board_info dr34x_mdio0_info[] = {
 140         {
 141                 .bus_id = "ag71xx-mdio.0",
 142                 .phy_addr = 0,
 143                 .platform_data = &dr34x_at803x_data,
 144         },
 145 };
 146
 147 static void __init dr34x_setup(void)
 148 {
 149         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 150         u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
 151
 152         ath79_register_m25p80(NULL);
 153
 154         ath79_gpio_direction_select(DR34X_GPIO_LED_STATUS, true);
 155         gpio_set_value(DR34X_GPIO_LED_STATUS, 1);
 156         ath79_gpio_output_select(DR34X_GPIO_LED_STATUS, 0);
 157
 158         ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
 159                                         ARRAY_SIZE(dr34x_gpio_keys),
 160                                         dr34x_gpio_keys);
 161
 162         ath79_register_usb();
 163
 164         ath79_register_wmac(art + DR34X_WMAC_CALDATA_OFFSET, NULL);
 165
 166         ath79_register_pci();
 167
 168         mdiobus_register_board_info(dr34x_mdio0_info,
 169                                     ARRAY_SIZE(dr34x_mdio0_info));
 170
 171         ath79_register_mdio(0, 0x0);
 172
 173         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
 174                                    AR934X_ETH_CFG_SW_ONLY_MODE);
 175
 176         /* GMAC0 is connected to an AR8035 Gbps PHY */
 177         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 178         ath79_eth0_data.phy_mask = BIT(0);
 179         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 180         ath79_eth0_pll_data.pll_1000 = 0x02000000;
 181         ath79_eth0_pll_data.pll_100 = 0x0101;
 182         ath79_eth0_pll_data.pll_10 = 0x1313;
 183
 184         ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR34X_MAC0_OFFSET, 0);
 185         ath79_register_eth(0);
 186 }
 187
 188 static void __init dr342_setup(void)
 189 {
 190         dr34x_setup();
 191
 192         ath79_register_leds_gpio(-1, ARRAY_SIZE(dr342_leds_gpio),
 193                                  dr342_leds_gpio);
 194 }
 195
 196 static void __init dr344_setup(void)
 197 {
 198         u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
 199
 200         dr34x_setup();
 201
 202         ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
 203         gpio_set_value(DR344_GPIO_LED_LAN, 1);
 204         ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
 205
 206         ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
 207                                  dr344_leds_gpio);
 208
 209         ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
 210         ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
 211
 212         ath79_register_mdio(1, 0x0);
 213
 214         /* GMAC1 is connected to the internal switch */
 215         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 216         ath79_eth1_data.speed = SPEED_1000;
 217         ath79_eth1_data.duplex = DUPLEX_FULL;
 218
 219         ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR34X_MAC1_OFFSET, 0);
 220         ath79_register_eth(1);
 221 }
 222
 223 MIPS_MACHINE(ATH79_MACH_DR342, "DR342", "Wallys DR342", dr342_setup);
 224 MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup);