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ar71xx: add definitions for RouterBOARD hardware option bits
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP 2nD
5 * - MikroTik RouterBOARD mAP L-2nD
6 * - MikroTik RouterBOARD 941L-2nD
7 * - MikroTik RouterBOARD 951Ui-2nD
8 * - MikroTik RouterBOARD 952Ui-5ac2nD
9 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
10 * - MikroTik RouterBOARD 750UP r2
11 * - MikroTik RouterBOARD 750P-PBr2
12 * - MikroTik RouterBOARD 750 r2
13 * - MikroTik RouterBOARD LHG 5nD
14 * - MikroTik RouterBOARD wAP2nD
15 * - MikroTik RouterBOARD wAP G-5HacT2HnDwAP (wAP AC)
16 *
17 * Preliminary support for the following hardware
18 * - MikroTik RouterBOARD cAP2nD
19 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
20 * hardware as the mAP L-2nD. It is unknown if they share the same board
21 * identifier.
22 *
23 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
24 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
25 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License version 2 as published
29 * by the Free Software Foundation.
30 */
31
32 #include <linux/pci.h>
33 #include <linux/platform_device.h>
34 #include <linux/phy.h>
35 #include <linux/routerboot.h>
36 #include <linux/gpio.h>
37
38 #include <linux/spi/spi.h>
39 #include <linux/spi/74x164.h>
40
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/partitions.h>
43
44 #include <linux/ar8216_platform.h>
45 #include <linux/platform_data/phy-at803x.h>
46 #include <linux/platform_data/mdio-gpio.h>
47
48 #include <asm/prom.h>
49 #include <asm/mach-ath79/ar71xx_regs.h>
50 #include <asm/mach-ath79/ath79.h>
51
52 #include "common.h"
53 #include "dev-eth.h"
54 #include "dev-spi.h"
55 #include "dev-gpio-buttons.h"
56 #include "dev-leds-gpio.h"
57 #include "dev-m25p80.h"
58 #include "dev-usb.h"
59 #include "dev-wmac.h"
60 #include "machtypes.h"
61 #include "pci.h"
62 #include "routerboot.h"
63
64 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
65 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
66
67 #define RBSPI_HAS_USB BIT(0)
68 #define RBSPI_HAS_WLAN0 BIT(1)
69 #define RBSPI_HAS_WLAN1 BIT(2)
70 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
71 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
72 #define RBSPI_HAS_POE BIT(5)
73 #define RBSPI_HAS_MDIO1 BIT(6)
74 #define RBSPI_HAS_PCI BIT(7)
75
76 #define RB_ROUTERBOOT_OFFSET 0x0000
77 #define RB_BIOS_SIZE 0x1000
78 #define RB_SOFT_CFG_SIZE 0x1000
79
80 /* Flash partitions indexes */
81 enum {
82 RBSPI_PART_RBOOT,
83 RBSPI_PART_HCONF,
84 RBSPI_PART_BIOS,
85 RBSPI_PART_RBOOT2,
86 RBSPI_PART_SCONF,
87 RBSPI_PART_FIRMW,
88 RBSPI_PARTS
89 };
90
91 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
92
93 /*
94 * Setup the SPI flash partition table based on initial parsing.
95 * The kernel can be at any aligned position and have any size.
96 */
97 static void __init rbspi_init_partitions(const struct rb_info *info)
98 {
99 struct mtd_partition *parts = rbspi_spi_partitions;
100 memset(parts, 0x0, sizeof(*parts));
101
102 parts[RBSPI_PART_RBOOT].name = "routerboot";
103 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
104 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
105 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
106
107 parts[RBSPI_PART_HCONF].name = "hard_config";
108 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
109 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
110 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
111
112 parts[RBSPI_PART_BIOS].name = "bios";
113 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
114 + info->hard_cfg_size;
115 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
116 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
117
118 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
119 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
120 + RB_BIOS_SIZE;
121 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
122 - parts[RBSPI_PART_RBOOT2].offset;
123 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
124
125 parts[RBSPI_PART_SCONF].name = "soft_config";
126 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
127 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
128
129 parts[RBSPI_PART_FIRMW].name = "firmware";
130 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
131 + parts[RBSPI_PART_SCONF].size;
132 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
133 }
134
135 static struct flash_platform_data rbspi_spi_flash_data = {
136 .parts = rbspi_spi_partitions,
137 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
138 };
139
140 /*
141 * Several boards only have a single reset button, use a common
142 * structure for that.
143 */
144 static struct gpio_keys_button rbspi_gpio_keys_reset[] __initdata = {
145 {
146 .desc = "Reset button",
147 .type = EV_KEY,
148 .code = KEY_RESTART,
149 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
150 .gpio = -ENOENT, /* filled dynamically */
151 .active_low = 1,
152 },
153 };
154
155 /* RB mAP L-2nD gpios */
156 #define RBMAPL_GPIO_LED_POWER 17
157 #define RBMAPL_GPIO_LED_USER 14
158 #define RBMAPL_GPIO_LED_ETH 4
159 #define RBMAPL_GPIO_LED_WLAN 11
160 #define RBMAPL_GPIO_BTN_RESET 16
161
162 static struct gpio_led rbmapl_leds[] __initdata = {
163 {
164 .name = "rb:green:power",
165 .gpio = RBMAPL_GPIO_LED_POWER,
166 .active_low = 0,
167 .default_state = LEDS_GPIO_DEFSTATE_ON,
168 }, {
169 .name = "rb:green:user",
170 .gpio = RBMAPL_GPIO_LED_USER,
171 .active_low = 0,
172 }, {
173 .name = "rb:green:eth",
174 .gpio = RBMAPL_GPIO_LED_ETH,
175 .active_low = 0,
176 }, {
177 .name = "rb:green:wlan",
178 .gpio = RBMAPL_GPIO_LED_WLAN,
179 .active_low = 0,
180 },
181 };
182
183 /* RB 941L-2nD gpios */
184 #define RBHAPL_GPIO_LED_USER 14
185 #define RBHAPL_GPIO_BTN_RESET 16
186
187 static struct gpio_led rbhapl_leds[] __initdata = {
188 {
189 .name = "rb:green:user",
190 .gpio = RBHAPL_GPIO_LED_USER,
191 .active_low = 1,
192 },
193 };
194
195 /* common RB SSRs */
196 #define RBSPI_SSR_GPIO_BASE 40
197 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
198
199 /* RB 951Ui-2nD gpios */
200 #define RB952_SSR_BIT_LED_LAN1 0
201 #define RB952_SSR_BIT_LED_LAN2 1
202 #define RB952_SSR_BIT_LED_LAN3 2
203 #define RB952_SSR_BIT_LED_LAN4 3
204 #define RB952_SSR_BIT_LED_LAN5 4
205 #define RB952_SSR_BIT_USB_POWER 5
206 #define RB952_SSR_BIT_LED_WLAN 6
207 #define RB952_GPIO_SSR_CS 11
208 #define RB952_GPIO_LED_USER 4
209 #define RB952_GPIO_POE_POWER 14
210 #define RB952_GPIO_POE_STATUS 12
211 #define RB952_GPIO_BTN_RESET 16
212 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
213 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
214 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
215 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
216 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
217 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
218 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
219
220 static struct gpio_led rb952_leds[] __initdata = {
221 {
222 .name = "rb:green:user",
223 .gpio = RB952_GPIO_LED_USER,
224 .active_low = 0,
225 }, {
226 .name = "rb:blue:wlan",
227 .gpio = RB952_GPIO_LED_WLAN,
228 .active_low = 1,
229 }, {
230 .name = "rb:green:port1",
231 .gpio = RB952_GPIO_LED_LAN1,
232 .active_low = 1,
233 }, {
234 .name = "rb:green:port2",
235 .gpio = RB952_GPIO_LED_LAN2,
236 .active_low = 1,
237 }, {
238 .name = "rb:green:port3",
239 .gpio = RB952_GPIO_LED_LAN3,
240 .active_low = 1,
241 }, {
242 .name = "rb:green:port4",
243 .gpio = RB952_GPIO_LED_LAN4,
244 .active_low = 1,
245 }, {
246 .name = "rb:green:port5",
247 .gpio = RB952_GPIO_LED_LAN5,
248 .active_low = 1,
249 },
250 };
251
252
253 /* RB 962UiGS-5HacT2HnT gpios */
254 #define RB962_GPIO_POE_STATUS 2
255 #define RB962_GPIO_POE_POWER 3
256 #define RB962_GPIO_LED_USER 12
257 #define RB962_GPIO_USB_POWER 13
258 #define RB962_GPIO_BTN_RESET 20
259
260 static struct gpio_led rb962_leds_gpio[] __initdata = {
261 {
262 .name = "rb:green:user",
263 .gpio = RB962_GPIO_LED_USER,
264 .active_low = 1,
265 },
266 };
267
268 static const struct ar8327_led_info rb962_leds_ar8327[] = {
269 AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"),
270 AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"),
271 AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"),
272 AR8327_LED_INFO(PHY3_0, HW, "rb:green:port4"),
273 AR8327_LED_INFO(PHY4_0, HW, "rb:green:port5"),
274 };
275
276 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg = {
277 .mode = AR8327_PAD_MAC_RGMII,
278 .txclk_delay_en = true,
279 .rxclk_delay_en = true,
280 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
281 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
282 .mac06_exchange_dis = true,
283 };
284
285 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg = {
286 /* Use SGMII interface for GMAC6 of the AR8337 switch */
287 .mode = AR8327_PAD_MAC_SGMII,
288 .rxclk_delay_en = true,
289 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
290 };
291
292 static struct ar8327_led_cfg rb962_ar8327_led_cfg = {
293 .led_ctrl0 = 0xc737c737,
294 .led_ctrl1 = 0x00000000,
295 .led_ctrl2 = 0x00000000,
296 .led_ctrl3 = 0x0030c300,
297 .open_drain = false,
298 };
299
300 static struct ar8327_platform_data rb962_ar8327_data = {
301 .pad0_cfg = &rb962_ar8327_pad0_cfg,
302 .pad6_cfg = &rb962_ar8327_pad6_cfg,
303 .port0_cfg = {
304 .force_link = 1,
305 .speed = AR8327_PORT_SPEED_1000,
306 .duplex = 1,
307 .txpause = 1,
308 .rxpause = 1,
309 },
310 .port6_cfg = {
311 .force_link = 1,
312 .speed = AR8327_PORT_SPEED_1000,
313 .duplex = 1,
314 .txpause = 1,
315 .rxpause = 1,
316 },
317 .led_cfg = &rb962_ar8327_led_cfg,
318 .num_leds = ARRAY_SIZE(rb962_leds_ar8327),
319 .leds = rb962_leds_ar8327,
320 };
321
322 static struct mdio_board_info rb962_mdio0_info[] = {
323 {
324 .bus_id = "ag71xx-mdio.0",
325 .phy_addr = 0,
326 .platform_data = &rb962_ar8327_data,
327 },
328 };
329
330 /* RB wAP-2nD gpios */
331 #define RBWAP_GPIO_LED_USER 14
332 #define RBWAP_GPIO_LED_WLAN 11
333 #define RBWAP_GPIO_BTN_RESET 16
334
335 static struct gpio_led rbwap_leds[] __initdata = {
336 {
337 .name = "rb:green:user",
338 .gpio = RBWAP_GPIO_LED_USER,
339 .active_low = 1,
340 }, {
341 .name = "rb:green:wlan",
342 .gpio = RBWAP_GPIO_LED_WLAN,
343 .active_low = 1,
344 },
345 };
346
347 /* RB cAP-2nD gpios */
348 #define RBCAP_GPIO_LED_1 14
349 #define RBCAP_GPIO_LED_2 12
350 #define RBCAP_GPIO_LED_3 11
351 #define RBCAP_GPIO_LED_4 4
352 #define RBCAP_GPIO_LED_ALL 13
353
354 static struct gpio_led rbcap_leds[] __initdata = {
355 {
356 .name = "rb:green:rssi1",
357 .gpio = RBCAP_GPIO_LED_1,
358 .active_low = 1,
359 }, {
360 .name = "rb:green:rssi2",
361 .gpio = RBCAP_GPIO_LED_2,
362 .active_low = 1,
363 }, {
364 .name = "rb:green:rssi3",
365 .gpio = RBCAP_GPIO_LED_3,
366 .active_low = 1,
367 }, {
368 .name = "rb:green:rssi4",
369 .gpio = RBCAP_GPIO_LED_4,
370 .active_low = 1,
371 },
372 };
373
374 /* RB mAP-2nD gpios */
375 #define RBMAP_SSR_BIT_LED_LAN1 0
376 #define RBMAP_SSR_BIT_LED_LAN2 1
377 #define RBMAP_SSR_BIT_LED_POEO 2
378 #define RBMAP_SSR_BIT_LED_USER 3
379 #define RBMAP_SSR_BIT_LED_WLAN 4
380 #define RBMAP_SSR_BIT_USB_POWER 5
381 #define RBMAP_SSR_BIT_LED_APCAP 6
382 #define RBMAP_GPIO_BTN_RESET 16
383 #define RBMAP_GPIO_SSR_CS 11
384 #define RBMAP_GPIO_LED_POWER 4
385 #define RBMAP_GPIO_POE_POWER 14
386 #define RBMAP_GPIO_POE_STATUS 12
387 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
388 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
389 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
390 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
391 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
392 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
393 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
394
395 static struct gpio_led rbmap_leds[] __initdata = {
396 {
397 .name = "rb:green:power",
398 .gpio = RBMAP_GPIO_LED_POWER,
399 .active_low = 1,
400 .default_state = LEDS_GPIO_DEFSTATE_ON,
401 }, {
402 .name = "rb:green:eth1",
403 .gpio = RBMAP_GPIO_LED_LAN1,
404 .active_low = 1,
405 }, {
406 .name = "rb:green:eth2",
407 .gpio = RBMAP_GPIO_LED_LAN2,
408 .active_low = 1,
409 }, {
410 .name = "rb:red:poe_out",
411 .gpio = RBMAP_GPIO_LED_POEO,
412 .active_low = 1,
413 }, {
414 .name = "rb:green:user",
415 .gpio = RBMAP_GPIO_LED_USER,
416 .active_low = 1,
417 }, {
418 .name = "rb:green:wlan",
419 .gpio = RBMAP_GPIO_LED_WLAN,
420 .active_low = 1,
421 }, {
422 .name = "rb:green:ap_cap",
423 .gpio = RBMAP_GPIO_LED_APCAP,
424 .active_low = 1,
425 },
426 };
427
428 /* RB LHG 5nD gpios */
429 #define RBLHG_GPIO_LED_0 13
430 #define RBLHG_GPIO_LED_1 12
431 #define RBLHG_GPIO_LED_2 4
432 #define RBLHG_GPIO_LED_3 21
433 #define RBLHG_GPIO_LED_4 18
434 #define RBLHG_GPIO_LED_ETH 14
435 #define RBLHG_GPIO_LED_POWER 11
436 #define RBLHG_GPIO_LED_USER 20
437 #define RBLHG_GPIO_BTN_RESET 15
438
439 static struct gpio_led rblhg_leds[] __initdata = {
440 {
441 .name = "rb:green:rssi0",
442 .gpio = RBLHG_GPIO_LED_0,
443 .active_low = 1,
444 }, {
445 .name = "rb:green:rssi1",
446 .gpio = RBLHG_GPIO_LED_1,
447 .active_low = 1,
448 }, {
449 .name = "rb:green:rssi2",
450 .gpio = RBLHG_GPIO_LED_2,
451 .active_low = 1,
452 }, {
453 .name = "rb:green:rssi3",
454 .gpio = RBLHG_GPIO_LED_3,
455 .active_low = 1,
456 }, {
457 .name = "rb:green:rssi4",
458 .gpio = RBLHG_GPIO_LED_4,
459 .active_low = 1,
460 }, {
461 .name = "rb:green:eth",
462 .gpio = RBLHG_GPIO_LED_ETH,
463 .active_low = 1,
464 }, {
465 .name = "rb:green:user",
466 .gpio = RBLHG_GPIO_LED_USER,
467 .active_low = 1,
468 }, {
469 .name = "rb:blue:power",
470 .gpio = RBLHG_GPIO_LED_POWER,
471 .active_low = 0,
472 .default_state = LEDS_GPIO_DEFSTATE_ON,
473 },
474 };
475
476 /* RB w APG-5HacT2HnD (wAP AC) gpios*/
477 #define RBWAPGSC_LED1 1
478 #define RBWAPGSC_LED2 8
479 #define RBWAPGSC_LED3 9
480 #define RBWAPGSC_POWERLED 16
481 #define RBWAPGSC_GPIO_BTN_RESET 1
482 #define RBWAPGSC_GPIO_MDIO_MDC 12
483 #define RBWAPGSC_GPIO_MDIO_DATA 11
484 #define RBWAPGSC_MDIO_PHYADDR 0
485
486 static struct gpio_led rbwapgsc_leds[] __initdata = {
487 {
488 .name = "rb:green:led1",
489 .gpio = RBWAPGSC_LED1,
490 .active_low = 1,
491 },{
492 .name = "rb:blue:power",
493 .gpio = RBWAPGSC_POWERLED,
494 .active_low = 1,
495 },
496 };
497
498 static struct mdio_gpio_platform_data rbwapgsc_mdio_data = {
499 .mdc = RBWAPGSC_GPIO_MDIO_MDC,
500 .mdio = RBWAPGSC_GPIO_MDIO_DATA,
501 .phy_mask = ~BIT(RBWAPGSC_MDIO_PHYADDR),
502 };
503
504 static struct platform_device rbwapgsc_phy_device = {
505 .name = "mdio-gpio",
506 .id = 1,
507 .dev = {
508 .platform_data = &rbwapgsc_mdio_data
509 },
510 };
511
512 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
513 .base = RBSPI_SSR_GPIO_BASE,
514 .num_registers = 1,
515 };
516
517 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
518 static int rbspi_spi_cs_gpios[] = {
519 -ENOENT, /* CS0 is always -ENOENT: natively handled */
520 -ENOENT, /* CS1 can be updated by the code as necessary */
521 };
522
523 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
524 .bus_num = 0,
525 .cs_gpios = rbspi_spi_cs_gpios,
526 };
527
528 /*
529 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
530 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
531 */
532 static struct spi_board_info rbspi_spi_info[] = {
533 {
534 .bus_num = 0,
535 .chip_select = 0,
536 .max_speed_hz = 25000000,
537 .modalias = "m25p80",
538 .platform_data = &rbspi_spi_flash_data,
539 }, {
540 .bus_num = 0,
541 .chip_select = 1,
542 .max_speed_hz = 25000000,
543 .modalias = "74x164",
544 .platform_data = &rbspi_ssr_data,
545 }
546 };
547
548 void __init rbspi_wlan_init(u16 id, int wmac_offset)
549 {
550 char *art_buf;
551 u8 wlan_mac[ETH_ALEN];
552
553 art_buf = rb_get_ext_wlan_data(id);
554 if (!art_buf)
555 return;
556
557 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
558 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
559
560 kfree(art_buf);
561 }
562
563 #define RBSPI_MACH_BUFLEN 64
564 /*
565 * Common platform init routine for all SPI NOR devices.
566 */
567 static int __init rbspi_platform_setup(void)
568 {
569 const struct rb_info *info;
570 char buf[RBSPI_MACH_BUFLEN] = "MikroTik ";
571 char *str;
572 int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1;
573
574 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
575 if (!info)
576 return -ENODEV;
577
578 if (info->board_name) {
579 str = "RouterBOARD ";
580 if (strncmp(info->board_name, str, strlen(str))) {
581 strncat(buf, str, len);
582 len -= strlen(str);
583 }
584 strncat(buf, info->board_name, len);
585 }
586 else
587 strncat(buf, "UNKNOWN", len);
588
589 mips_set_machine_name(buf);
590
591 /* fix partitions based on flash parsing */
592 rbspi_init_partitions(info);
593
594 return 0;
595 }
596
597 /*
598 * Common peripherals init routine for all SPI NOR devices.
599 * Sets SPI and USB.
600 */
601 static void __init rbspi_peripherals_setup(u32 flags)
602 {
603 unsigned spi_n;
604
605 if (flags & RBSPI_HAS_SSR)
606 spi_n = ARRAY_SIZE(rbspi_spi_info);
607 else
608 spi_n = 1; /* only one device on bus0 */
609
610 rbspi_ath79_spi_data.num_chipselect = spi_n;
611 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
612 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
613
614 if (flags & RBSPI_HAS_USB)
615 ath79_register_usb();
616
617 if (flags & RBSPI_HAS_PCI)
618 ath79_register_pci();
619 }
620
621 /*
622 * Common network init routine for all SPI NOR devices.
623 * Sets LAN/WAN/WLAN.
624 */
625 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
626 int wmac0_offset, int wmac1_offset)
627 {
628 /* for QCA953x that will init mdio1_device/data */
629 ath79_register_mdio(0, 0x0);
630 if (flags & RBSPI_HAS_MDIO1)
631 ath79_register_mdio(1, 0x0);
632
633 if (flags & RBSPI_HAS_WAN4) {
634 ath79_setup_ar934x_eth_cfg(0);
635
636 /* set switch to oper mode 1, PHY4 connected to CPU */
637 ath79_switch_data.phy4_mii_en = 1;
638 ath79_switch_data.phy_poll_mask |= BIT(4);
639
640 /* init GMAC0 connected to PHY4 at 100M */
641 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
642 ath79_eth0_data.phy_mask = BIT(4);
643 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
644 ath79_register_eth(0);
645 } else {
646 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
647 * to the internal switch.
648 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
649 * the QCA953x, this works because this configuration bit is
650 * the same as the AR934x. There's no equivalent function for
651 * QCA953x for now. */
652 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
653 }
654
655 /* init GMAC1 */
656 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
657 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
658 ath79_register_eth(1);
659
660 if (flags & RBSPI_HAS_WLAN0)
661 rbspi_wlan_init(0, wmac0_offset);
662
663 if (flags & RBSPI_HAS_WLAN1)
664 rbspi_wlan_init(1, wmac1_offset);
665 }
666
667 static __init void rbspi_register_reset_button(int gpio)
668 {
669 rbspi_gpio_keys_reset[0].gpio = gpio;
670 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
671 ARRAY_SIZE(rbspi_gpio_keys_reset),
672 rbspi_gpio_keys_reset);
673 }
674
675 /*
676 * Init the mAP lite hardware (QCA953x).
677 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
678 * Trying to use GMAC0 in direct mode was unsucessful, so we're
679 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
680 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
681 */
682 static void __init rbmapl_setup(void)
683 {
684 u32 flags = RBSPI_HAS_WLAN0;
685
686 if (rbspi_platform_setup())
687 return;
688
689 rbspi_peripherals_setup(flags);
690
691 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
692 rbspi_network_setup(flags, 0, 1, 0);
693
694 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
695
696 /* mAP lite has a single reset button as gpio 16 */
697 rbspi_register_reset_button(RBMAPL_GPIO_BTN_RESET);
698
699 /* clear internal multiplexing */
700 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
701 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
702 }
703
704 /*
705 * Init the hAP lite hardware (QCA953x).
706 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
707 * being assigned to LAN on the casing, and port 1 being assigned
708 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
709 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
710 */
711 static void __init rbhapl_setup(void)
712 {
713 u32 flags = RBSPI_HAS_WLAN0;
714
715 if (rbspi_platform_setup())
716 return;
717
718 rbspi_peripherals_setup(flags);
719
720 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
721 rbspi_network_setup(flags, 0, 4, 0);
722
723 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
724
725 /* hAP lite has a single reset button as gpio 16 */
726 rbspi_register_reset_button(RBHAPL_GPIO_BTN_RESET);
727 }
728
729 /*
730 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
731 */
732 static void __init rbspi_952_750r2_setup(u32 flags)
733 {
734 if (flags & RBSPI_HAS_SSR)
735 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
736
737 rbspi_peripherals_setup(flags);
738
739 /*
740 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
741 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
742 */
743 rbspi_network_setup(flags, 1, 5, 6);
744
745 if (flags & RBSPI_HAS_USB)
746 gpio_request_one(RB952_GPIO_USB_POWER,
747 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
748 "USB power");
749
750 if (flags & RBSPI_HAS_POE)
751 gpio_request_one(RB952_GPIO_POE_POWER,
752 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
753 "POE power");
754
755 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
756
757 /* These devices have a single reset button as gpio 16 */
758 rbspi_register_reset_button(RB952_GPIO_BTN_RESET);
759 }
760
761 /*
762 * Init the hAP (ac lite) hardware (QCA953x).
763 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
764 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
765 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
766 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
767 * internal switch for the LAN ports.
768 * The device also has USB, PoE output and an SSR used for LED multiplexing.
769 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
770 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
771 */
772 static void __init rb952_setup(void)
773 {
774 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
775 RBSPI_HAS_SSR | RBSPI_HAS_POE;
776
777 if (rbspi_platform_setup())
778 return;
779
780 /* differentiate the hAP from the hAP ac lite */
781 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
782 flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI;
783 else
784 flags |= RBSPI_HAS_WLAN0;
785
786 rbspi_952_750r2_setup(flags);
787 }
788
789 /*
790 * Init the hEX (PoE) lite hardware (QCA953x).
791 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
792 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
793 * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
794 * lite, only without USB. It shares the same bootloader board identifier.
795 */
796 static void __init rb750upr2_setup(void)
797 {
798 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
799
800 if (rbspi_platform_setup())
801 return;
802
803 /* differentiate the hEX lite from the hEX PoE lite */
804 if (strstr(mips_get_machine_name(), "750UP r2"))
805 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
806
807 /* differentiate the Powerbox from the hEX lite */
808 else if (strstr(mips_get_machine_name(), "750P r2"))
809 flags |= RBSPI_HAS_POE;
810
811 rbspi_952_750r2_setup(flags);
812 }
813
814 /*
815 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
816 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
817 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
818 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
819 * The SFP cage is not assigned by default on RouterOS. Extra work is required
820 * to support this interface as it is directly connected to the SoC (eth1).
821 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
822 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
823 * they are not attached to GPIOs, extra work is required to support these.
824 * PoE and USB output power control is supported.
825 */
826 static void __init rb962_setup(void)
827 {
828 u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI;
829
830 if (rbspi_platform_setup())
831 return;
832
833 rbspi_peripherals_setup(flags);
834
835 /* Do not call rbspi_network_setup as we have a discrete switch chip */
836 ath79_eth0_pll_data.pll_1000 = 0xae000000;
837 ath79_eth0_pll_data.pll_100 = 0xa0000101;
838 ath79_eth0_pll_data.pll_10 = 0xa0001313;
839
840 ath79_register_mdio(0, 0x0);
841 mdiobus_register_board_info(rb962_mdio0_info,
842 ARRAY_SIZE(rb962_mdio0_info));
843
844 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
845
846 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
847 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
848 ath79_eth0_data.phy_mask = BIT(0);
849 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
850 ath79_register_eth(0);
851
852 /* WLAN1 MAC is HW MAC + 7 */
853 rbspi_wlan_init(1, 7);
854
855 if (flags & RBSPI_HAS_USB)
856 gpio_request_one(RB962_GPIO_USB_POWER,
857 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
858 "USB power");
859
860 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
861 if (flags & RBSPI_HAS_POE)
862 gpio_request_one(RB962_GPIO_POE_POWER,
863 GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
864 GPIOF_EXPORT_DIR_FIXED,
865 "POE power");
866
867 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio),
868 rb962_leds_gpio);
869
870 /* This device has a single reset button as gpio 20 */
871 rbspi_register_reset_button(RB962_GPIO_BTN_RESET);
872 }
873
874 /*
875 * Init the LHG hardware (AR9344).
876 * The LHG 5nD has a single ethernet port connected to PHY0.
877 * Wireless is provided via 5GHz WLAN1.
878 */
879 static void __init rblhg_setup(void)
880 {
881 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
882
883 if (rbspi_platform_setup())
884 return;
885
886 rbspi_peripherals_setup(flags);
887
888 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
889 rbspi_network_setup(flags, 0, 0, 1);
890
891 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
892
893 rbspi_register_reset_button(RBLHG_GPIO_BTN_RESET);
894 }
895
896 /*
897 * Init the wAP hardware.
898 * The wAP 2nD has a single ethernet port.
899 */
900 static void __init rbwap_setup(void)
901 {
902 u32 flags = RBSPI_HAS_WLAN0;
903
904 if (rbspi_platform_setup())
905 return;
906
907 rbspi_peripherals_setup(flags);
908
909 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
910 rbspi_network_setup(flags, 0, 1, 0);
911
912 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
913
914 /* wAP has a single reset button as GPIO 16 */
915 rbspi_register_reset_button(RBWAP_GPIO_BTN_RESET);
916 }
917
918 /*
919 * Init the cAP hardware (EXPERIMENTAL).
920 * The cAP 2nD has a single ethernet port, and a global LED switch.
921 */
922 static void __init rbcap_setup(void)
923 {
924 u32 flags = RBSPI_HAS_WLAN0;
925
926 if (rbspi_platform_setup())
927 return;
928
929 rbspi_peripherals_setup(flags);
930
931 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
932 rbspi_network_setup(flags, 0, 1, 0);
933
934 gpio_request_one(RBCAP_GPIO_LED_ALL,
935 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
936 "LEDs enable");
937
938 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
939 }
940
941 /*
942 * Init the mAP hardware.
943 * The mAP 2nD has two ethernet ports, PoE output, SSR for LED
944 * multiplexing and USB port.
945 */
946 static void __init rbmap_setup(void)
947 {
948 u32 flags = RBSPI_HAS_USB | RBSPI_HAS_WLAN0 |
949 RBSPI_HAS_SSR | RBSPI_HAS_POE;
950
951 if (rbspi_platform_setup())
952 return;
953
954 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
955 rbspi_peripherals_setup(flags);
956
957 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
958 rbspi_network_setup(flags, 0, 2, 0);
959
960 if (flags & RBSPI_HAS_POE)
961 gpio_request_one(RBMAP_GPIO_POE_POWER,
962 GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
963 "POE power");
964
965 /* USB power GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
966 if (flags & RBSPI_HAS_USB)
967 gpio_request_one(RBMAP_GPIO_USB_POWER,
968 GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
969 GPIOF_EXPORT_DIR_FIXED,
970 "USB power");
971
972 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
973
974 /* mAP 2nD has a single reset button as gpio 16 */
975 rbspi_register_reset_button(RBMAP_GPIO_BTN_RESET);
976 }
977
978 /*
979 * Init the wAPGSC (RB wAPG-5HacT2HnD // wAP AC) hardware.
980 * The wAPGSC has one Ethernet port via AR8033 with PoE input, dual radio (SoC
981 * 2.4 GHz and external QCA9880) and a ZT2046Q temperature and voltage sensor
982 * (currently not supported).
983 */
984 static void __init rbwapgsc_setup(void)
985 {
986 u32 flags = RBSPI_HAS_PCI;
987
988 if (rbspi_platform_setup())
989 return;
990
991 rbspi_peripherals_setup(flags);
992
993 platform_device_register(&rbwapgsc_phy_device);
994
995 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
996 ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
997 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
998 ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
999 ath79_eth1_pll_data.pll_1000 = 0x03000101;
1000 ath79_eth1_pll_data.pll_100 = 0x80000101;
1001 ath79_eth1_pll_data.pll_10 = 0x80001313;
1002 ath79_eth1_data.speed = SPEED_1000;
1003 ath79_eth1_data.duplex = DUPLEX_FULL;
1004 ath79_register_eth(1);
1005
1006 rbspi_wlan_init(1, 2);
1007
1008 rbspi_register_reset_button(RBWAPGSC_GPIO_BTN_RESET);
1009
1010 ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE|
1011 QCA955X_GPIO_REG_OUT_FUNC4|
1012 QCA955X_GPIO_REG_OUT_FUNC3);
1013
1014 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwapgsc_leds),
1015 rbwapgsc_leds);
1016 }
1017
1018 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
1019 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
1020 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
1021 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962, "962", rb962_setup);
1022 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
1023 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
1024 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
1025 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
1026 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);
1027 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPAC, "wapg-sc", rbwapgsc_setup);
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