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[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 952Ui-5ac2nD
8 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
9 * - MikroTik RouterBOARD 750UP r2
10 * - MikroTik RouterBOARD 750P-PBr2
11 * - MikroTik RouterBOARD 750 r2
12 * - MikroTik RouterBOARD LHG 5nD
13 *
14 * Preliminary support for the following hardware
15 * - MikroTik RouterBOARD wAP2nD
16 * - MikroTik RouterBOARD cAP2nD
17 * - MikroTik RouterBOARD mAP2nD
18 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
19 * hardware as the mAP L-2nD. It is unknown if they share the same board
20 * identifier.
21 *
22 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
23 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
24 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
25 *
26 * This program is free software; you can redistribute it and/or modify it
27 * under the terms of the GNU General Public License version 2 as published
28 * by the Free Software Foundation.
29 */
30
31 #include <linux/pci.h>
32 #include <linux/platform_device.h>
33 #include <linux/phy.h>
34 #include <linux/routerboot.h>
35 #include <linux/gpio.h>
36
37 #include <linux/spi/spi.h>
38 #include <linux/spi/74x164.h>
39
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/partitions.h>
42
43 #include <linux/ar8216_platform.h>
44
45 #include <asm/prom.h>
46 #include <asm/mach-ath79/ar71xx_regs.h>
47 #include <asm/mach-ath79/ath79.h>
48
49 #include "common.h"
50 #include "dev-eth.h"
51 #include "dev-spi.h"
52 #include "dev-gpio-buttons.h"
53 #include "dev-leds-gpio.h"
54 #include "dev-m25p80.h"
55 #include "dev-usb.h"
56 #include "dev-wmac.h"
57 #include "machtypes.h"
58 #include "pci.h"
59 #include "routerboot.h"
60
61 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
62 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
63
64 #define RBSPI_HAS_USB BIT(0)
65 #define RBSPI_HAS_WLAN0 BIT(1)
66 #define RBSPI_HAS_WLAN1 BIT(2)
67 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
68 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
69 #define RBSPI_HAS_POE BIT(5)
70 #define RBSPI_HAS_MDIO1 BIT(6)
71 #define RBSPI_HAS_PCI BIT(7)
72
73 #define RB_ROUTERBOOT_OFFSET 0x0000
74 #define RB_BIOS_SIZE 0x1000
75 #define RB_SOFT_CFG_SIZE 0x1000
76
77 /* Flash partitions indexes */
78 enum {
79 RBSPI_PART_RBOOT,
80 RBSPI_PART_HCONF,
81 RBSPI_PART_BIOS,
82 RBSPI_PART_RBOOT2,
83 RBSPI_PART_SCONF,
84 RBSPI_PART_FIRMW,
85 RBSPI_PARTS
86 };
87
88 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
89
90 /*
91 * Setup the SPI flash partition table based on initial parsing.
92 * The kernel can be at any aligned position and have any size.
93 */
94 static void __init rbspi_init_partitions(const struct rb_info *info)
95 {
96 struct mtd_partition *parts = rbspi_spi_partitions;
97 memset(parts, 0x0, sizeof(*parts));
98
99 parts[RBSPI_PART_RBOOT].name = "routerboot";
100 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
101 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
102 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
103
104 parts[RBSPI_PART_HCONF].name = "hard_config";
105 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
106 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
107 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
108
109 parts[RBSPI_PART_BIOS].name = "bios";
110 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
111 + info->hard_cfg_size;
112 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
113 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
114
115 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
116 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
117 + RB_BIOS_SIZE;
118 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
119 - parts[RBSPI_PART_RBOOT2].offset;
120 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
121
122 parts[RBSPI_PART_SCONF].name = "soft_config";
123 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
124 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
125
126 parts[RBSPI_PART_FIRMW].name = "firmware";
127 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
128 + parts[RBSPI_PART_SCONF].size;
129 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
130 }
131
132 static struct flash_platform_data rbspi_spi_flash_data = {
133 .parts = rbspi_spi_partitions,
134 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
135 };
136
137 /* Several boards only have a single reset button wired to GPIO 16 */
138 #define RBSPI_GPIO_BTN_RESET16 16
139 #define RBSPI_GPIO_BTN_RESET20 20
140
141 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
142 {
143 .desc = "Reset button",
144 .type = EV_KEY,
145 .code = KEY_RESTART,
146 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
147 .gpio = RBSPI_GPIO_BTN_RESET16,
148 .active_low = 1,
149 },
150 };
151
152 static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = {
153 {
154 .desc = "Reset button",
155 .type = EV_KEY,
156 .code = KEY_RESTART,
157 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
158 .gpio = RBSPI_GPIO_BTN_RESET20,
159 .active_low = 1,
160 },
161 };
162
163 /* RB mAP L-2nD gpios */
164 #define RBMAPL_GPIO_LED_POWER 17
165 #define RBMAPL_GPIO_LED_USER 14
166 #define RBMAPL_GPIO_LED_ETH 4
167 #define RBMAPL_GPIO_LED_WLAN 11
168
169 static struct gpio_led rbmapl_leds[] __initdata = {
170 {
171 .name = "rb:green:power",
172 .gpio = RBMAPL_GPIO_LED_POWER,
173 .active_low = 0,
174 .default_state = LEDS_GPIO_DEFSTATE_ON,
175 }, {
176 .name = "rb:green:user",
177 .gpio = RBMAPL_GPIO_LED_USER,
178 .active_low = 0,
179 }, {
180 .name = "rb:green:eth",
181 .gpio = RBMAPL_GPIO_LED_ETH,
182 .active_low = 0,
183 }, {
184 .name = "rb:green:wlan",
185 .gpio = RBMAPL_GPIO_LED_WLAN,
186 .active_low = 0,
187 },
188 };
189
190 /* RB 941L-2nD gpios */
191 #define RBHAPL_GPIO_LED_USER 14
192 static struct gpio_led rbhapl_leds[] __initdata = {
193 {
194 .name = "rb:green:user",
195 .gpio = RBHAPL_GPIO_LED_USER,
196 .active_low = 1,
197 },
198 };
199
200 /* common RB SSRs */
201 #define RBSPI_SSR_GPIO_BASE 40
202 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
203
204 /* RB 951Ui-2nD gpios */
205 #define RB952_SSR_BIT_LED_LAN1 0
206 #define RB952_SSR_BIT_LED_LAN2 1
207 #define RB952_SSR_BIT_LED_LAN3 2
208 #define RB952_SSR_BIT_LED_LAN4 3
209 #define RB952_SSR_BIT_LED_LAN5 4
210 #define RB952_SSR_BIT_USB_POWER 5
211 #define RB952_SSR_BIT_LED_WLAN 6
212 #define RB952_GPIO_SSR_CS 11
213 #define RB952_GPIO_LED_USER 4
214 #define RB952_GPIO_POE_POWER 14
215 #define RB952_GPIO_POE_STATUS 12
216 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
217 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
218 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
219 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
220 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
221 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
222 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
223
224 static struct gpio_led rb952_leds[] __initdata = {
225 {
226 .name = "rb:green:user",
227 .gpio = RB952_GPIO_LED_USER,
228 .active_low = 0,
229 }, {
230 .name = "rb:blue:wlan",
231 .gpio = RB952_GPIO_LED_WLAN,
232 .active_low = 1,
233 }, {
234 .name = "rb:green:port1",
235 .gpio = RB952_GPIO_LED_LAN1,
236 .active_low = 1,
237 }, {
238 .name = "rb:green:port2",
239 .gpio = RB952_GPIO_LED_LAN2,
240 .active_low = 1,
241 }, {
242 .name = "rb:green:port3",
243 .gpio = RB952_GPIO_LED_LAN3,
244 .active_low = 1,
245 }, {
246 .name = "rb:green:port4",
247 .gpio = RB952_GPIO_LED_LAN4,
248 .active_low = 1,
249 }, {
250 .name = "rb:green:port5",
251 .gpio = RB952_GPIO_LED_LAN5,
252 .active_low = 1,
253 },
254 };
255
256
257 /* RB 962UiGS-5HacT2HnT gpios */
258 #define RB962_GPIO_POE_STATUS 2
259 #define RB962_GPIO_POE_POWER 3
260 #define RB962_GPIO_LED_USER 12
261 #define RB962_GPIO_USB_POWER 13
262
263 static struct gpio_led rb962_leds_gpio[] __initdata = {
264 {
265 .name = "rb:green:user",
266 .gpio = RB962_GPIO_LED_USER,
267 .active_low = 1,
268 },
269 };
270
271 static const struct ar8327_led_info rb962_leds_ar8327[] = {
272 AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"),
273 AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"),
274 AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"),
275 AR8327_LED_INFO(PHY3_0, HW, "rb:green:port4"),
276 AR8327_LED_INFO(PHY4_0, HW, "rb:green:port5"),
277 };
278
279 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg = {
280 .mode = AR8327_PAD_MAC_RGMII,
281 .txclk_delay_en = true,
282 .rxclk_delay_en = true,
283 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
284 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
285 .mac06_exchange_dis = true,
286 };
287
288 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg = {
289 /* Use SGMII interface for GMAC6 of the AR8337 switch */
290 .mode = AR8327_PAD_MAC_SGMII,
291 .rxclk_delay_en = true,
292 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
293 };
294
295 static struct ar8327_led_cfg rb962_ar8327_led_cfg = {
296 .led_ctrl0 = 0xc737c737,
297 .led_ctrl1 = 0x00000000,
298 .led_ctrl2 = 0x00000000,
299 .led_ctrl3 = 0x0030c300,
300 .open_drain = false,
301 };
302
303 static struct ar8327_platform_data rb962_ar8327_data = {
304 .pad0_cfg = &rb962_ar8327_pad0_cfg,
305 .pad6_cfg = &rb962_ar8327_pad6_cfg,
306 .port0_cfg = {
307 .force_link = 1,
308 .speed = AR8327_PORT_SPEED_1000,
309 .duplex = 1,
310 .txpause = 1,
311 .rxpause = 1,
312 },
313 .port6_cfg = {
314 .force_link = 1,
315 .speed = AR8327_PORT_SPEED_1000,
316 .duplex = 1,
317 .txpause = 1,
318 .rxpause = 1,
319 },
320 .led_cfg = &rb962_ar8327_led_cfg,
321 .num_leds = ARRAY_SIZE(rb962_leds_ar8327),
322 .leds = rb962_leds_ar8327,
323 };
324
325 static struct mdio_board_info rb962_mdio0_info[] = {
326 {
327 .bus_id = "ag71xx-mdio.0",
328 .phy_addr = 0,
329 .platform_data = &rb962_ar8327_data,
330 },
331 };
332
333 /* RB wAP-2nD gpios */
334 #define RBWAP_GPIO_LED_USER 14
335 #define RBWAP_GPIO_LED_WLAN 11
336
337 static struct gpio_led rbwap_leds[] __initdata = {
338 {
339 .name = "rb:green:user",
340 .gpio = RBWAP_GPIO_LED_USER,
341 .active_low = 1,
342 }, {
343 .name = "rb:green:wlan",
344 .gpio = RBWAP_GPIO_LED_WLAN,
345 .active_low = 1,
346 },
347 };
348
349 /* RB cAP-2nD gpios */
350 #define RBCAP_GPIO_LED_1 14
351 #define RBCAP_GPIO_LED_2 12
352 #define RBCAP_GPIO_LED_3 11
353 #define RBCAP_GPIO_LED_4 4
354 #define RBCAP_GPIO_LED_ALL 13
355
356 static struct gpio_led rbcap_leds[] __initdata = {
357 {
358 .name = "rb:green:rssi1",
359 .gpio = RBCAP_GPIO_LED_1,
360 .active_low = 1,
361 }, {
362 .name = "rb:green:rssi2",
363 .gpio = RBCAP_GPIO_LED_2,
364 .active_low = 1,
365 }, {
366 .name = "rb:green:rssi3",
367 .gpio = RBCAP_GPIO_LED_3,
368 .active_low = 1,
369 }, {
370 .name = "rb:green:rssi4",
371 .gpio = RBCAP_GPIO_LED_4,
372 .active_low = 1,
373 },
374 };
375
376 /* RB mAP-2nD gpios */
377 #define RBMAP_SSR_BIT_LED_LAN1 0
378 #define RBMAP_SSR_BIT_LED_LAN2 1
379 #define RBMAP_SSR_BIT_LED_POEO 2
380 #define RBMAP_SSR_BIT_LED_USER 3
381 #define RBMAP_SSR_BIT_LED_WLAN 4
382 #define RBMAP_SSR_BIT_USB_POWER 5
383 #define RBMAP_SSR_BIT_LED_APCAP 6
384 #define RBMAP_GPIO_SSR_CS 11
385 #define RBMAP_GPIO_LED_POWER 4
386 #define RBMAP_GPIO_POE_POWER 14
387 #define RBMAP_GPIO_POE_STATUS 12
388 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
389 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
390 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
391 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
392 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
393 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
394 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
395
396 static struct gpio_led rbmap_leds[] __initdata = {
397 {
398 .name = "rb:green:power",
399 .gpio = RBMAP_GPIO_LED_POWER,
400 .active_low = 1,
401 .default_state = LEDS_GPIO_DEFSTATE_ON,
402 }, {
403 .name = "rb:green:eth1",
404 .gpio = RBMAP_GPIO_LED_LAN1,
405 .active_low = 1,
406 }, {
407 .name = "rb:green:eth2",
408 .gpio = RBMAP_GPIO_LED_WLAN,
409 .active_low = 1,
410 }, {
411 .name = "rb:red:poe_out",
412 .gpio = RBMAP_GPIO_LED_POEO,
413 .active_low = 1,
414 }, {
415 .name = "rb:green:user",
416 .gpio = RBMAP_GPIO_LED_USER,
417 .active_low = 1,
418 }, {
419 .name = "rb:green:wlan",
420 .gpio = RBMAP_GPIO_LED_WLAN,
421 .active_low = 1,
422 }, {
423 .name = "rb:green:ap_cap",
424 .gpio = RBMAP_GPIO_LED_APCAP,
425 .active_low = 1,
426 },
427 };
428
429 /* RB LHG 5nD gpios */
430 #define RBLHG_GPIO_LED_0 13
431 #define RBLHG_GPIO_LED_1 12
432 #define RBLHG_GPIO_LED_2 4
433 #define RBLHG_GPIO_LED_3 21
434 #define RBLHG_GPIO_LED_4 18
435 #define RBLHG_GPIO_LED_ETH 14
436 #define RBLHG_GPIO_LED_POWER 11
437 #define RBLHG_GPIO_LED_USER 20
438 #define RBLHG_GPIO_BTN_RESET 15
439
440 static struct gpio_led rblhg_leds[] __initdata = {
441 {
442 .name = "rb:green:rssi0",
443 .gpio = RBLHG_GPIO_LED_0,
444 .active_low = 1,
445 }, {
446 .name = "rb:green:rssi1",
447 .gpio = RBLHG_GPIO_LED_1,
448 .active_low = 1,
449 }, {
450 .name = "rb:green:rssi2",
451 .gpio = RBLHG_GPIO_LED_2,
452 .active_low = 1,
453 }, {
454 .name = "rb:green:rssi3",
455 .gpio = RBLHG_GPIO_LED_3,
456 .active_low = 1,
457 }, {
458 .name = "rb:green:rssi4",
459 .gpio = RBLHG_GPIO_LED_4,
460 .active_low = 1,
461 }, {
462 .name = "rb:green:eth",
463 .gpio = RBLHG_GPIO_LED_ETH,
464 .active_low = 1,
465 }, {
466 .name = "rb:green:user",
467 .gpio = RBLHG_GPIO_LED_USER,
468 .active_low = 1,
469 }, {
470 .name = "rb:blue:power",
471 .gpio = RBLHG_GPIO_LED_POWER,
472 .active_low = 0,
473 .default_state = LEDS_GPIO_DEFSTATE_ON,
474 },
475 };
476
477 static struct gpio_keys_button rblhg_gpio_keys[] __initdata = {
478 {
479 .desc = "Reset button",
480 .type = EV_KEY,
481 .code = KEY_RESTART,
482 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
483 .gpio = RBLHG_GPIO_BTN_RESET,
484 .active_low = 1,
485 },
486 };
487
488
489 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
490 .base = RBSPI_SSR_GPIO_BASE,
491 .num_registers = 1,
492 };
493
494 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
495 static int rbspi_spi_cs_gpios[] = {
496 -ENOENT, /* CS0 is always -ENOENT: natively handled */
497 -ENOENT, /* CS1 can be updated by the code as necessary */
498 };
499
500 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
501 .bus_num = 0,
502 .cs_gpios = rbspi_spi_cs_gpios,
503 };
504
505 /*
506 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
507 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
508 */
509 static struct spi_board_info rbspi_spi_info[] = {
510 {
511 .bus_num = 0,
512 .chip_select = 0,
513 .max_speed_hz = 25000000,
514 .modalias = "m25p80",
515 .platform_data = &rbspi_spi_flash_data,
516 }, {
517 .bus_num = 0,
518 .chip_select = 1,
519 .max_speed_hz = 25000000,
520 .modalias = "74x164",
521 .platform_data = &rbspi_ssr_data,
522 }
523 };
524
525 void __init rbspi_wlan_init(u16 id, int wmac_offset)
526 {
527 char *art_buf;
528 u8 wlan_mac[ETH_ALEN];
529
530 art_buf = rb_get_ext_wlan_data(id);
531 if (!art_buf)
532 return;
533
534 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
535 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
536
537 kfree(art_buf);
538 }
539
540 #define RBSPI_MACH_BUFLEN 64
541 /*
542 * Common platform init routine for all SPI NOR devices.
543 */
544 static int __init rbspi_platform_setup(void)
545 {
546 const struct rb_info *info;
547 char buf[RBSPI_MACH_BUFLEN] = "MikroTik ";
548 char *str;
549 int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1;
550
551 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
552 if (!info)
553 return -ENODEV;
554
555 if (info->board_name) {
556 str = "RouterBOARD ";
557 if (strncmp(info->board_name, str, strlen(str))) {
558 strncat(buf, str, len);
559 len -= strlen(str);
560 }
561 strncat(buf, info->board_name, len);
562 }
563 else
564 strncat(buf, "UNKNOWN", len);
565
566 mips_set_machine_name(buf);
567
568 /* fix partitions based on flash parsing */
569 rbspi_init_partitions(info);
570
571 return 0;
572 }
573
574 /*
575 * Common peripherals init routine for all SPI NOR devices.
576 * Sets SPI and USB.
577 */
578 static void __init rbspi_peripherals_setup(u32 flags)
579 {
580 unsigned spi_n;
581
582 if (flags & RBSPI_HAS_SSR)
583 spi_n = ARRAY_SIZE(rbspi_spi_info);
584 else
585 spi_n = 1; /* only one device on bus0 */
586
587 rbspi_ath79_spi_data.num_chipselect = spi_n;
588 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
589 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
590
591 if (flags & RBSPI_HAS_USB)
592 ath79_register_usb();
593
594 if (flags & RBSPI_HAS_PCI)
595 ath79_register_pci();
596 }
597
598 /*
599 * Common network init routine for all SPI NOR devices.
600 * Sets LAN/WAN/WLAN.
601 */
602 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
603 int wmac0_offset, int wmac1_offset)
604 {
605 /* for QCA953x that will init mdio1_device/data */
606 ath79_register_mdio(0, 0x0);
607 if (flags & RBSPI_HAS_MDIO1)
608 ath79_register_mdio(1, 0x0);
609
610 if (flags & RBSPI_HAS_WAN4) {
611 ath79_setup_ar934x_eth_cfg(0);
612
613 /* set switch to oper mode 1, PHY4 connected to CPU */
614 ath79_switch_data.phy4_mii_en = 1;
615 ath79_switch_data.phy_poll_mask |= BIT(4);
616
617 /* init GMAC0 connected to PHY4 at 100M */
618 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
619 ath79_eth0_data.phy_mask = BIT(4);
620 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
621 ath79_register_eth(0);
622 } else {
623 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
624 * to the internal switch.
625 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
626 * the QCA953x, this works because this configuration bit is
627 * the same as the AR934x. There's no equivalent function for
628 * QCA953x for now. */
629 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
630 }
631
632 /* init GMAC1 */
633 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
634 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
635 ath79_register_eth(1);
636
637 if (flags & RBSPI_HAS_WLAN0)
638 rbspi_wlan_init(0, wmac0_offset);
639
640 if (flags & RBSPI_HAS_WLAN1)
641 rbspi_wlan_init(1, wmac1_offset);
642 }
643
644 /*
645 * Init the mAP lite hardware (QCA953x).
646 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
647 * Trying to use GMAC0 in direct mode was unsucessful, so we're
648 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
649 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
650 */
651 static void __init rbmapl_setup(void)
652 {
653 u32 flags = RBSPI_HAS_WLAN0;
654
655 if (rbspi_platform_setup())
656 return;
657
658 rbspi_peripherals_setup(flags);
659
660 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
661 rbspi_network_setup(flags, 0, 1, 0);
662
663 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
664
665 /* mAP lite has a single reset button as gpio 16 */
666 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
667 ARRAY_SIZE(rbspi_gpio_keys_reset16),
668 rbspi_gpio_keys_reset16);
669
670 /* clear internal multiplexing */
671 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
672 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
673 }
674
675 /*
676 * Init the hAP lite hardware (QCA953x).
677 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
678 * being assigned to LAN on the casing, and port 1 being assigned
679 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
680 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
681 */
682 static void __init rbhapl_setup(void)
683 {
684 u32 flags = RBSPI_HAS_WLAN0;
685
686 if (rbspi_platform_setup())
687 return;
688
689 rbspi_peripherals_setup(flags);
690
691 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
692 rbspi_network_setup(flags, 0, 4, 0);
693
694 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
695
696 /* hAP lite has a single reset button as gpio 16 */
697 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
698 ARRAY_SIZE(rbspi_gpio_keys_reset16),
699 rbspi_gpio_keys_reset16);
700 }
701
702 /*
703 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
704 */
705 static void __init rbspi_952_750r2_setup(u32 flags)
706 {
707 if (flags & RBSPI_HAS_SSR)
708 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
709
710 rbspi_peripherals_setup(flags);
711
712 /*
713 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
714 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
715 */
716 rbspi_network_setup(flags, 1, 5, 6);
717
718 if (flags & RBSPI_HAS_USB)
719 gpio_request_one(RB952_GPIO_USB_POWER,
720 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
721 "USB power");
722
723 if (flags & RBSPI_HAS_POE)
724 gpio_request_one(RB952_GPIO_POE_POWER,
725 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
726 "POE power");
727
728 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
729
730 /* These devices have a single reset button as gpio 16 */
731 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
732 ARRAY_SIZE(rbspi_gpio_keys_reset16),
733 rbspi_gpio_keys_reset16);
734 }
735
736 /*
737 * Init the hAP (ac lite) hardware (QCA953x).
738 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
739 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
740 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
741 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
742 * internal switch for the LAN ports.
743 * The device also has USB, PoE output and an SSR used for LED multiplexing.
744 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
745 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
746 */
747 static void __init rb952_setup(void)
748 {
749 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
750 RBSPI_HAS_SSR | RBSPI_HAS_POE;
751
752 if (rbspi_platform_setup())
753 return;
754
755 /* differentiate the hAP from the hAP ac lite */
756 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
757 flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI;
758 else
759 flags |= RBSPI_HAS_WLAN0;
760
761 rbspi_952_750r2_setup(flags);
762 }
763
764 /*
765 * Init the hEX (PoE) lite hardware (QCA953x).
766 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
767 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
768 * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
769 * lite, only without USB. It shares the same bootloader board identifier.
770 */
771 static void __init rb750upr2_setup(void)
772 {
773 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
774
775 if (rbspi_platform_setup())
776 return;
777
778 /* differentiate the hEX lite from the hEX PoE lite */
779 if (strstr(mips_get_machine_name(), "750UP r2"))
780 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
781
782 /* differentiate the Powerbox from the hEX lite */
783 else if (strstr(mips_get_machine_name(), "750P r2"))
784 flags |= RBSPI_HAS_POE;
785
786 rbspi_952_750r2_setup(flags);
787 }
788
789 /*
790 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
791 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
792 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
793 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
794 * The SFP cage is not assigned by default on RouterOS. Extra work is required
795 * to support this interface as it is directly connected to the SoC (eth1).
796 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
797 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
798 * they are not attached to GPIOs, extra work is required to support these.
799 * PoE and USB output power control is supported.
800 */
801 static void __init rb962_setup(void)
802 {
803 u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI;
804
805 if (rbspi_platform_setup())
806 return;
807
808 rbspi_peripherals_setup(flags);
809
810 /* Do not call rbspi_network_setup as we have a discrete switch chip */
811 ath79_eth0_pll_data.pll_1000 = 0xae000000;
812 ath79_eth0_pll_data.pll_100 = 0xa0000101;
813 ath79_eth0_pll_data.pll_10 = 0xa0001313;
814
815 ath79_register_mdio(0, 0x0);
816 mdiobus_register_board_info(rb962_mdio0_info,
817 ARRAY_SIZE(rb962_mdio0_info));
818
819 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
820
821 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
822 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
823 ath79_eth0_data.phy_mask = BIT(0);
824 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
825 ath79_register_eth(0);
826
827 /* WLAN1 MAC is HW MAC + 7 */
828 rbspi_wlan_init(1, 7);
829
830 if (flags & RBSPI_HAS_USB)
831 gpio_request_one(RB962_GPIO_USB_POWER,
832 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
833 "USB power");
834
835 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
836 if (flags & RBSPI_HAS_POE)
837 gpio_request_one(RB962_GPIO_POE_POWER,
838 GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
839 GPIOF_EXPORT_DIR_FIXED,
840 "POE power");
841
842 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio),
843 rb962_leds_gpio);
844
845 /* This device has a single reset button as gpio 20 */
846 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
847 ARRAY_SIZE(rbspi_gpio_keys_reset20),
848 rbspi_gpio_keys_reset20);
849 }
850
851 /*
852 * Init the LHG hardware (AR9344).
853 * The LHG 5nD has a single ethernet port connected to PHY0.
854 * Wireless is provided via 5GHz WLAN1.
855 */
856 static void __init rblhg_setup(void)
857 {
858 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
859
860 if (rbspi_platform_setup())
861 return;
862
863 rbspi_peripherals_setup(flags);
864
865 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
866 rbspi_network_setup(flags, 0, 0, 1);
867
868 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
869
870 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
871 ARRAY_SIZE(rblhg_gpio_keys),
872 rblhg_gpio_keys);
873 }
874
875 /*
876 * Init the wAP hardware (EXPERIMENTAL).
877 * The wAP 2nD has a single ethernet port.
878 */
879 static void __init rbwap_setup(void)
880 {
881 u32 flags = RBSPI_HAS_WLAN0;
882
883 if (rbspi_platform_setup())
884 return;
885
886 rbspi_peripherals_setup(flags);
887
888 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
889 rbspi_network_setup(flags, 0, 1, 0);
890
891 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
892 }
893
894 /*
895 * Init the cAP hardware (EXPERIMENTAL).
896 * The cAP 2nD has a single ethernet port, and a global LED switch.
897 */
898 static void __init rbcap_setup(void)
899 {
900 u32 flags = RBSPI_HAS_WLAN0;
901
902 if (rbspi_platform_setup())
903 return;
904
905 rbspi_peripherals_setup(flags);
906
907 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
908 rbspi_network_setup(flags, 0, 1, 0);
909
910 gpio_request_one(RBCAP_GPIO_LED_ALL,
911 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
912 "LEDs enable");
913
914 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
915 }
916
917 /*
918 * Init the mAP hardware (EXPERIMENTAL).
919 * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED
920 * multiplexing.
921 */
922 static void __init rbmap_setup(void)
923 {
924 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_SSR | RBSPI_HAS_POE;
925
926 if (rbspi_platform_setup())
927 return;
928
929 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
930 rbspi_peripherals_setup(flags);
931
932 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
933 rbspi_network_setup(flags, 0, 2, 0);
934
935 if (flags & RBSPI_HAS_POE)
936 gpio_request_one(RBMAP_GPIO_POE_POWER,
937 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
938 "POE power");
939
940 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
941 }
942
943
944 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
945 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
946 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
947 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962, "962", rb962_setup);
948 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
949 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
950 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
951 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
952 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);
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