b26b1ae46eb7c3fcf94863249608b9f379c4189c
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 750UP r2
8 * - MikroTik RouterBOARD 750 r2
9 * - MikroTik RouterBOARD LHG 5nD
10 *
11 * Preliminary support for the following hardware
12 * - MikroTik RouterBOARD wAP2nD
13 * - MikroTik RouterBOARD cAP2nD
14 * - MikroTik RouterBOARD mAP2nD
15 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
16 * hardware as the mAP L-2nD. It is unknown if they share the same board
17 * identifier.
18 *
19 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License version 2 as published
23 * by the Free Software Foundation.
24 */
25
26 #include <linux/platform_device.h>
27 #include <linux/phy.h>
28 #include <linux/routerboot.h>
29 #include <linux/gpio.h>
30
31 #include <linux/spi/spi.h>
32 #include <linux/spi/74x164.h>
33
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/partitions.h>
36
37 #include <asm/prom.h>
38 #include <asm/mach-ath79/ar71xx_regs.h>
39 #include <asm/mach-ath79/ath79.h>
40
41 #include "common.h"
42 #include "dev-eth.h"
43 #include "dev-spi.h"
44 #include "dev-gpio-buttons.h"
45 #include "dev-leds-gpio.h"
46 #include "dev-m25p80.h"
47 #include "dev-usb.h"
48 #include "dev-wmac.h"
49 #include "machtypes.h"
50 #include "routerboot.h"
51
52 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
53 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
54
55 #define RBSPI_HAS_USB BIT(0)
56 #define RBSPI_HAS_WLAN0 BIT(1)
57 #define RBSPI_HAS_WLAN1 BIT(2)
58 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
59 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
60 #define RBSPI_HAS_POE BIT(5)
61 #define RBSPI_HAS_MDIO1 BIT(6)
62
63 #define RB_ROUTERBOOT_OFFSET 0x0000
64 #define RB_BIOS_SIZE 0x1000
65 #define RB_SOFT_CFG_SIZE 0x1000
66
67 /* Flash partitions indexes */
68 enum {
69 RBSPI_PART_RBOOT,
70 RBSPI_PART_HCONF,
71 RBSPI_PART_BIOS,
72 RBSPI_PART_RBOOT2,
73 RBSPI_PART_SCONF,
74 RBSPI_PART_FIRMW,
75 RBSPI_PARTS
76 };
77
78 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
79
80 /*
81 * Setup the SPI flash partition table based on initial parsing.
82 * The kernel can be at any aligned position and have any size.
83 */
84 static void __init rbspi_init_partitions(const struct rb_info *info)
85 {
86 struct mtd_partition *parts = rbspi_spi_partitions;
87 memset(parts, 0x0, sizeof(*parts));
88
89 parts[RBSPI_PART_RBOOT].name = "routerboot";
90 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
91 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
92 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
93
94 parts[RBSPI_PART_HCONF].name = "hard_config";
95 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
96 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
97 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
98
99 parts[RBSPI_PART_BIOS].name = "bios";
100 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
101 + info->hard_cfg_size;
102 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
103 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
104
105 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
106 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
107 + RB_BIOS_SIZE;
108 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
109 - parts[RBSPI_PART_RBOOT2].offset;
110 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
111
112 parts[RBSPI_PART_SCONF].name = "soft_config";
113 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
114 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
115
116 parts[RBSPI_PART_FIRMW].name = "firmware";
117 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
118 + parts[RBSPI_PART_SCONF].size;
119 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
120 }
121
122 static struct flash_platform_data rbspi_spi_flash_data = {
123 .parts = rbspi_spi_partitions,
124 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
125 };
126
127 /* Several boards only have a single reset button wired to GPIO 16 */
128 #define RBSPI_GPIO_BTN_RESET16 16
129
130 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
131 {
132 .desc = "Reset button",
133 .type = EV_KEY,
134 .code = KEY_RESTART,
135 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
136 .gpio = RBSPI_GPIO_BTN_RESET16,
137 .active_low = 1,
138 },
139 };
140
141 /* RB mAP L-2nD gpios */
142 #define RBMAPL_GPIO_LED_POWER 17
143 #define RBMAPL_GPIO_LED_USER 14
144 #define RBMAPL_GPIO_LED_ETH 4
145 #define RBMAPL_GPIO_LED_WLAN 11
146
147 static struct gpio_led rbmapl_leds[] __initdata = {
148 {
149 .name = "rb:green:power",
150 .gpio = RBMAPL_GPIO_LED_POWER,
151 .active_low = 0,
152 .default_state = LEDS_GPIO_DEFSTATE_ON,
153 }, {
154 .name = "rb:green:user",
155 .gpio = RBMAPL_GPIO_LED_USER,
156 .active_low = 0,
157 }, {
158 .name = "rb:green:eth",
159 .gpio = RBMAPL_GPIO_LED_ETH,
160 .active_low = 0,
161 }, {
162 .name = "rb:green:wlan",
163 .gpio = RBMAPL_GPIO_LED_WLAN,
164 .active_low = 0,
165 },
166 };
167
168 /* RB 941L-2nD gpios */
169 #define RBHAPL_GPIO_LED_USER 14
170 static struct gpio_led rbhapl_leds[] __initdata = {
171 {
172 .name = "rb:green:user",
173 .gpio = RBHAPL_GPIO_LED_USER,
174 .active_low = 1,
175 },
176 };
177
178 /* common RB SSRs */
179 #define RBSPI_SSR_GPIO_BASE 40
180 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
181
182 /* RB 951Ui-2nD gpios */
183 #define RB952_SSR_BIT_LED_LAN1 0
184 #define RB952_SSR_BIT_LED_LAN2 1
185 #define RB952_SSR_BIT_LED_LAN3 2
186 #define RB952_SSR_BIT_LED_LAN4 3
187 #define RB952_SSR_BIT_LED_LAN5 4
188 #define RB952_SSR_BIT_USB_POWER 5
189 #define RB952_SSR_BIT_LED_WLAN 6
190 #define RB952_GPIO_SSR_CS 11
191 #define RB952_GPIO_LED_USER 4
192 #define RB952_GPIO_POE_POWER 14
193 #define RB952_GPIO_POE_STATUS 12
194 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
195 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
196 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
197 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
198 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
199 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
200 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
201
202 static struct gpio_led rb952_leds[] __initdata = {
203 {
204 .name = "rb:green:user",
205 .gpio = RB952_GPIO_LED_USER,
206 .active_low = 0,
207 }, {
208 .name = "rb:blue:wlan",
209 .gpio = RB952_GPIO_LED_WLAN,
210 .active_low = 1,
211 }, {
212 .name = "rb:green:port1",
213 .gpio = RB952_GPIO_LED_LAN1,
214 .active_low = 1,
215 }, {
216 .name = "rb:green:port2",
217 .gpio = RB952_GPIO_LED_LAN2,
218 .active_low = 1,
219 }, {
220 .name = "rb:green:port3",
221 .gpio = RB952_GPIO_LED_LAN3,
222 .active_low = 1,
223 }, {
224 .name = "rb:green:port4",
225 .gpio = RB952_GPIO_LED_LAN4,
226 .active_low = 1,
227 }, {
228 .name = "rb:green:port5",
229 .gpio = RB952_GPIO_LED_LAN5,
230 .active_low = 1,
231 },
232 };
233
234 /* RB wAP-2nD gpios */
235 #define RBWAP_GPIO_LED_USER 14
236 #define RBWAP_GPIO_LED_WLAN 11
237
238 static struct gpio_led rbwap_leds[] __initdata = {
239 {
240 .name = "rb:green:user",
241 .gpio = RBWAP_GPIO_LED_USER,
242 .active_low = 1,
243 }, {
244 .name = "rb:green:wlan",
245 .gpio = RBWAP_GPIO_LED_WLAN,
246 .active_low = 1,
247 },
248 };
249
250 /* RB cAP-2nD gpios */
251 #define RBCAP_GPIO_LED_1 14
252 #define RBCAP_GPIO_LED_2 12
253 #define RBCAP_GPIO_LED_3 11
254 #define RBCAP_GPIO_LED_4 4
255 #define RBCAP_GPIO_LED_ALL 13
256
257 static struct gpio_led rbcap_leds[] __initdata = {
258 {
259 .name = "rb:green:rssi1",
260 .gpio = RBCAP_GPIO_LED_1,
261 .active_low = 1,
262 }, {
263 .name = "rb:green:rssi2",
264 .gpio = RBCAP_GPIO_LED_2,
265 .active_low = 1,
266 }, {
267 .name = "rb:green:rssi3",
268 .gpio = RBCAP_GPIO_LED_3,
269 .active_low = 1,
270 }, {
271 .name = "rb:green:rssi4",
272 .gpio = RBCAP_GPIO_LED_4,
273 .active_low = 1,
274 },
275 };
276
277 /* RB mAP-2nD gpios */
278 #define RBMAP_SSR_BIT_LED_LAN1 0
279 #define RBMAP_SSR_BIT_LED_LAN2 1
280 #define RBMAP_SSR_BIT_LED_POEO 2
281 #define RBMAP_SSR_BIT_LED_USER 3
282 #define RBMAP_SSR_BIT_LED_WLAN 4
283 #define RBMAP_SSR_BIT_USB_POWER 5
284 #define RBMAP_SSR_BIT_LED_APCAP 6
285 #define RBMAP_GPIO_SSR_CS 11
286 #define RBMAP_GPIO_LED_POWER 4
287 #define RBMAP_GPIO_POE_POWER 14
288 #define RBMAP_GPIO_POE_STATUS 12
289 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
290 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
291 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
292 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
293 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
294 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
295 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
296
297 static struct gpio_led rbmap_leds[] __initdata = {
298 {
299 .name = "rb:green:power",
300 .gpio = RBMAP_GPIO_LED_POWER,
301 .active_low = 1,
302 .default_state = LEDS_GPIO_DEFSTATE_ON,
303 }, {
304 .name = "rb:green:eth1",
305 .gpio = RBMAP_GPIO_LED_LAN1,
306 .active_low = 1,
307 }, {
308 .name = "rb:green:eth2",
309 .gpio = RBMAP_GPIO_LED_WLAN,
310 .active_low = 1,
311 }, {
312 .name = "rb:red:poe_out",
313 .gpio = RBMAP_GPIO_LED_POEO,
314 .active_low = 1,
315 }, {
316 .name = "rb:green:user",
317 .gpio = RBMAP_GPIO_LED_USER,
318 .active_low = 1,
319 }, {
320 .name = "rb:green:wlan",
321 .gpio = RBMAP_GPIO_LED_WLAN,
322 .active_low = 1,
323 }, {
324 .name = "rb:green:ap_cap",
325 .gpio = RBMAP_GPIO_LED_APCAP,
326 .active_low = 1,
327 },
328 };
329
330 /* RB LHG 5nD gpios */
331 #define RBLHG_GPIO_LED_0 13
332 #define RBLHG_GPIO_LED_1 12
333 #define RBLHG_GPIO_LED_2 4
334 #define RBLHG_GPIO_LED_3 21
335 #define RBLHG_GPIO_LED_4 18
336 #define RBLHG_GPIO_LED_ETH 14
337 #define RBLHG_GPIO_LED_POWER 11
338 #define RBLHG_GPIO_LED_USER 20
339 #define RBLHG_GPIO_BTN_RESET 15
340
341 static struct gpio_led rblhg_leds[] __initdata = {
342 {
343 .name = "rb:green:rssi0",
344 .gpio = RBLHG_GPIO_LED_0,
345 .active_low = 1,
346 }, {
347 .name = "rb:green:rssi1",
348 .gpio = RBLHG_GPIO_LED_1,
349 .active_low = 1,
350 }, {
351 .name = "rb:green:rssi2",
352 .gpio = RBLHG_GPIO_LED_2,
353 .active_low = 1,
354 }, {
355 .name = "rb:green:rssi3",
356 .gpio = RBLHG_GPIO_LED_3,
357 .active_low = 1,
358 }, {
359 .name = "rb:green:rssi4",
360 .gpio = RBLHG_GPIO_LED_4,
361 .active_low = 1,
362 }, {
363 .name = "rb:green:eth",
364 .gpio = RBLHG_GPIO_LED_ETH,
365 .active_low = 1,
366 }, {
367 .name = "rb:green:user",
368 .gpio = RBLHG_GPIO_LED_USER,
369 .active_low = 1,
370 }, {
371 .name = "rb:blue:power",
372 .gpio = RBLHG_GPIO_LED_POWER,
373 .active_low = 0,
374 .default_state = LEDS_GPIO_DEFSTATE_ON,
375 },
376 };
377
378 static struct gpio_keys_button rblhg_gpio_keys[] __initdata = {
379 {
380 .desc = "Reset button",
381 .type = EV_KEY,
382 .code = KEY_RESTART,
383 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
384 .gpio = RBLHG_GPIO_BTN_RESET,
385 .active_low = 1,
386 },
387 };
388
389
390 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
391 .base = RBSPI_SSR_GPIO_BASE,
392 };
393
394 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
395 static int rbspi_spi_cs_gpios[] = {
396 -ENOENT, /* CS0 is always -ENOENT: natively handled */
397 -ENOENT, /* CS1 can be updated by the code as necessary */
398 };
399
400 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
401 .bus_num = 0,
402 .cs_gpios = rbspi_spi_cs_gpios,
403 };
404
405 /*
406 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
407 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
408 */
409 static struct spi_board_info rbspi_spi_info[] = {
410 {
411 .bus_num = 0,
412 .chip_select = 0,
413 .max_speed_hz = 25000000,
414 .modalias = "m25p80",
415 .platform_data = &rbspi_spi_flash_data,
416 }, {
417 .bus_num = 0,
418 .chip_select = 1,
419 .max_speed_hz = 25000000,
420 .modalias = "74x164",
421 .platform_data = &rbspi_ssr_data,
422 }
423 };
424
425 void __init rbspi_wlan_init(u16 id, int wmac_offset)
426 {
427 char *art_buf;
428 u8 wlan_mac[ETH_ALEN];
429
430 art_buf = rb_get_ext_wlan_data(id);
431 if (!art_buf)
432 return;
433
434 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
435 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
436
437 kfree(art_buf);
438 }
439
440 /*
441 * Common platform init routine for all SPI NOR devices.
442 */
443 static int __init rbspi_platform_setup(void)
444 {
445 const struct rb_info *info;
446 char buf[64];
447
448 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
449 if (!info)
450 return -ENODEV;
451
452 scnprintf(buf, sizeof(buf), "MikroTik %s",
453 (info->board_name) ? info->board_name : "");
454 mips_set_machine_name(buf);
455
456 /* fix partitions based on flash parsing */
457 rbspi_init_partitions(info);
458
459 return 0;
460 }
461
462 /*
463 * Common peripherals init routine for all SPI NOR devices.
464 * Sets SPI and USB.
465 */
466 static void __init rbspi_peripherals_setup(u32 flags)
467 {
468 unsigned spi_n;
469
470 if (flags & RBSPI_HAS_SSR)
471 spi_n = ARRAY_SIZE(rbspi_spi_info);
472 else
473 spi_n = 1; /* only one device on bus0 */
474
475 rbspi_ath79_spi_data.num_chipselect = spi_n;
476 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
477 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
478
479 if (flags & RBSPI_HAS_USB)
480 ath79_register_usb();
481 }
482
483 /*
484 * Common network init routine for all SPI NOR devices.
485 * Sets LAN/WAN/WLAN.
486 */
487 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
488 int wmac0_offset, int wmac1_offset)
489 {
490 /* for QCA953x that will init mdio1_device/data */
491 ath79_register_mdio(0, 0x0);
492 if (flags & RBSPI_HAS_MDIO1)
493 ath79_register_mdio(1, 0x0);
494
495 if (flags & RBSPI_HAS_WAN4) {
496 ath79_setup_ar934x_eth_cfg(0);
497
498 /* set switch to oper mode 1, PHY4 connected to CPU */
499 ath79_switch_data.phy4_mii_en = 1;
500 ath79_switch_data.phy_poll_mask |= BIT(4);
501
502 /* init GMAC0 connected to PHY4 at 100M */
503 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
504 ath79_eth0_data.phy_mask = BIT(4);
505 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
506 ath79_register_eth(0);
507 } else {
508 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
509 * to the internal switch.
510 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
511 * the QCA953x, this works because this configuration bit is
512 * the same as the AR934x. There's no equivalent function for
513 * QCA953x for now. */
514 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
515 }
516
517 /* init GMAC1 */
518 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
519 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
520 ath79_register_eth(1);
521
522 if (flags & RBSPI_HAS_WLAN0)
523 rbspi_wlan_init(0, wmac0_offset);
524
525 if (flags & RBSPI_HAS_WLAN1)
526 rbspi_wlan_init(1, wmac1_offset);
527 }
528
529 /*
530 * Init the mAP lite hardware (QCA953x).
531 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
532 * Trying to use GMAC0 in direct mode was unsucessful, so we're
533 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
534 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
535 */
536 static void __init rbmapl_setup(void)
537 {
538 u32 flags = RBSPI_HAS_WLAN0;
539
540 if (rbspi_platform_setup())
541 return;
542
543 rbspi_peripherals_setup(flags);
544
545 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
546 rbspi_network_setup(flags, 0, 1, 0);
547
548 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
549
550 /* mAP lite has a single reset button as gpio 16 */
551 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
552 ARRAY_SIZE(rbspi_gpio_keys_reset16),
553 rbspi_gpio_keys_reset16);
554
555 /* clear internal multiplexing */
556 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
557 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
558 }
559
560 /*
561 * Init the hAP lite hardware (QCA953x).
562 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
563 * being assigned to LAN on the casing, and port 1 being assigned
564 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
565 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
566 */
567 static void __init rbhapl_setup(void)
568 {
569 u32 flags = RBSPI_HAS_WLAN0;
570
571 if (rbspi_platform_setup())
572 return;
573
574 rbspi_peripherals_setup(flags);
575
576 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
577 rbspi_network_setup(flags, 0, 4, 0);
578
579 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
580
581 /* hAP lite has a single reset button as gpio 16 */
582 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
583 ARRAY_SIZE(rbspi_gpio_keys_reset16),
584 rbspi_gpio_keys_reset16);
585 }
586
587 /*
588 * The hAP, hEX lite and hEX PoE lite share the same platform
589 */
590 static void __init rbspi_952_750r2_setup(u32 flags)
591 {
592 if (flags & RBSPI_HAS_SSR)
593 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
594
595 rbspi_peripherals_setup(flags);
596
597 /* GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 */
598 rbspi_network_setup(flags, 1, 5, 0);
599
600 if (flags & RBSPI_HAS_USB)
601 gpio_request_one(RB952_GPIO_USB_POWER,
602 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
603 "USB power");
604
605 if (flags & RBSPI_HAS_POE)
606 gpio_request_one(RB952_GPIO_POE_POWER,
607 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
608 "POE power");
609
610 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
611
612 /* These devices have a single reset button as gpio 16 */
613 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
614 ARRAY_SIZE(rbspi_gpio_keys_reset16),
615 rbspi_gpio_keys_reset16);
616 }
617
618 /*
619 * Init the hAP hardware (QCA953x).
620 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
621 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
622 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
623 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
624 * internal switch for the LAN ports.
625 * The device also has USB, PoE output and an SSR used for LED multiplexing.
626 */
627 static void __init rb952_setup(void)
628 {
629 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
630 RBSPI_HAS_SSR | RBSPI_HAS_POE;
631
632 if (rbspi_platform_setup())
633 return;
634
635 rbspi_952_750r2_setup(flags);
636 }
637
638 /*
639 * Init the hEX (PoE) lite hardware (QCA953x).
640 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
641 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
642 * without USB and POE. It shares the same bootloader board identifier.
643 */
644 static void __init rb750upr2_setup(void)
645 {
646 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
647
648 if (rbspi_platform_setup())
649 return;
650
651 /* differentiate the hEX lite from the hEX PoE lite */
652 if (strstr(mips_get_machine_name(), "750UP r2"))
653 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
654
655 rbspi_952_750r2_setup(flags);
656 }
657
658 /*
659 * Init the LHG hardware (AR9344).
660 * The LHG 5nD has a single ethernet port connected to PHY0.
661 * Wireless is provided via 5GHz WLAN1.
662 */
663 static void __init rblhg_setup(void)
664 {
665 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
666
667 if (rbspi_platform_setup())
668 return;
669
670 rbspi_peripherals_setup(flags);
671
672 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
673 rbspi_network_setup(flags, 0, 0, 1);
674
675 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
676
677 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
678 ARRAY_SIZE(rblhg_gpio_keys),
679 rblhg_gpio_keys);
680 }
681
682 /*
683 * Init the wAP hardware (EXPERIMENTAL).
684 * The wAP 2nD has a single ethernet port.
685 */
686 static void __init rbwap_setup(void)
687 {
688 u32 flags = RBSPI_HAS_WLAN0;
689
690 if (rbspi_platform_setup())
691 return;
692
693 rbspi_peripherals_setup(flags);
694
695 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
696 rbspi_network_setup(flags, 0, 1, 0);
697
698 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
699 }
700
701 /*
702 * Init the cAP hardware (EXPERIMENTAL).
703 * The cAP 2nD has a single ethernet port, and a global LED switch.
704 */
705 static void __init rbcap_setup(void)
706 {
707 u32 flags = RBSPI_HAS_WLAN0;
708
709 if (rbspi_platform_setup())
710 return;
711
712 rbspi_peripherals_setup(flags);
713
714 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
715 rbspi_network_setup(flags, 0, 1, 0);
716
717 gpio_request_one(RBCAP_GPIO_LED_ALL,
718 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
719 "LEDs enable");
720
721 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
722 }
723
724 /*
725 * Init the mAP hardware (EXPERIMENTAL).
726 * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED
727 * multiplexing.
728 */
729 static void __init rbmap_setup(void)
730 {
731 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_SSR | RBSPI_HAS_POE;
732
733 if (rbspi_platform_setup())
734 return;
735
736 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
737 rbspi_peripherals_setup(flags);
738
739 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
740 rbspi_network_setup(flags, 0, 2, 0);
741
742 if (flags & RBSPI_HAS_POE)
743 gpio_request_one(RBMAP_GPIO_POE_POWER,
744 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
745 "POE power");
746
747 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
748 }
749
750
751 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
752 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
753 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
754 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
755 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
756 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
757 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
758 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);