target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c

   1 /*
   2  *  MikroTik SPI-NOR RouterBOARDs support
   3  *
   4  *  - MikroTik RouterBOARD mAP L-2nD
   5  *  - MikroTik RouterBOARD 941L-2nD
   6  *  - MikroTik RouterBOARD 951Ui-2nD
   7  *  - MikroTik RouterBOARD 750UP r2
   8  *
   9  *  Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/phy.h>
  18 #include <linux/routerboot.h>
  19 #include <linux/gpio.h>
  20
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/74x164.h>
  23
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26
  27 #include <asm/prom.h>
  28 #include <asm/mach-ath79/ar71xx_regs.h>
  29 #include <asm/mach-ath79/ath79.h>
  30
  31 #include "common.h"
  32 #include "dev-eth.h"
  33 #include "dev-spi.h"
  34 #include "dev-gpio-buttons.h"
  35 #include "dev-leds-gpio.h"
  36 #include "dev-m25p80.h"
  37 #include "dev-usb.h"
  38 #include "dev-wmac.h"
  39 #include "machtypes.h"
  40 #include "routerboot.h"
  41
  42 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
  43 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
  44
  45 #define RBSPI_HAS_USB           BIT(0)
  46 #define RBSPI_HAS_WLAN          BIT(1)
  47 #define RBSPI_HAS_WAN4          BIT(2)  /* has WAN port on PHY4 */
  48 #define RBSPI_HAS_SSR           BIT(3)  /* has an SSR on SPI bus 0 */
  49 #define RBSPI_HAS_POE           BIT(4)
  50
  51 #define RB_ROUTERBOOT_OFFSET    0x0000
  52 #define RB_BIOS_SIZE            0x1000
  53 #define RB_SOFT_CFG_SIZE        0x1000
  54 #define RB_KERNEL_SIZE          (2 * 1024 * 1024)       /* 2MB kernel */
  55
  56 /* Flash partitions indexes */
  57 enum {
  58         RBSPI_PART_RBOOT,
  59         RBSPI_PART_HCONF,
  60         RBSPI_PART_BIOS,
  61         RBSPI_PART_RBOOT2,
  62         RBSPI_PART_SCONF,
  63         RBSPI_PART_KERN,
  64         RBSPI_PART_ROOT,
  65         RBSPI_PARTS
  66 };
  67
  68 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
  69
  70 /*
  71  * Setup the SPI flash partition table based on initial parsing.
  72  * The kernel can be at any aligned position and have any size.
  73  * The size of the kernel partition is the desired RB_KERNEL_SIZE
  74  * minus the size of the preceding partitions (128KB).
  75  */
  76 static void __init rbspi_init_partitions(const struct rb_info *info)
  77 {
  78         struct mtd_partition *parts = rbspi_spi_partitions;
  79         memset(parts, 0x0, sizeof(*parts));
  80
  81         parts[RBSPI_PART_RBOOT].name = "routerboot";
  82         parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
  83         parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
  84         parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
  85
  86         parts[RBSPI_PART_HCONF].name = "hard_config";
  87         parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
  88         parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
  89         parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
  90
  91         parts[RBSPI_PART_BIOS].name = "bios";
  92         parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
  93                                         + info->hard_cfg_size;
  94         parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
  95         parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
  96
  97         parts[RBSPI_PART_RBOOT2].name = "routerboot2";
  98         parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
  99                                         + RB_BIOS_SIZE;
 100         parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
 101                                         - parts[RBSPI_PART_RBOOT2].offset;
 102         parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
 103
 104         parts[RBSPI_PART_SCONF].name = "soft_config";
 105         parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
 106         parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
 107
 108         parts[RBSPI_PART_KERN].name = "kernel";
 109         parts[RBSPI_PART_KERN].offset = parts[RBSPI_PART_SCONF].offset
 110                                         + parts[RBSPI_PART_SCONF].size;
 111         parts[RBSPI_PART_KERN].size = RB_KERNEL_SIZE
 112                                         - parts[RBSPI_PART_KERN].offset;
 113
 114         parts[RBSPI_PART_ROOT].name = "rootfs";
 115         parts[RBSPI_PART_ROOT].offset = parts[RBSPI_PART_KERN].offset
 116                                         + parts[RBSPI_PART_KERN].size;
 117         parts[RBSPI_PART_ROOT].size = MTDPART_SIZ_FULL;
 118 }
 119
 120 static struct flash_platform_data rbspi_spi_flash_data = {
 121         .parts = rbspi_spi_partitions,
 122         .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
 123 };
 124
 125 /* Several boards only have a single reset button wired to GPIO 16 */
 126 #define RBSPI_GPIO_BTN_RESET16  16
 127
 128 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
 129         {
 130                 .desc = "Reset button",
 131                 .type = EV_KEY,
 132                 .code = KEY_RESTART,
 133                 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
 134                 .gpio = RBSPI_GPIO_BTN_RESET16,
 135                 .active_low = 1,
 136         },
 137 };
 138
 139 /* RB mAP L-2nD gpios */
 140 #define RBMAPL_GPIO_LED_POWER   17
 141 #define RBMAPL_GPIO_LED_USER    14
 142 #define RBMAPL_GPIO_LED_ETH     4
 143 #define RBMAPL_GPIO_LED_WLAN    11
 144
 145 static struct gpio_led rbmapl_leds[] __initdata = {
 146         {
 147                 .name = "rb:green:power",
 148                 .gpio = RBMAPL_GPIO_LED_POWER,
 149                 .active_low = 0,
 150                 .default_state = LEDS_GPIO_DEFSTATE_ON,
 151         }, {
 152                 .name = "rb:green:user",
 153                 .gpio = RBMAPL_GPIO_LED_USER,
 154                 .active_low = 0,
 155         }, {
 156                 .name = "rb:green:eth",
 157                 .gpio = RBMAPL_GPIO_LED_ETH,
 158                 .active_low = 0,
 159         }, {
 160                 .name = "rb:green:wlan",
 161                 .gpio = RBMAPL_GPIO_LED_WLAN,
 162                 .active_low = 0,
 163         },
 164 };
 165
 166 /* RB 941L-2nD gpios */
 167 #define RBHAPL_GPIO_LED_USER   14
 168 static struct gpio_led rbhapl_leds[] __initdata = {
 169         {
 170                 .name = "rb:green:user",
 171                 .gpio = RBHAPL_GPIO_LED_USER,
 172                 .active_low = 1,
 173         },
 174 };
 175
 176 /* common RB SSRs */
 177 #define RBSPI_SSR_GPIO_BASE     40
 178 #define RBSPI_SSR_GPIO(bit)     (RBSPI_SSR_GPIO_BASE + (bit))
 179
 180 /* RB 951Ui-2nD gpios */
 181 #define RB952_SSR_BIT_LED_LAN1  0
 182 #define RB952_SSR_BIT_LED_LAN2  1
 183 #define RB952_SSR_BIT_LED_LAN3  2
 184 #define RB952_SSR_BIT_LED_LAN4  3
 185 #define RB952_SSR_BIT_LED_LAN5  4
 186 #define RB952_SSR_BIT_USB_POWER 5
 187 #define RB952_SSR_BIT_LED_WLAN  6
 188 #define RB952_GPIO_SSR_CS       11
 189 #define RB952_GPIO_LED_USER     4
 190 #define RB952_GPIO_POE_POWER    14
 191 #define RB952_GPIO_USB_POWER    RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
 192 #define RB952_GPIO_LED_LAN1     RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
 193 #define RB952_GPIO_LED_LAN2     RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
 194 #define RB952_GPIO_LED_LAN3     RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
 195 #define RB952_GPIO_LED_LAN4     RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
 196 #define RB952_GPIO_LED_LAN5     RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
 197 #define RB952_GPIO_LED_WLAN     RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
 198
 199 static struct gpio_led rb952_leds[] __initdata = {
 200         {
 201                 .name = "rb:green:user",
 202                 .gpio = RB952_GPIO_LED_USER,
 203                 .active_low = 0,
 204         }, {
 205                 .name = "rb:blue:wlan",
 206                 .gpio = RB952_GPIO_LED_WLAN,
 207                 .active_low = 1,
 208         }, {
 209                 .name = "rb:green:port1",
 210                 .gpio = RB952_GPIO_LED_LAN1,
 211                 .active_low = 1,
 212         }, {
 213                 .name = "rb:green:port2",
 214                 .gpio = RB952_GPIO_LED_LAN2,
 215                 .active_low = 1,
 216         }, {
 217                 .name = "rb:green:port3",
 218                 .gpio = RB952_GPIO_LED_LAN3,
 219                 .active_low = 1,
 220         }, {
 221                 .name = "rb:green:port4",
 222                 .gpio = RB952_GPIO_LED_LAN4,
 223                 .active_low = 1,
 224         }, {
 225                 .name = "rb:green:port5",
 226                 .gpio = RB952_GPIO_LED_LAN5,
 227                 .active_low = 1,
 228         },
 229 };
 230
 231 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
 232         .base = RBSPI_SSR_GPIO_BASE,
 233 };
 234
 235 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
 236 static int rbspi_spi_cs_gpios[] = {
 237         -ENOENT,        /* CS0 is always -ENOENT: natively handled */
 238         -ENOENT,        /* CS1 can be updated by the code as necessary */
 239 };
 240
 241 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
 242         .bus_num = 0,
 243         .cs_gpios = rbspi_spi_cs_gpios,
 244 };
 245
 246 /*
 247  * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
 248  * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
 249  */
 250 static struct spi_board_info rbspi_spi_info[] = {
 251         {
 252                 .bus_num        = 0,
 253                 .chip_select    = 0,
 254                 .max_speed_hz   = 25000000,
 255                 .modalias       = "m25p80",
 256                 .platform_data  = &rbspi_spi_flash_data,
 257         }, {
 258                 .bus_num        = 0,
 259                 .chip_select    = 1,
 260                 .max_speed_hz   = 25000000,
 261                 .modalias       = "74x164",
 262                 .platform_data  = &rbspi_ssr_data,
 263         }
 264 };
 265
 266 void __init rbspi_wlan_init(int wmac_offset)
 267 {
 268         char *art_buf;
 269         u8 wlan_mac[ETH_ALEN];
 270
 271         art_buf = rb_get_wlan_data();
 272         if (!art_buf)
 273                 return;
 274
 275         ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
 276         ath79_register_wmac(art_buf + 0x1000, wlan_mac);
 277
 278         kfree(art_buf);
 279 }
 280
 281 /*
 282  * Common platform init routine for all SPI NOR devices.
 283  */
 284 static int __init rbspi_platform_setup(void)
 285 {
 286         const struct rb_info *info;
 287         char buf[64];
 288
 289         info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
 290         if (!info)
 291                 return -ENODEV;
 292
 293         scnprintf(buf, sizeof(buf), "MikroTik %s",
 294                 (info->board_name) ? info->board_name : "");
 295         mips_set_machine_name(buf);
 296
 297         /* fix partitions based on flash parsing */
 298         rbspi_init_partitions(info);
 299
 300         return 0;
 301 }
 302
 303 /*
 304  * Common peripherals init routine for all SPI NOR devices.
 305  * Sets SPI and USB.
 306  */
 307 static void __init rbspi_peripherals_setup(u32 flags)
 308 {
 309         unsigned spi_n;
 310
 311         if (flags & RBSPI_HAS_SSR)
 312                 spi_n = ARRAY_SIZE(rbspi_spi_info);
 313         else
 314                 spi_n = 1;     /* only one device on bus0 */
 315
 316         rbspi_ath79_spi_data.num_chipselect = spi_n;
 317         rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
 318         ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
 319
 320         if (flags & RBSPI_HAS_USB)
 321                 ath79_register_usb();
 322 }
 323
 324 /*
 325  * Common network init routine for all SPI NOR devices.
 326  * Sets LAN/WAN/WLAN.
 327  */
 328 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
 329                                         int wmac_offset)
 330 {
 331         /* for QCA953x that will init mdio1_device/data */
 332         ath79_register_mdio(0, 0x0);
 333
 334         if (flags & RBSPI_HAS_WAN4) {
 335                 ath79_setup_ar934x_eth_cfg(0);
 336
 337                 /* set switch to oper mode 1, PHY4 connected to CPU */
 338                 ath79_switch_data.phy4_mii_en = 1;
 339                 ath79_switch_data.phy_poll_mask |= BIT(4);
 340
 341                 /* init GMAC0 connected to PHY4 at 100M */
 342                 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 343                 ath79_eth0_data.phy_mask = BIT(4);
 344                 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
 345                 ath79_register_eth(0);
 346         } else {
 347                 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
 348                  * to the internal switch.
 349                  * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
 350                  * the QCA953x, this works because this configuration bit is
 351                  * the same as the AR934x. There's no equivalent function for
 352                  * QCA953x for now. */
 353                 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
 354         }
 355
 356         /* init GMAC1 */
 357         ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
 358         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 359         ath79_register_eth(1);
 360
 361         if (flags & RBSPI_HAS_WLAN)
 362                 rbspi_wlan_init(wmac_offset);
 363 }
 364
 365 /*
 366  * Init the mAP lite hardware.
 367  * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
 368  * Trying to use GMAC0 in direct mode was unsucessful, so we're
 369  * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
 370  * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
 371  */
 372 static void __init rbmapl_setup(void)
 373 {
 374         u32 flags = RBSPI_HAS_WLAN;
 375
 376         if (rbspi_platform_setup())
 377                 return;
 378
 379         rbspi_peripherals_setup(flags);
 380
 381         /* GMAC1 is HW MAC, WLAN MAC is HW MAC + 1 */
 382         rbspi_network_setup(flags, 0, 1);
 383
 384         ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
 385
 386         /* mAP lite has a single reset button as gpio 16 */
 387         ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
 388                                         ARRAY_SIZE(rbspi_gpio_keys_reset16),
 389                                         rbspi_gpio_keys_reset16);
 390
 391         /* clear internal multiplexing */
 392         ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
 393         ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
 394 }
 395
 396 /*
 397  * Init the hAP lite hardware.
 398  * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
 399  * being assigned to LAN on the casing, and port 1 being assigned
 400  * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
 401  * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
 402  */
 403 static void __init rbhapl_setup(void)
 404 {
 405         u32 flags = RBSPI_HAS_WLAN;
 406
 407         if (rbspi_platform_setup())
 408                 return;
 409
 410         rbspi_peripherals_setup(flags);
 411
 412         /* GMAC1 is HW MAC, WLAN MAC is HW MAC + 4 */
 413         rbspi_network_setup(flags, 0, 4);
 414
 415         ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
 416
 417         /* hAP lite has a single reset button as gpio 16 */
 418         ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
 419                                         ARRAY_SIZE(rbspi_gpio_keys_reset16),
 420                                         rbspi_gpio_keys_reset16);
 421 }
 422
 423 /*
 424  * The hAP, hEX lite and hEX PoE lite share the same platform
 425  */
 426 static void __init rbspi_952_750r2_setup(u32 flags)
 427 {
 428         if (flags & RBSPI_HAS_SSR)
 429                 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
 430
 431         rbspi_peripherals_setup(flags);
 432
 433         /* GMAC1 is HW MAC + 1, WLAN MAC IS HW MAC + 5 */
 434         rbspi_network_setup(flags, 1, 5);
 435
 436         if (flags & RBSPI_HAS_USB)
 437                 gpio_request_one(RB952_GPIO_USB_POWER,
 438                                 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
 439                                 "USB power");
 440
 441         if (flags & RBSPI_HAS_POE)
 442                 gpio_request_one(RB952_GPIO_POE_POWER,
 443                                 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
 444                                 "POE power");
 445
 446         ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
 447
 448         /* These devices have a single reset button as gpio 16 */
 449         ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
 450                                         ARRAY_SIZE(rbspi_gpio_keys_reset16),
 451                                         rbspi_gpio_keys_reset16);
 452 }
 453
 454 /*
 455  * Init the hAP hardware.
 456  * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
 457  * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
 458  * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
 459  * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
 460  * internal switch for the LAN ports.
 461  * The device also has USB, PoE output and an SSR used for LED multiplexing.
 462  */
 463 static void __init rb952_setup(void)
 464 {
 465         u32 flags = RBSPI_HAS_WLAN | RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
 466                         RBSPI_HAS_SSR | RBSPI_HAS_POE;
 467
 468         if (rbspi_platform_setup())
 469                 return;
 470
 471         rbspi_952_750r2_setup(flags);
 472 }
 473
 474 /*
 475  * Init the hEX PoE lite hardware.
 476  * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
 477  * WLAN.
 478  */
 479 static void __init rb750upr2_setup(void)
 480 {
 481         u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
 482                         RBSPI_HAS_SSR | RBSPI_HAS_POE;
 483
 484         if (rbspi_platform_setup())
 485                 return;
 486
 487         rbspi_952_750r2_setup(flags);
 488 }
 489
 490 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
 491 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
 492 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
 493 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);