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ar71xx: fix section mismatches
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 952Ui-5ac2nD
8 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
9 * - MikroTik RouterBOARD 750UP r2
10 * - MikroTik RouterBOARD 750 r2
11 * - MikroTik RouterBOARD LHG 5nD
12 *
13 * Preliminary support for the following hardware
14 * - MikroTik RouterBOARD wAP2nD
15 * - MikroTik RouterBOARD cAP2nD
16 * - MikroTik RouterBOARD mAP2nD
17 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
18 * hardware as the mAP L-2nD. It is unknown if they share the same board
19 * identifier.
20 *
21 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
22 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
23 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License version 2 as published
27 * by the Free Software Foundation.
28 */
29
30 #include <linux/pci.h>
31 #include <linux/platform_device.h>
32 #include <linux/phy.h>
33 #include <linux/routerboot.h>
34 #include <linux/gpio.h>
35
36 #include <linux/spi/spi.h>
37 #include <linux/spi/74x164.h>
38
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/partitions.h>
41
42 #include <linux/ar8216_platform.h>
43
44 #include <asm/prom.h>
45 #include <asm/mach-ath79/ar71xx_regs.h>
46 #include <asm/mach-ath79/ath79.h>
47
48 #include "common.h"
49 #include "dev-eth.h"
50 #include "dev-spi.h"
51 #include "dev-gpio-buttons.h"
52 #include "dev-leds-gpio.h"
53 #include "dev-m25p80.h"
54 #include "dev-usb.h"
55 #include "dev-wmac.h"
56 #include "machtypes.h"
57 #include "pci.h"
58 #include "routerboot.h"
59
60 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
61 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
62
63 #define RBSPI_HAS_USB BIT(0)
64 #define RBSPI_HAS_WLAN0 BIT(1)
65 #define RBSPI_HAS_WLAN1 BIT(2)
66 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
67 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
68 #define RBSPI_HAS_POE BIT(5)
69 #define RBSPI_HAS_MDIO1 BIT(6)
70 #define RBSPI_HAS_PCI BIT(7)
71
72 #define RB_ROUTERBOOT_OFFSET 0x0000
73 #define RB_BIOS_SIZE 0x1000
74 #define RB_SOFT_CFG_SIZE 0x1000
75
76 /* Flash partitions indexes */
77 enum {
78 RBSPI_PART_RBOOT,
79 RBSPI_PART_HCONF,
80 RBSPI_PART_BIOS,
81 RBSPI_PART_RBOOT2,
82 RBSPI_PART_SCONF,
83 RBSPI_PART_FIRMW,
84 RBSPI_PARTS
85 };
86
87 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
88
89 /*
90 * Setup the SPI flash partition table based on initial parsing.
91 * The kernel can be at any aligned position and have any size.
92 */
93 static void __init rbspi_init_partitions(const struct rb_info *info)
94 {
95 struct mtd_partition *parts = rbspi_spi_partitions;
96 memset(parts, 0x0, sizeof(*parts));
97
98 parts[RBSPI_PART_RBOOT].name = "routerboot";
99 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
100 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
101 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
102
103 parts[RBSPI_PART_HCONF].name = "hard_config";
104 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
105 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
106 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
107
108 parts[RBSPI_PART_BIOS].name = "bios";
109 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
110 + info->hard_cfg_size;
111 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
112 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
113
114 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
115 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
116 + RB_BIOS_SIZE;
117 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
118 - parts[RBSPI_PART_RBOOT2].offset;
119 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
120
121 parts[RBSPI_PART_SCONF].name = "soft_config";
122 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
123 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
124
125 parts[RBSPI_PART_FIRMW].name = "firmware";
126 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
127 + parts[RBSPI_PART_SCONF].size;
128 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
129 }
130
131 static struct flash_platform_data rbspi_spi_flash_data = {
132 .parts = rbspi_spi_partitions,
133 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
134 };
135
136 /* Several boards only have a single reset button wired to GPIO 16 */
137 #define RBSPI_GPIO_BTN_RESET16 16
138 #define RBSPI_GPIO_BTN_RESET20 20
139
140 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
141 {
142 .desc = "Reset button",
143 .type = EV_KEY,
144 .code = KEY_RESTART,
145 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
146 .gpio = RBSPI_GPIO_BTN_RESET16,
147 .active_low = 1,
148 },
149 };
150
151 static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = {
152 {
153 .desc = "Reset button",
154 .type = EV_KEY,
155 .code = KEY_RESTART,
156 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
157 .gpio = RBSPI_GPIO_BTN_RESET20,
158 .active_low = 1,
159 },
160 };
161
162 /* RB mAP L-2nD gpios */
163 #define RBMAPL_GPIO_LED_POWER 17
164 #define RBMAPL_GPIO_LED_USER 14
165 #define RBMAPL_GPIO_LED_ETH 4
166 #define RBMAPL_GPIO_LED_WLAN 11
167
168 static struct gpio_led rbmapl_leds[] __initdata = {
169 {
170 .name = "rb:green:power",
171 .gpio = RBMAPL_GPIO_LED_POWER,
172 .active_low = 0,
173 .default_state = LEDS_GPIO_DEFSTATE_ON,
174 }, {
175 .name = "rb:green:user",
176 .gpio = RBMAPL_GPIO_LED_USER,
177 .active_low = 0,
178 }, {
179 .name = "rb:green:eth",
180 .gpio = RBMAPL_GPIO_LED_ETH,
181 .active_low = 0,
182 }, {
183 .name = "rb:green:wlan",
184 .gpio = RBMAPL_GPIO_LED_WLAN,
185 .active_low = 0,
186 },
187 };
188
189 /* RB 941L-2nD gpios */
190 #define RBHAPL_GPIO_LED_USER 14
191 static struct gpio_led rbhapl_leds[] __initdata = {
192 {
193 .name = "rb:green:user",
194 .gpio = RBHAPL_GPIO_LED_USER,
195 .active_low = 1,
196 },
197 };
198
199 /* common RB SSRs */
200 #define RBSPI_SSR_GPIO_BASE 40
201 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
202
203 /* RB 951Ui-2nD gpios */
204 #define RB952_SSR_BIT_LED_LAN1 0
205 #define RB952_SSR_BIT_LED_LAN2 1
206 #define RB952_SSR_BIT_LED_LAN3 2
207 #define RB952_SSR_BIT_LED_LAN4 3
208 #define RB952_SSR_BIT_LED_LAN5 4
209 #define RB952_SSR_BIT_USB_POWER 5
210 #define RB952_SSR_BIT_LED_WLAN 6
211 #define RB952_GPIO_SSR_CS 11
212 #define RB952_GPIO_LED_USER 4
213 #define RB952_GPIO_POE_POWER 14
214 #define RB952_GPIO_POE_STATUS 12
215 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
216 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
217 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
218 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
219 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
220 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
221 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
222
223 static struct gpio_led rb952_leds[] __initdata = {
224 {
225 .name = "rb:green:user",
226 .gpio = RB952_GPIO_LED_USER,
227 .active_low = 0,
228 }, {
229 .name = "rb:blue:wlan",
230 .gpio = RB952_GPIO_LED_WLAN,
231 .active_low = 1,
232 }, {
233 .name = "rb:green:port1",
234 .gpio = RB952_GPIO_LED_LAN1,
235 .active_low = 1,
236 }, {
237 .name = "rb:green:port2",
238 .gpio = RB952_GPIO_LED_LAN2,
239 .active_low = 1,
240 }, {
241 .name = "rb:green:port3",
242 .gpio = RB952_GPIO_LED_LAN3,
243 .active_low = 1,
244 }, {
245 .name = "rb:green:port4",
246 .gpio = RB952_GPIO_LED_LAN4,
247 .active_low = 1,
248 }, {
249 .name = "rb:green:port5",
250 .gpio = RB952_GPIO_LED_LAN5,
251 .active_low = 1,
252 },
253 };
254
255
256 /* RB 962UiGS-5HacT2HnT gpios */
257 #define RB962_GPIO_POE_STATUS 2
258 #define RB962_GPIO_POE_POWER 3
259 #define RB962_GPIO_LED_USER 12
260 #define RB962_GPIO_USB_POWER 13
261
262 static struct gpio_led rb962_leds_gpio[] __initdata = {
263 {
264 .name = "rb:green:user",
265 .gpio = RB962_GPIO_LED_USER,
266 .active_low = 1,
267 },
268 };
269
270 static const struct ar8327_led_info rb962_leds_ar8327[] = {
271 AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"),
272 AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"),
273 AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"),
274 AR8327_LED_INFO(PHY3_0, HW, "rb:green:port4"),
275 AR8327_LED_INFO(PHY4_0, HW, "rb:green:port5"),
276 };
277
278 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg = {
279 .mode = AR8327_PAD_MAC_RGMII,
280 .txclk_delay_en = true,
281 .rxclk_delay_en = true,
282 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
283 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
284 .mac06_exchange_dis = true,
285 };
286
287 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg = {
288 /* Use SGMII interface for GMAC6 of the AR8337 switch */
289 .mode = AR8327_PAD_MAC_SGMII,
290 .rxclk_delay_en = true,
291 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
292 };
293
294 static struct ar8327_led_cfg rb962_ar8327_led_cfg = {
295 .led_ctrl0 = 0xc737c737,
296 .led_ctrl1 = 0x00000000,
297 .led_ctrl2 = 0x00000000,
298 .led_ctrl3 = 0x0030c300,
299 .open_drain = false,
300 };
301
302 static struct ar8327_platform_data rb962_ar8327_data = {
303 .pad0_cfg = &rb962_ar8327_pad0_cfg,
304 .pad6_cfg = &rb962_ar8327_pad6_cfg,
305 .port0_cfg = {
306 .force_link = 1,
307 .speed = AR8327_PORT_SPEED_1000,
308 .duplex = 1,
309 .txpause = 1,
310 .rxpause = 1,
311 },
312 .port6_cfg = {
313 .force_link = 1,
314 .speed = AR8327_PORT_SPEED_1000,
315 .duplex = 1,
316 .txpause = 1,
317 .rxpause = 1,
318 },
319 .led_cfg = &rb962_ar8327_led_cfg,
320 .num_leds = ARRAY_SIZE(rb962_leds_ar8327),
321 .leds = rb962_leds_ar8327,
322 };
323
324 static struct mdio_board_info rb962_mdio0_info[] = {
325 {
326 .bus_id = "ag71xx-mdio.0",
327 .phy_addr = 0,
328 .platform_data = &rb962_ar8327_data,
329 },
330 };
331
332 /* RB wAP-2nD gpios */
333 #define RBWAP_GPIO_LED_USER 14
334 #define RBWAP_GPIO_LED_WLAN 11
335
336 static struct gpio_led rbwap_leds[] __initdata = {
337 {
338 .name = "rb:green:user",
339 .gpio = RBWAP_GPIO_LED_USER,
340 .active_low = 1,
341 }, {
342 .name = "rb:green:wlan",
343 .gpio = RBWAP_GPIO_LED_WLAN,
344 .active_low = 1,
345 },
346 };
347
348 /* RB cAP-2nD gpios */
349 #define RBCAP_GPIO_LED_1 14
350 #define RBCAP_GPIO_LED_2 12
351 #define RBCAP_GPIO_LED_3 11
352 #define RBCAP_GPIO_LED_4 4
353 #define RBCAP_GPIO_LED_ALL 13
354
355 static struct gpio_led rbcap_leds[] __initdata = {
356 {
357 .name = "rb:green:rssi1",
358 .gpio = RBCAP_GPIO_LED_1,
359 .active_low = 1,
360 }, {
361 .name = "rb:green:rssi2",
362 .gpio = RBCAP_GPIO_LED_2,
363 .active_low = 1,
364 }, {
365 .name = "rb:green:rssi3",
366 .gpio = RBCAP_GPIO_LED_3,
367 .active_low = 1,
368 }, {
369 .name = "rb:green:rssi4",
370 .gpio = RBCAP_GPIO_LED_4,
371 .active_low = 1,
372 },
373 };
374
375 /* RB mAP-2nD gpios */
376 #define RBMAP_SSR_BIT_LED_LAN1 0
377 #define RBMAP_SSR_BIT_LED_LAN2 1
378 #define RBMAP_SSR_BIT_LED_POEO 2
379 #define RBMAP_SSR_BIT_LED_USER 3
380 #define RBMAP_SSR_BIT_LED_WLAN 4
381 #define RBMAP_SSR_BIT_USB_POWER 5
382 #define RBMAP_SSR_BIT_LED_APCAP 6
383 #define RBMAP_GPIO_SSR_CS 11
384 #define RBMAP_GPIO_LED_POWER 4
385 #define RBMAP_GPIO_POE_POWER 14
386 #define RBMAP_GPIO_POE_STATUS 12
387 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
388 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
389 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
390 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
391 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
392 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
393 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
394
395 static struct gpio_led rbmap_leds[] __initdata = {
396 {
397 .name = "rb:green:power",
398 .gpio = RBMAP_GPIO_LED_POWER,
399 .active_low = 1,
400 .default_state = LEDS_GPIO_DEFSTATE_ON,
401 }, {
402 .name = "rb:green:eth1",
403 .gpio = RBMAP_GPIO_LED_LAN1,
404 .active_low = 1,
405 }, {
406 .name = "rb:green:eth2",
407 .gpio = RBMAP_GPIO_LED_WLAN,
408 .active_low = 1,
409 }, {
410 .name = "rb:red:poe_out",
411 .gpio = RBMAP_GPIO_LED_POEO,
412 .active_low = 1,
413 }, {
414 .name = "rb:green:user",
415 .gpio = RBMAP_GPIO_LED_USER,
416 .active_low = 1,
417 }, {
418 .name = "rb:green:wlan",
419 .gpio = RBMAP_GPIO_LED_WLAN,
420 .active_low = 1,
421 }, {
422 .name = "rb:green:ap_cap",
423 .gpio = RBMAP_GPIO_LED_APCAP,
424 .active_low = 1,
425 },
426 };
427
428 /* RB LHG 5nD gpios */
429 #define RBLHG_GPIO_LED_0 13
430 #define RBLHG_GPIO_LED_1 12
431 #define RBLHG_GPIO_LED_2 4
432 #define RBLHG_GPIO_LED_3 21
433 #define RBLHG_GPIO_LED_4 18
434 #define RBLHG_GPIO_LED_ETH 14
435 #define RBLHG_GPIO_LED_POWER 11
436 #define RBLHG_GPIO_LED_USER 20
437 #define RBLHG_GPIO_BTN_RESET 15
438
439 static struct gpio_led rblhg_leds[] __initdata = {
440 {
441 .name = "rb:green:rssi0",
442 .gpio = RBLHG_GPIO_LED_0,
443 .active_low = 1,
444 }, {
445 .name = "rb:green:rssi1",
446 .gpio = RBLHG_GPIO_LED_1,
447 .active_low = 1,
448 }, {
449 .name = "rb:green:rssi2",
450 .gpio = RBLHG_GPIO_LED_2,
451 .active_low = 1,
452 }, {
453 .name = "rb:green:rssi3",
454 .gpio = RBLHG_GPIO_LED_3,
455 .active_low = 1,
456 }, {
457 .name = "rb:green:rssi4",
458 .gpio = RBLHG_GPIO_LED_4,
459 .active_low = 1,
460 }, {
461 .name = "rb:green:eth",
462 .gpio = RBLHG_GPIO_LED_ETH,
463 .active_low = 1,
464 }, {
465 .name = "rb:green:user",
466 .gpio = RBLHG_GPIO_LED_USER,
467 .active_low = 1,
468 }, {
469 .name = "rb:blue:power",
470 .gpio = RBLHG_GPIO_LED_POWER,
471 .active_low = 0,
472 .default_state = LEDS_GPIO_DEFSTATE_ON,
473 },
474 };
475
476 static struct gpio_keys_button rblhg_gpio_keys[] __initdata = {
477 {
478 .desc = "Reset button",
479 .type = EV_KEY,
480 .code = KEY_RESTART,
481 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
482 .gpio = RBLHG_GPIO_BTN_RESET,
483 .active_low = 1,
484 },
485 };
486
487
488 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
489 .base = RBSPI_SSR_GPIO_BASE,
490 };
491
492 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
493 static int rbspi_spi_cs_gpios[] = {
494 -ENOENT, /* CS0 is always -ENOENT: natively handled */
495 -ENOENT, /* CS1 can be updated by the code as necessary */
496 };
497
498 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
499 .bus_num = 0,
500 .cs_gpios = rbspi_spi_cs_gpios,
501 };
502
503 /*
504 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
505 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
506 */
507 static struct spi_board_info rbspi_spi_info[] = {
508 {
509 .bus_num = 0,
510 .chip_select = 0,
511 .max_speed_hz = 25000000,
512 .modalias = "m25p80",
513 .platform_data = &rbspi_spi_flash_data,
514 }, {
515 .bus_num = 0,
516 .chip_select = 1,
517 .max_speed_hz = 25000000,
518 .modalias = "74x164",
519 .platform_data = &rbspi_ssr_data,
520 }
521 };
522
523 void __init rbspi_wlan_init(u16 id, int wmac_offset)
524 {
525 char *art_buf;
526 u8 wlan_mac[ETH_ALEN];
527
528 art_buf = rb_get_ext_wlan_data(id);
529 if (!art_buf)
530 return;
531
532 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
533 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
534
535 kfree(art_buf);
536 }
537
538 #define RBSPI_MACH_BUFLEN 64
539 /*
540 * Common platform init routine for all SPI NOR devices.
541 */
542 static int __init rbspi_platform_setup(void)
543 {
544 const struct rb_info *info;
545 char buf[RBSPI_MACH_BUFLEN] = "MikroTik ";
546 char *str;
547 int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1;
548
549 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
550 if (!info)
551 return -ENODEV;
552
553 if (info->board_name) {
554 str = "RouterBOARD ";
555 if (strncmp(info->board_name, str, strlen(str))) {
556 strncat(buf, str, len);
557 len -= strlen(str);
558 }
559 strncat(buf, info->board_name, len);
560 }
561 else
562 strncat(buf, "UNKNOWN", len);
563
564 mips_set_machine_name(buf);
565
566 /* fix partitions based on flash parsing */
567 rbspi_init_partitions(info);
568
569 return 0;
570 }
571
572 /*
573 * Common peripherals init routine for all SPI NOR devices.
574 * Sets SPI and USB.
575 */
576 static void __init rbspi_peripherals_setup(u32 flags)
577 {
578 unsigned spi_n;
579
580 if (flags & RBSPI_HAS_SSR)
581 spi_n = ARRAY_SIZE(rbspi_spi_info);
582 else
583 spi_n = 1; /* only one device on bus0 */
584
585 rbspi_ath79_spi_data.num_chipselect = spi_n;
586 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
587 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
588
589 if (flags & RBSPI_HAS_USB)
590 ath79_register_usb();
591
592 if (flags & RBSPI_HAS_PCI)
593 ath79_register_pci();
594 }
595
596 /*
597 * Common network init routine for all SPI NOR devices.
598 * Sets LAN/WAN/WLAN.
599 */
600 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
601 int wmac0_offset, int wmac1_offset)
602 {
603 /* for QCA953x that will init mdio1_device/data */
604 ath79_register_mdio(0, 0x0);
605 if (flags & RBSPI_HAS_MDIO1)
606 ath79_register_mdio(1, 0x0);
607
608 if (flags & RBSPI_HAS_WAN4) {
609 ath79_setup_ar934x_eth_cfg(0);
610
611 /* set switch to oper mode 1, PHY4 connected to CPU */
612 ath79_switch_data.phy4_mii_en = 1;
613 ath79_switch_data.phy_poll_mask |= BIT(4);
614
615 /* init GMAC0 connected to PHY4 at 100M */
616 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
617 ath79_eth0_data.phy_mask = BIT(4);
618 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
619 ath79_register_eth(0);
620 } else {
621 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
622 * to the internal switch.
623 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
624 * the QCA953x, this works because this configuration bit is
625 * the same as the AR934x. There's no equivalent function for
626 * QCA953x for now. */
627 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
628 }
629
630 /* init GMAC1 */
631 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
632 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
633 ath79_register_eth(1);
634
635 if (flags & RBSPI_HAS_WLAN0)
636 rbspi_wlan_init(0, wmac0_offset);
637
638 if (flags & RBSPI_HAS_WLAN1)
639 rbspi_wlan_init(1, wmac1_offset);
640 }
641
642 /*
643 * Init the mAP lite hardware (QCA953x).
644 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
645 * Trying to use GMAC0 in direct mode was unsucessful, so we're
646 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
647 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
648 */
649 static void __init rbmapl_setup(void)
650 {
651 u32 flags = RBSPI_HAS_WLAN0;
652
653 if (rbspi_platform_setup())
654 return;
655
656 rbspi_peripherals_setup(flags);
657
658 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
659 rbspi_network_setup(flags, 0, 1, 0);
660
661 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
662
663 /* mAP lite has a single reset button as gpio 16 */
664 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
665 ARRAY_SIZE(rbspi_gpio_keys_reset16),
666 rbspi_gpio_keys_reset16);
667
668 /* clear internal multiplexing */
669 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
670 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
671 }
672
673 /*
674 * Init the hAP lite hardware (QCA953x).
675 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
676 * being assigned to LAN on the casing, and port 1 being assigned
677 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
678 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
679 */
680 static void __init rbhapl_setup(void)
681 {
682 u32 flags = RBSPI_HAS_WLAN0;
683
684 if (rbspi_platform_setup())
685 return;
686
687 rbspi_peripherals_setup(flags);
688
689 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
690 rbspi_network_setup(flags, 0, 4, 0);
691
692 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
693
694 /* hAP lite has a single reset button as gpio 16 */
695 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
696 ARRAY_SIZE(rbspi_gpio_keys_reset16),
697 rbspi_gpio_keys_reset16);
698 }
699
700 /*
701 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
702 */
703 static void __init rbspi_952_750r2_setup(u32 flags)
704 {
705 if (flags & RBSPI_HAS_SSR)
706 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
707
708 rbspi_peripherals_setup(flags);
709
710 /*
711 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
712 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
713 */
714 rbspi_network_setup(flags, 1, 5, 6);
715
716 if (flags & RBSPI_HAS_USB)
717 gpio_request_one(RB952_GPIO_USB_POWER,
718 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
719 "USB power");
720
721 if (flags & RBSPI_HAS_POE)
722 gpio_request_one(RB952_GPIO_POE_POWER,
723 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
724 "POE power");
725
726 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
727
728 /* These devices have a single reset button as gpio 16 */
729 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
730 ARRAY_SIZE(rbspi_gpio_keys_reset16),
731 rbspi_gpio_keys_reset16);
732 }
733
734 /*
735 * Init the hAP (ac lite) hardware (QCA953x).
736 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
737 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
738 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
739 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
740 * internal switch for the LAN ports.
741 * The device also has USB, PoE output and an SSR used for LED multiplexing.
742 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
743 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
744 */
745 static void __init rb952_setup(void)
746 {
747 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
748 RBSPI_HAS_SSR | RBSPI_HAS_POE;
749
750 if (rbspi_platform_setup())
751 return;
752
753 /* differentiate the hAP from the hAP ac lite */
754 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
755 flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI;
756 else
757 flags |= RBSPI_HAS_WLAN0;
758
759 rbspi_952_750r2_setup(flags);
760 }
761
762 /*
763 * Init the hEX (PoE) lite hardware (QCA953x).
764 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
765 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
766 * without USB and POE. It shares the same bootloader board identifier.
767 */
768 static void __init rb750upr2_setup(void)
769 {
770 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
771
772 if (rbspi_platform_setup())
773 return;
774
775 /* differentiate the hEX lite from the hEX PoE lite */
776 if (strstr(mips_get_machine_name(), "750UP r2"))
777 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
778
779 rbspi_952_750r2_setup(flags);
780 }
781
782 /*
783 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
784 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
785 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
786 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
787 * The SFP cage is not assigned by default on RouterOS. Extra work is required
788 * to support this interface as it is directly connected to the SoC (eth1).
789 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
790 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
791 * they are not attached to GPIOs, extra work is required to support these.
792 * PoE and USB output power control is supported.
793 */
794 static void __init rb962_setup(void)
795 {
796 u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI;
797
798 if (rbspi_platform_setup())
799 return;
800
801 rbspi_peripherals_setup(flags);
802
803 /* Do not call rbspi_network_setup as we have a discrete switch chip */
804 ath79_eth0_pll_data.pll_1000 = 0xae000000;
805 ath79_eth0_pll_data.pll_100 = 0xa0000101;
806 ath79_eth0_pll_data.pll_10 = 0xa0001313;
807
808 ath79_register_mdio(0, 0x0);
809 mdiobus_register_board_info(rb962_mdio0_info,
810 ARRAY_SIZE(rb962_mdio0_info));
811
812 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
813
814 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
815 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
816 ath79_eth0_data.phy_mask = BIT(0);
817 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
818 ath79_register_eth(0);
819
820 /* WLAN1 MAC is HW MAC + 7 */
821 rbspi_wlan_init(1, 7);
822
823 if (flags & RBSPI_HAS_USB)
824 gpio_request_one(RB962_GPIO_USB_POWER,
825 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
826 "USB power");
827
828 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
829 if (flags & RBSPI_HAS_POE)
830 gpio_request_one(RB962_GPIO_POE_POWER,
831 GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
832 GPIOF_EXPORT_DIR_FIXED,
833 "POE power");
834
835 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio),
836 rb962_leds_gpio);
837
838 /* This device has a single reset button as gpio 20 */
839 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
840 ARRAY_SIZE(rbspi_gpio_keys_reset20),
841 rbspi_gpio_keys_reset20);
842 }
843
844 /*
845 * Init the LHG hardware (AR9344).
846 * The LHG 5nD has a single ethernet port connected to PHY0.
847 * Wireless is provided via 5GHz WLAN1.
848 */
849 static void __init rblhg_setup(void)
850 {
851 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
852
853 if (rbspi_platform_setup())
854 return;
855
856 rbspi_peripherals_setup(flags);
857
858 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
859 rbspi_network_setup(flags, 0, 0, 1);
860
861 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
862
863 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
864 ARRAY_SIZE(rblhg_gpio_keys),
865 rblhg_gpio_keys);
866 }
867
868 /*
869 * Init the wAP hardware (EXPERIMENTAL).
870 * The wAP 2nD has a single ethernet port.
871 */
872 static void __init rbwap_setup(void)
873 {
874 u32 flags = RBSPI_HAS_WLAN0;
875
876 if (rbspi_platform_setup())
877 return;
878
879 rbspi_peripherals_setup(flags);
880
881 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
882 rbspi_network_setup(flags, 0, 1, 0);
883
884 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
885 }
886
887 /*
888 * Init the cAP hardware (EXPERIMENTAL).
889 * The cAP 2nD has a single ethernet port, and a global LED switch.
890 */
891 static void __init rbcap_setup(void)
892 {
893 u32 flags = RBSPI_HAS_WLAN0;
894
895 if (rbspi_platform_setup())
896 return;
897
898 rbspi_peripherals_setup(flags);
899
900 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
901 rbspi_network_setup(flags, 0, 1, 0);
902
903 gpio_request_one(RBCAP_GPIO_LED_ALL,
904 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
905 "LEDs enable");
906
907 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
908 }
909
910 /*
911 * Init the mAP hardware (EXPERIMENTAL).
912 * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED
913 * multiplexing.
914 */
915 static void __init rbmap_setup(void)
916 {
917 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_SSR | RBSPI_HAS_POE;
918
919 if (rbspi_platform_setup())
920 return;
921
922 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
923 rbspi_peripherals_setup(flags);
924
925 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
926 rbspi_network_setup(flags, 0, 2, 0);
927
928 if (flags & RBSPI_HAS_POE)
929 gpio_request_one(RBMAP_GPIO_POE_POWER,
930 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
931 "POE power");
932
933 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
934 }
935
936
937 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
938 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
939 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
940 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962, "962", rb962_setup);
941 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
942 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
943 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
944 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
945 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);
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