ar71xx: mikrotik: prepend "RouterBOARD" to machine name for NOR devices
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 750UP r2
8 * - MikroTik RouterBOARD 750 r2
9 * - MikroTik RouterBOARD LHG 5nD
10 *
11 * Preliminary support for the following hardware
12 * - MikroTik RouterBOARD wAP2nD
13 * - MikroTik RouterBOARD cAP2nD
14 * - MikroTik RouterBOARD mAP2nD
15 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
16 * hardware as the mAP L-2nD. It is unknown if they share the same board
17 * identifier.
18 *
19 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License version 2 as published
23 * by the Free Software Foundation.
24 */
25
26 #include <linux/platform_device.h>
27 #include <linux/phy.h>
28 #include <linux/routerboot.h>
29 #include <linux/gpio.h>
30
31 #include <linux/spi/spi.h>
32 #include <linux/spi/74x164.h>
33
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/partitions.h>
36
37 #include <asm/prom.h>
38 #include <asm/mach-ath79/ar71xx_regs.h>
39 #include <asm/mach-ath79/ath79.h>
40
41 #include "common.h"
42 #include "dev-eth.h"
43 #include "dev-spi.h"
44 #include "dev-gpio-buttons.h"
45 #include "dev-leds-gpio.h"
46 #include "dev-m25p80.h"
47 #include "dev-usb.h"
48 #include "dev-wmac.h"
49 #include "machtypes.h"
50 #include "routerboot.h"
51
52 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
53 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
54
55 #define RBSPI_HAS_USB BIT(0)
56 #define RBSPI_HAS_WLAN0 BIT(1)
57 #define RBSPI_HAS_WLAN1 BIT(2)
58 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
59 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
60 #define RBSPI_HAS_POE BIT(5)
61 #define RBSPI_HAS_MDIO1 BIT(6)
62
63 #define RB_ROUTERBOOT_OFFSET 0x0000
64 #define RB_BIOS_SIZE 0x1000
65 #define RB_SOFT_CFG_SIZE 0x1000
66
67 /* Flash partitions indexes */
68 enum {
69 RBSPI_PART_RBOOT,
70 RBSPI_PART_HCONF,
71 RBSPI_PART_BIOS,
72 RBSPI_PART_RBOOT2,
73 RBSPI_PART_SCONF,
74 RBSPI_PART_FIRMW,
75 RBSPI_PARTS
76 };
77
78 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
79
80 /*
81 * Setup the SPI flash partition table based on initial parsing.
82 * The kernel can be at any aligned position and have any size.
83 */
84 static void __init rbspi_init_partitions(const struct rb_info *info)
85 {
86 struct mtd_partition *parts = rbspi_spi_partitions;
87 memset(parts, 0x0, sizeof(*parts));
88
89 parts[RBSPI_PART_RBOOT].name = "routerboot";
90 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
91 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
92 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
93
94 parts[RBSPI_PART_HCONF].name = "hard_config";
95 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
96 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
97 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
98
99 parts[RBSPI_PART_BIOS].name = "bios";
100 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
101 + info->hard_cfg_size;
102 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
103 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
104
105 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
106 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
107 + RB_BIOS_SIZE;
108 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
109 - parts[RBSPI_PART_RBOOT2].offset;
110 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
111
112 parts[RBSPI_PART_SCONF].name = "soft_config";
113 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
114 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
115
116 parts[RBSPI_PART_FIRMW].name = "firmware";
117 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
118 + parts[RBSPI_PART_SCONF].size;
119 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
120 }
121
122 static struct flash_platform_data rbspi_spi_flash_data = {
123 .parts = rbspi_spi_partitions,
124 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
125 };
126
127 /* Several boards only have a single reset button wired to GPIO 16 */
128 #define RBSPI_GPIO_BTN_RESET16 16
129
130 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
131 {
132 .desc = "Reset button",
133 .type = EV_KEY,
134 .code = KEY_RESTART,
135 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
136 .gpio = RBSPI_GPIO_BTN_RESET16,
137 .active_low = 1,
138 },
139 };
140
141 /* RB mAP L-2nD gpios */
142 #define RBMAPL_GPIO_LED_POWER 17
143 #define RBMAPL_GPIO_LED_USER 14
144 #define RBMAPL_GPIO_LED_ETH 4
145 #define RBMAPL_GPIO_LED_WLAN 11
146
147 static struct gpio_led rbmapl_leds[] __initdata = {
148 {
149 .name = "rb:green:power",
150 .gpio = RBMAPL_GPIO_LED_POWER,
151 .active_low = 0,
152 .default_state = LEDS_GPIO_DEFSTATE_ON,
153 }, {
154 .name = "rb:green:user",
155 .gpio = RBMAPL_GPIO_LED_USER,
156 .active_low = 0,
157 }, {
158 .name = "rb:green:eth",
159 .gpio = RBMAPL_GPIO_LED_ETH,
160 .active_low = 0,
161 }, {
162 .name = "rb:green:wlan",
163 .gpio = RBMAPL_GPIO_LED_WLAN,
164 .active_low = 0,
165 },
166 };
167
168 /* RB 941L-2nD gpios */
169 #define RBHAPL_GPIO_LED_USER 14
170 static struct gpio_led rbhapl_leds[] __initdata = {
171 {
172 .name = "rb:green:user",
173 .gpio = RBHAPL_GPIO_LED_USER,
174 .active_low = 1,
175 },
176 };
177
178 /* common RB SSRs */
179 #define RBSPI_SSR_GPIO_BASE 40
180 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
181
182 /* RB 951Ui-2nD gpios */
183 #define RB952_SSR_BIT_LED_LAN1 0
184 #define RB952_SSR_BIT_LED_LAN2 1
185 #define RB952_SSR_BIT_LED_LAN3 2
186 #define RB952_SSR_BIT_LED_LAN4 3
187 #define RB952_SSR_BIT_LED_LAN5 4
188 #define RB952_SSR_BIT_USB_POWER 5
189 #define RB952_SSR_BIT_LED_WLAN 6
190 #define RB952_GPIO_SSR_CS 11
191 #define RB952_GPIO_LED_USER 4
192 #define RB952_GPIO_POE_POWER 14
193 #define RB952_GPIO_POE_STATUS 12
194 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
195 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
196 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
197 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
198 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
199 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
200 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
201
202 static struct gpio_led rb952_leds[] __initdata = {
203 {
204 .name = "rb:green:user",
205 .gpio = RB952_GPIO_LED_USER,
206 .active_low = 0,
207 }, {
208 .name = "rb:blue:wlan",
209 .gpio = RB952_GPIO_LED_WLAN,
210 .active_low = 1,
211 }, {
212 .name = "rb:green:port1",
213 .gpio = RB952_GPIO_LED_LAN1,
214 .active_low = 1,
215 }, {
216 .name = "rb:green:port2",
217 .gpio = RB952_GPIO_LED_LAN2,
218 .active_low = 1,
219 }, {
220 .name = "rb:green:port3",
221 .gpio = RB952_GPIO_LED_LAN3,
222 .active_low = 1,
223 }, {
224 .name = "rb:green:port4",
225 .gpio = RB952_GPIO_LED_LAN4,
226 .active_low = 1,
227 }, {
228 .name = "rb:green:port5",
229 .gpio = RB952_GPIO_LED_LAN5,
230 .active_low = 1,
231 },
232 };
233
234 /* RB wAP-2nD gpios */
235 #define RBWAP_GPIO_LED_USER 14
236 #define RBWAP_GPIO_LED_WLAN 11
237
238 static struct gpio_led rbwap_leds[] __initdata = {
239 {
240 .name = "rb:green:user",
241 .gpio = RBWAP_GPIO_LED_USER,
242 .active_low = 1,
243 }, {
244 .name = "rb:green:wlan",
245 .gpio = RBWAP_GPIO_LED_WLAN,
246 .active_low = 1,
247 },
248 };
249
250 /* RB cAP-2nD gpios */
251 #define RBCAP_GPIO_LED_1 14
252 #define RBCAP_GPIO_LED_2 12
253 #define RBCAP_GPIO_LED_3 11
254 #define RBCAP_GPIO_LED_4 4
255 #define RBCAP_GPIO_LED_ALL 13
256
257 static struct gpio_led rbcap_leds[] __initdata = {
258 {
259 .name = "rb:green:rssi1",
260 .gpio = RBCAP_GPIO_LED_1,
261 .active_low = 1,
262 }, {
263 .name = "rb:green:rssi2",
264 .gpio = RBCAP_GPIO_LED_2,
265 .active_low = 1,
266 }, {
267 .name = "rb:green:rssi3",
268 .gpio = RBCAP_GPIO_LED_3,
269 .active_low = 1,
270 }, {
271 .name = "rb:green:rssi4",
272 .gpio = RBCAP_GPIO_LED_4,
273 .active_low = 1,
274 },
275 };
276
277 /* RB mAP-2nD gpios */
278 #define RBMAP_SSR_BIT_LED_LAN1 0
279 #define RBMAP_SSR_BIT_LED_LAN2 1
280 #define RBMAP_SSR_BIT_LED_POEO 2
281 #define RBMAP_SSR_BIT_LED_USER 3
282 #define RBMAP_SSR_BIT_LED_WLAN 4
283 #define RBMAP_SSR_BIT_USB_POWER 5
284 #define RBMAP_SSR_BIT_LED_APCAP 6
285 #define RBMAP_GPIO_SSR_CS 11
286 #define RBMAP_GPIO_LED_POWER 4
287 #define RBMAP_GPIO_POE_POWER 14
288 #define RBMAP_GPIO_POE_STATUS 12
289 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
290 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
291 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
292 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
293 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
294 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
295 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
296
297 static struct gpio_led rbmap_leds[] __initdata = {
298 {
299 .name = "rb:green:power",
300 .gpio = RBMAP_GPIO_LED_POWER,
301 .active_low = 1,
302 .default_state = LEDS_GPIO_DEFSTATE_ON,
303 }, {
304 .name = "rb:green:eth1",
305 .gpio = RBMAP_GPIO_LED_LAN1,
306 .active_low = 1,
307 }, {
308 .name = "rb:green:eth2",
309 .gpio = RBMAP_GPIO_LED_WLAN,
310 .active_low = 1,
311 }, {
312 .name = "rb:red:poe_out",
313 .gpio = RBMAP_GPIO_LED_POEO,
314 .active_low = 1,
315 }, {
316 .name = "rb:green:user",
317 .gpio = RBMAP_GPIO_LED_USER,
318 .active_low = 1,
319 }, {
320 .name = "rb:green:wlan",
321 .gpio = RBMAP_GPIO_LED_WLAN,
322 .active_low = 1,
323 }, {
324 .name = "rb:green:ap_cap",
325 .gpio = RBMAP_GPIO_LED_APCAP,
326 .active_low = 1,
327 },
328 };
329
330 /* RB LHG 5nD gpios */
331 #define RBLHG_GPIO_LED_0 13
332 #define RBLHG_GPIO_LED_1 12
333 #define RBLHG_GPIO_LED_2 4
334 #define RBLHG_GPIO_LED_3 21
335 #define RBLHG_GPIO_LED_4 18
336 #define RBLHG_GPIO_LED_ETH 14
337 #define RBLHG_GPIO_LED_POWER 11
338 #define RBLHG_GPIO_LED_USER 20
339 #define RBLHG_GPIO_BTN_RESET 15
340
341 static struct gpio_led rblhg_leds[] __initdata = {
342 {
343 .name = "rb:green:rssi0",
344 .gpio = RBLHG_GPIO_LED_0,
345 .active_low = 1,
346 }, {
347 .name = "rb:green:rssi1",
348 .gpio = RBLHG_GPIO_LED_1,
349 .active_low = 1,
350 }, {
351 .name = "rb:green:rssi2",
352 .gpio = RBLHG_GPIO_LED_2,
353 .active_low = 1,
354 }, {
355 .name = "rb:green:rssi3",
356 .gpio = RBLHG_GPIO_LED_3,
357 .active_low = 1,
358 }, {
359 .name = "rb:green:rssi4",
360 .gpio = RBLHG_GPIO_LED_4,
361 .active_low = 1,
362 }, {
363 .name = "rb:green:eth",
364 .gpio = RBLHG_GPIO_LED_ETH,
365 .active_low = 1,
366 }, {
367 .name = "rb:green:user",
368 .gpio = RBLHG_GPIO_LED_USER,
369 .active_low = 1,
370 }, {
371 .name = "rb:blue:power",
372 .gpio = RBLHG_GPIO_LED_POWER,
373 .active_low = 0,
374 .default_state = LEDS_GPIO_DEFSTATE_ON,
375 },
376 };
377
378 static struct gpio_keys_button rblhg_gpio_keys[] __initdata = {
379 {
380 .desc = "Reset button",
381 .type = EV_KEY,
382 .code = KEY_RESTART,
383 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
384 .gpio = RBLHG_GPIO_BTN_RESET,
385 .active_low = 1,
386 },
387 };
388
389
390 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
391 .base = RBSPI_SSR_GPIO_BASE,
392 };
393
394 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
395 static int rbspi_spi_cs_gpios[] = {
396 -ENOENT, /* CS0 is always -ENOENT: natively handled */
397 -ENOENT, /* CS1 can be updated by the code as necessary */
398 };
399
400 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
401 .bus_num = 0,
402 .cs_gpios = rbspi_spi_cs_gpios,
403 };
404
405 /*
406 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
407 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
408 */
409 static struct spi_board_info rbspi_spi_info[] = {
410 {
411 .bus_num = 0,
412 .chip_select = 0,
413 .max_speed_hz = 25000000,
414 .modalias = "m25p80",
415 .platform_data = &rbspi_spi_flash_data,
416 }, {
417 .bus_num = 0,
418 .chip_select = 1,
419 .max_speed_hz = 25000000,
420 .modalias = "74x164",
421 .platform_data = &rbspi_ssr_data,
422 }
423 };
424
425 void __init rbspi_wlan_init(u16 id, int wmac_offset)
426 {
427 char *art_buf;
428 u8 wlan_mac[ETH_ALEN];
429
430 art_buf = rb_get_ext_wlan_data(id);
431 if (!art_buf)
432 return;
433
434 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
435 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
436
437 kfree(art_buf);
438 }
439
440 #define RBSPI_MACH_BUFLEN 64
441 /*
442 * Common platform init routine for all SPI NOR devices.
443 */
444 static int __init rbspi_platform_setup(void)
445 {
446 const struct rb_info *info;
447 char buf[RBSPI_MACH_BUFLEN] = "MikroTik ";
448 char *str;
449 int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1;
450
451 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
452 if (!info)
453 return -ENODEV;
454
455 if (info->board_name) {
456 str = "RouterBOARD ";
457 if (strncmp(info->board_name, str, strlen(str))) {
458 strncat(buf, str, len);
459 len -= strlen(str);
460 }
461 strncat(buf, info->board_name, len);
462 }
463 else
464 strncat(buf, "UNKNOWN", len);
465
466 mips_set_machine_name(buf);
467
468 /* fix partitions based on flash parsing */
469 rbspi_init_partitions(info);
470
471 return 0;
472 }
473
474 /*
475 * Common peripherals init routine for all SPI NOR devices.
476 * Sets SPI and USB.
477 */
478 static void __init rbspi_peripherals_setup(u32 flags)
479 {
480 unsigned spi_n;
481
482 if (flags & RBSPI_HAS_SSR)
483 spi_n = ARRAY_SIZE(rbspi_spi_info);
484 else
485 spi_n = 1; /* only one device on bus0 */
486
487 rbspi_ath79_spi_data.num_chipselect = spi_n;
488 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
489 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
490
491 if (flags & RBSPI_HAS_USB)
492 ath79_register_usb();
493 }
494
495 /*
496 * Common network init routine for all SPI NOR devices.
497 * Sets LAN/WAN/WLAN.
498 */
499 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
500 int wmac0_offset, int wmac1_offset)
501 {
502 /* for QCA953x that will init mdio1_device/data */
503 ath79_register_mdio(0, 0x0);
504 if (flags & RBSPI_HAS_MDIO1)
505 ath79_register_mdio(1, 0x0);
506
507 if (flags & RBSPI_HAS_WAN4) {
508 ath79_setup_ar934x_eth_cfg(0);
509
510 /* set switch to oper mode 1, PHY4 connected to CPU */
511 ath79_switch_data.phy4_mii_en = 1;
512 ath79_switch_data.phy_poll_mask |= BIT(4);
513
514 /* init GMAC0 connected to PHY4 at 100M */
515 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
516 ath79_eth0_data.phy_mask = BIT(4);
517 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
518 ath79_register_eth(0);
519 } else {
520 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
521 * to the internal switch.
522 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
523 * the QCA953x, this works because this configuration bit is
524 * the same as the AR934x. There's no equivalent function for
525 * QCA953x for now. */
526 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
527 }
528
529 /* init GMAC1 */
530 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
531 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
532 ath79_register_eth(1);
533
534 if (flags & RBSPI_HAS_WLAN0)
535 rbspi_wlan_init(0, wmac0_offset);
536
537 if (flags & RBSPI_HAS_WLAN1)
538 rbspi_wlan_init(1, wmac1_offset);
539 }
540
541 /*
542 * Init the mAP lite hardware (QCA953x).
543 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
544 * Trying to use GMAC0 in direct mode was unsucessful, so we're
545 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
546 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
547 */
548 static void __init rbmapl_setup(void)
549 {
550 u32 flags = RBSPI_HAS_WLAN0;
551
552 if (rbspi_platform_setup())
553 return;
554
555 rbspi_peripherals_setup(flags);
556
557 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
558 rbspi_network_setup(flags, 0, 1, 0);
559
560 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
561
562 /* mAP lite has a single reset button as gpio 16 */
563 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
564 ARRAY_SIZE(rbspi_gpio_keys_reset16),
565 rbspi_gpio_keys_reset16);
566
567 /* clear internal multiplexing */
568 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
569 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
570 }
571
572 /*
573 * Init the hAP lite hardware (QCA953x).
574 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
575 * being assigned to LAN on the casing, and port 1 being assigned
576 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
577 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
578 */
579 static void __init rbhapl_setup(void)
580 {
581 u32 flags = RBSPI_HAS_WLAN0;
582
583 if (rbspi_platform_setup())
584 return;
585
586 rbspi_peripherals_setup(flags);
587
588 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
589 rbspi_network_setup(flags, 0, 4, 0);
590
591 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
592
593 /* hAP lite has a single reset button as gpio 16 */
594 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
595 ARRAY_SIZE(rbspi_gpio_keys_reset16),
596 rbspi_gpio_keys_reset16);
597 }
598
599 /*
600 * The hAP, hEX lite and hEX PoE lite share the same platform
601 */
602 static void __init rbspi_952_750r2_setup(u32 flags)
603 {
604 if (flags & RBSPI_HAS_SSR)
605 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
606
607 rbspi_peripherals_setup(flags);
608
609 /* GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 */
610 rbspi_network_setup(flags, 1, 5, 0);
611
612 if (flags & RBSPI_HAS_USB)
613 gpio_request_one(RB952_GPIO_USB_POWER,
614 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
615 "USB power");
616
617 if (flags & RBSPI_HAS_POE)
618 gpio_request_one(RB952_GPIO_POE_POWER,
619 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
620 "POE power");
621
622 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
623
624 /* These devices have a single reset button as gpio 16 */
625 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
626 ARRAY_SIZE(rbspi_gpio_keys_reset16),
627 rbspi_gpio_keys_reset16);
628 }
629
630 /*
631 * Init the hAP hardware (QCA953x).
632 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
633 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
634 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
635 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
636 * internal switch for the LAN ports.
637 * The device also has USB, PoE output and an SSR used for LED multiplexing.
638 */
639 static void __init rb952_setup(void)
640 {
641 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
642 RBSPI_HAS_SSR | RBSPI_HAS_POE;
643
644 if (rbspi_platform_setup())
645 return;
646
647 rbspi_952_750r2_setup(flags);
648 }
649
650 /*
651 * Init the hEX (PoE) lite hardware (QCA953x).
652 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
653 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
654 * without USB and POE. It shares the same bootloader board identifier.
655 */
656 static void __init rb750upr2_setup(void)
657 {
658 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
659
660 if (rbspi_platform_setup())
661 return;
662
663 /* differentiate the hEX lite from the hEX PoE lite */
664 if (strstr(mips_get_machine_name(), "750UP r2"))
665 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
666
667 rbspi_952_750r2_setup(flags);
668 }
669
670 /*
671 * Init the LHG hardware (AR9344).
672 * The LHG 5nD has a single ethernet port connected to PHY0.
673 * Wireless is provided via 5GHz WLAN1.
674 */
675 static void __init rblhg_setup(void)
676 {
677 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
678
679 if (rbspi_platform_setup())
680 return;
681
682 rbspi_peripherals_setup(flags);
683
684 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
685 rbspi_network_setup(flags, 0, 0, 1);
686
687 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
688
689 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
690 ARRAY_SIZE(rblhg_gpio_keys),
691 rblhg_gpio_keys);
692 }
693
694 /*
695 * Init the wAP hardware (EXPERIMENTAL).
696 * The wAP 2nD has a single ethernet port.
697 */
698 static void __init rbwap_setup(void)
699 {
700 u32 flags = RBSPI_HAS_WLAN0;
701
702 if (rbspi_platform_setup())
703 return;
704
705 rbspi_peripherals_setup(flags);
706
707 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
708 rbspi_network_setup(flags, 0, 1, 0);
709
710 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
711 }
712
713 /*
714 * Init the cAP hardware (EXPERIMENTAL).
715 * The cAP 2nD has a single ethernet port, and a global LED switch.
716 */
717 static void __init rbcap_setup(void)
718 {
719 u32 flags = RBSPI_HAS_WLAN0;
720
721 if (rbspi_platform_setup())
722 return;
723
724 rbspi_peripherals_setup(flags);
725
726 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
727 rbspi_network_setup(flags, 0, 1, 0);
728
729 gpio_request_one(RBCAP_GPIO_LED_ALL,
730 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
731 "LEDs enable");
732
733 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
734 }
735
736 /*
737 * Init the mAP hardware (EXPERIMENTAL).
738 * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED
739 * multiplexing.
740 */
741 static void __init rbmap_setup(void)
742 {
743 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_SSR | RBSPI_HAS_POE;
744
745 if (rbspi_platform_setup())
746 return;
747
748 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
749 rbspi_peripherals_setup(flags);
750
751 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
752 rbspi_network_setup(flags, 0, 2, 0);
753
754 if (flags & RBSPI_HAS_POE)
755 gpio_request_one(RBMAP_GPIO_POE_POWER,
756 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
757 "POE power");
758
759 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
760 }
761
762
763 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
764 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
765 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
766 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
767 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
768 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
769 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
770 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);