target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c

   1 /*
   2  * Compex WPJ344 board support
   3  *
   4  * Copyright (c) 2011 Qualcomm Atheros
   5  * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include <linux/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/ath9k_platform.h>
  24 #include <linux/ar8216_platform.h>
  25
  26 #include <asm/mach-ath79/ar71xx_regs.h>
  27
  28 #include "common.h"
  29 #include "pci.h"
  30 #include "dev-ap9x-pci.h"
  31 #include "dev-gpio-buttons.h"
  32 #include "dev-eth.h"
  33 #include "dev-usb.h"
  34 #include "dev-leds-gpio.h"
  35 #include "dev-m25p80.h"
  36 #include "dev-spi.h"
  37 #include "dev-wmac.h"
  38 #include "machtypes.h"
  39
  40 #define WPJ344_GPIO_LED_SIG1    15
  41 #define WPJ344_GPIO_LED_SIG2    20
  42 #define WPJ344_GPIO_LED_SIG3    21
  43 #define WPJ344_GPIO_LED_SIG4    22
  44 #define WPJ344_GPIO_LED_STATUS  14
  45
  46 #define WPJ344_GPIO_BTN_RESET   12
  47
  48 #define WPJ344_KEYS_POLL_INTERVAL       20      /* msecs */
  49 #define WPJ344_KEYS_DEBOUNCE_INTERVAL   (3 * WPJ344_KEYS_POLL_INTERVAL)
  50
  51 #define WPJ344_MAC0_OFFSET              0
  52 #define WPJ344_MAC1_OFFSET              6
  53 #define WPJ344_WMAC_CALDATA_OFFSET      0x1000
  54 #define WPJ344_PCIE_CALDATA_OFFSET      0x5000
  55
  56 static struct gpio_led wpj344_leds_gpio[] __initdata = {
  57         {
  58                 .name           = "wpj344:green:status",
  59                 .gpio           = WPJ344_GPIO_LED_STATUS,
  60                 .active_low     = 1,
  61         },
  62         {
  63                 .name           = "wpj344:red:sig1",
  64                 .gpio           = WPJ344_GPIO_LED_SIG1,
  65                 .active_low     = 1,
  66         },
  67         {
  68                 .name           = "wpj344:yellow:sig2",
  69                 .gpio           = WPJ344_GPIO_LED_SIG2,
  70                 .active_low     = 1,
  71         },
  72         {
  73                 .name           = "wpj344:green:sig3",
  74                 .gpio           = WPJ344_GPIO_LED_SIG3,
  75                 .active_low     = 1,
  76         },
  77         {
  78                 .name           = "wpj344:green:sig4",
  79                 .gpio           = WPJ344_GPIO_LED_SIG4,
  80                 .active_low     = 1,
  81         }
  82 };
  83
  84 static struct gpio_keys_button wpj344_gpio_keys[] __initdata = {
  85         {
  86                 .desc           = "reset",
  87                 .type           = EV_KEY,
  88                 .code           = KEY_RESTART,
  89                 .debounce_interval = WPJ344_KEYS_DEBOUNCE_INTERVAL,
  90                 .gpio           = WPJ344_GPIO_BTN_RESET,
  91                 .active_low     = 1,
  92         },
  93 };
  94
  95 static struct ar8327_pad_cfg wpj344_ar8327_pad0_cfg = {
  96         .mode = AR8327_PAD_MAC_RGMII,
  97         .txclk_delay_en = true,
  98         .rxclk_delay_en = true,
  99         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 100         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 101 };
 102
 103 static struct ar8327_led_cfg wpj344_ar8327_led_cfg = {
 104         .led_ctrl0 = 0x00000000,
 105         .led_ctrl1 = 0xc737c737,
 106         .led_ctrl2 = 0x00000000,
 107         .led_ctrl3 = 0x00c30c00,
 108         .open_drain = true,
 109 };
 110
 111 static struct ar8327_platform_data wpj344_ar8327_data = {
 112         .pad0_cfg = &wpj344_ar8327_pad0_cfg,
 113         .port0_cfg = {
 114                 .force_link = 1,
 115                 .speed = AR8327_PORT_SPEED_1000,
 116                 .duplex = 1,
 117                 .txpause = 1,
 118                 .rxpause = 1,
 119         },
 120         .led_cfg = &wpj344_ar8327_led_cfg,
 121 };
 122
 123 static struct mdio_board_info wpj344_mdio0_info[] = {
 124         {
 125                 .bus_id = "ag71xx-mdio.0",
 126                 .phy_addr = 0,
 127                 .platform_data = &wpj344_ar8327_data,
 128         },
 129 };
 130
 131 static void __init wpj344_setup(void)
 132 {
 133         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 134
 135         ath79_register_m25p80(NULL);
 136         ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj344_leds_gpio),
 137                                  wpj344_leds_gpio);
 138         ath79_register_gpio_keys_polled(-1, WPJ344_KEYS_POLL_INTERVAL,
 139                                         ARRAY_SIZE(wpj344_gpio_keys),
 140                                         wpj344_gpio_keys);
 141
 142         ath79_register_usb();
 143
 144         ath79_register_wmac(art + WPJ344_WMAC_CALDATA_OFFSET, NULL);
 145
 146         ath79_register_pci();
 147
 148         mdiobus_register_board_info(wpj344_mdio0_info,
 149                                         ARRAY_SIZE(wpj344_mdio0_info));
 150
 151         ath79_register_mdio(1, 0x0);
 152         ath79_register_mdio(0, 0x0);
 153
 154         ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ344_MAC0_OFFSET, 0);
 155         ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ344_MAC1_OFFSET, 0);
 156
 157         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
 158                                    AR934X_ETH_CFG_SW_ONLY_MODE);
 159
 160         /* GMAC0 is connected to an AR8327 switch */
 161         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 162         ath79_eth0_data.phy_mask = BIT(0);
 163         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 164         ath79_eth0_pll_data.pll_1000 = 0x06000000;
 165
 166         /* GMAC1 is connected to the internal switch */
 167         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 168         ath79_eth1_data.speed = SPEED_1000;
 169         ath79_eth1_data.duplex = DUPLEX_FULL;
 170
 171         ath79_register_eth(0);
 172         ath79_register_eth(1);
 173 }
 174
 175 MIPS_MACHINE(ATH79_MACH_WPJ344, "WPJ344", "Compex WPJ344", wpj344_setup);