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ar71xx: remove the use of the obsolete IRQF_DISABLED flag in the NAND flash driver...
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / mtd / nand / ar934x_nfc.c
1 /*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
21
22 #include <linux/platform/ar934x_nfc.h>
23
24 #define AR934X_NFC_REG_CMD 0x00
25 #define AR934X_NFC_REG_CTRL 0x04
26 #define AR934X_NFC_REG_STATUS 0x08
27 #define AR934X_NFC_REG_INT_MASK 0x0c
28 #define AR934X_NFC_REG_INT_STATUS 0x10
29 #define AR934X_NFC_REG_ECC_CTRL 0x14
30 #define AR934X_NFC_REG_ECC_OFFSET 0x18
31 #define AR934X_NFC_REG_ADDR0_0 0x1c
32 #define AR934X_NFC_REG_ADDR0_1 0x24
33 #define AR934X_NFC_REG_ADDR1_0 0x20
34 #define AR934X_NFC_REG_ADDR1_1 0x28
35 #define AR934X_NFC_REG_SPARE_SIZE 0x30
36 #define AR934X_NFC_REG_PROTECT 0x38
37 #define AR934X_NFC_REG_LOOKUP_EN 0x40
38 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39 #define AR934X_NFC_REG_DMA_ADDR 0x64
40 #define AR934X_NFC_REG_DMA_COUNT 0x68
41 #define AR934X_NFC_REG_DMA_CTRL 0x6c
42 #define AR934X_NFC_REG_MEM_CTRL 0x80
43 #define AR934X_NFC_REG_DATA_SIZE 0x84
44 #define AR934X_NFC_REG_READ_STATUS 0x88
45 #define AR934X_NFC_REG_TIME_SEQ 0x8c
46 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
48 #define AR934X_NFC_REG_FIFO_DATA 0x98
49 #define AR934X_NFC_REG_TIME_MODE 0x9c
50 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51 #define AR934X_NFC_REG_FIFO_INIT 0xb0
52 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
53
54 #define AR934X_NFC_CMD_CMD_SEQ_S 0
55 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56 #define AR934X_NFC_CMD_SEQ_1C 0x00
57 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58 #define AR934X_NFC_CMD_SEQ_12 0x0c
59 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60 #define AR934X_NFC_CMD_SEQ_S 0x24
61 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63 #define AR934X_NFC_CMD_SEQ_18 0x32
64 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66 #define AR934X_NFC_CMD_ADDR_SEL_0 0
67 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68 #define AR934X_NFC_CMD_CMD0_S 8
69 #define AR934X_NFC_CMD_CMD0_M 0xff
70 #define AR934X_NFC_CMD_CMD1_S 16
71 #define AR934X_NFC_CMD_CMD1_M 0xff
72 #define AR934X_NFC_CMD_CMD2_S 24
73 #define AR934X_NFC_CMD_CMD2_M 0xff
74
75 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78 #define AR934X_NFC_CTRL_INT_EN BIT(4)
79 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
80 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
100 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
107
108 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
121
122 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123 #define AR934X_NFC_INT_CMD_END BIT(1)
124
125 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
126 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
127 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
128 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
129 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
130 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
131 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
132 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
133 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
137 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
138 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
139 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
140
141 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
142
143 /* default timing values */
144 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
145 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
146 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
147
148 #define AR934X_NFC_ID_BUF_SIZE 8
149 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
150 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
151 #define AR934X_NFC_DONE_TIMEOUT 1000
152 #define AR934X_NFC_DMA_RETRIES 20
153
154 #define AR934X_NFC_USE_IRQ true
155 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
156
157 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
158
159 #undef AR934X_NFC_DEBUG_DATA
160 #undef AR934X_NFC_DEBUG
161
162 struct ar934x_nfc;
163
164 static inline __attribute__ ((format (printf, 2, 3)))
165 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
166 {
167 }
168
169 #ifdef AR934X_NFC_DEBUG
170 #define nfc_dbg(_nfc, fmt, ...) \
171 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
172 #else
173 #define nfc_dbg(_nfc, fmt, ...) \
174 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
175 #endif /* AR934X_NFC_DEBUG */
176
177 #ifdef AR934X_NFC_DEBUG_DATA
178 static void
179 nfc_debug_data(const char *label, void *data, int len)
180 {
181 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
182 data, len, 0);
183 }
184 #else
185 static inline void
186 nfc_debug_data(const char *label, void *data, int len) {}
187 #endif /* AR934X_NFC_DEBUG_DATA */
188
189 struct ar934x_nfc {
190 struct mtd_info mtd;
191 struct nand_chip nand_chip;
192 struct device *parent;
193 void __iomem *base;
194 void (*select_chip)(int chip_no);
195 bool swap_dma;
196 int irq;
197 wait_queue_head_t irq_waitq;
198
199 bool spurious_irq_expected;
200 u32 irq_status;
201
202 u32 ctrl_reg;
203 u32 ecc_ctrl_reg;
204 u32 ecc_offset_reg;
205 u32 ecc_thres;
206 u32 ecc_oob_pos;
207
208 bool small_page;
209 unsigned int addr_count0;
210 unsigned int addr_count1;
211
212 u8 *buf;
213 dma_addr_t buf_dma;
214 unsigned int buf_size;
215 int buf_index;
216
217 bool read_id;
218
219 int erase1_page_addr;
220
221 int rndout_page_addr;
222 int rndout_read_cmd;
223
224 int seqin_page_addr;
225 int seqin_column;
226 int seqin_read_cmd;
227 };
228
229 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
230
231 static inline bool
232 is_all_ff(u8 *buf, int len)
233 {
234 while (len--)
235 if (buf[len] != 0xff)
236 return false;
237
238 return true;
239 }
240
241 static inline void
242 ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
243 {
244 __raw_writel(val, nfc->base + reg);
245 }
246
247 static inline u32
248 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
249 {
250 return __raw_readl(nfc->base + reg);
251 }
252
253 static inline struct ar934x_nfc_platform_data *
254 ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
255 {
256 return nfc->parent->platform_data;
257 }
258
259 static inline struct
260 ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
261 {
262 return container_of(mtd, struct ar934x_nfc, mtd);
263 }
264
265 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
266 {
267 return AR934X_NFC_USE_IRQ;
268 }
269
270 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
271 {
272 wmb();
273
274 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
275 /* flush write */
276 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
277 }
278
279 static bool
280 __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
281 {
282 u32 status;
283
284 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
285 return (status & 0xff) == 0xff;
286 }
287
288 static inline bool
289 __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
290 {
291 u32 status;
292
293 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
294 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
295 }
296
297 static int
298 ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
299 {
300 unsigned long timeout;
301
302 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
303 do {
304 if (__ar934x_nfc_dev_ready(nfc))
305 return 0;
306 } while time_before(jiffies, timeout);
307
308 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
309 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
310 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
311 return -ETIMEDOUT;
312 }
313
314 static int
315 ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
316 {
317 unsigned long timeout;
318
319 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
320 do {
321 if (__ar934x_nfc_is_dma_ready(nfc))
322 return 0;
323 } while time_before(jiffies, timeout);
324
325 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
326 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
327 return -ETIMEDOUT;
328 }
329
330 static int
331 ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
332 {
333 long timeout;
334 int ret;
335
336 timeout = wait_event_timeout(nfc->irq_waitq,
337 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
338 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
339
340 ret = 0;
341 if (!timeout) {
342 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
343 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
344 /* flush write */
345 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
346
347 nfc_dbg(nfc,
348 "timeout waiting for interrupt, status:%08x\n",
349 nfc->irq_status);
350 ret = -ETIMEDOUT;
351 }
352
353 nfc->irq_status = 0;
354 return ret;
355 }
356
357 static int
358 ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
359 {
360 int ret;
361
362 if (ar934x_nfc_use_irq(nfc))
363 ret = ar934x_nfc_wait_irq(nfc);
364 else
365 ret = ar934x_nfc_wait_dev_ready(nfc);
366
367 if (ret)
368 return ret;
369
370 return ar934x_nfc_wait_dma_ready(nfc);
371 }
372
373 static int
374 ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
375 {
376 nfc->buf = dma_alloc_coherent(nfc->parent, size,
377 &nfc->buf_dma, GFP_KERNEL);
378 if (nfc->buf == NULL) {
379 dev_err(nfc->parent, "no memory for DMA buffer\n");
380 return -ENOMEM;
381 }
382
383 nfc->buf_size = size;
384 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
385
386 return 0;
387 }
388
389 static void
390 ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
391 {
392 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
393 }
394
395 static void
396 ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
397 u32 *addr0, u32 *addr1)
398 {
399 u32 a0, a1;
400
401 a0 = 0;
402 a1 = 0;
403
404 if (column == -1) {
405 /* ERASE1 */
406 a0 = (page_addr & 0xffff) << 16;
407 a1 = (page_addr >> 16) & 0xf;
408 } else if (page_addr != -1) {
409 /* SEQIN, READ0, etc.. */
410
411 /* TODO: handle 16bit bus width */
412 if (nfc->small_page) {
413 a0 = column & 0xff;
414 a0 |= (page_addr & 0xff) << 8;
415 a0 |= ((page_addr >> 8) & 0xff) << 16;
416 a0 |= ((page_addr >> 16) & 0xff) << 24;
417 } else {
418 a0 = column & 0x0FFF;
419 a0 |= (page_addr & 0xffff) << 16;
420
421 if (nfc->addr_count0 > 4)
422 a1 = (page_addr >> 16) & 0xf;
423 }
424 }
425
426 *addr0 = a0;
427 *addr1 = a1;
428 }
429
430 static void
431 ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
432 {
433 u32 cmd_reg;
434
435 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
436 AR934X_NFC_CMD_SEQ_1C;
437 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
438
439 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
440 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
441
442 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
443 ar934x_nfc_wait_dev_ready(nfc);
444 }
445
446 static int
447 ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
448 int len, u32 cmd_reg, u32 ctrl_reg, bool write)
449 {
450 u32 addr0, addr1;
451 u32 dma_ctrl;
452 int dir;
453 int err;
454 int retries = 0;
455
456 WARN_ON(len & 3);
457
458 if (WARN_ON(len > nfc->buf_size))
459 dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
460
461 if (write) {
462 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
463 dir = DMA_TO_DEVICE;
464 } else {
465 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
466 dir = DMA_FROM_DEVICE;
467 }
468
469 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
470
471 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
472 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
473 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
474
475 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
476 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
477
478 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
479 (write) ? "write" : "read",
480 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
481
482 retry:
483 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
484 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
485 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
486 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
487 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
488 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
489 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
490 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
491 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg);
492 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg);
493
494 if (ar934x_nfc_use_irq(nfc)) {
495 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
496 /* flush write */
497 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
498 }
499
500 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
501 err = ar934x_nfc_wait_done(nfc);
502 if (err) {
503 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
504 (write) ? "write" : "read", page_addr);
505
506 ar934x_nfc_restart(nfc);
507 if (retries++ < AR934X_NFC_DMA_RETRIES)
508 goto retry;
509
510 dev_err(nfc->parent, "%s operation failed on page %d\n",
511 (write) ? "write" : "read", page_addr);
512 }
513
514 return err;
515 }
516
517 static int
518 ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
519 {
520 u32 cmd_reg;
521 int err;
522
523 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
524
525 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
526 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
527
528 err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE,
529 cmd_reg, nfc->ctrl_reg, false);
530
531 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
532
533 return err;
534 }
535
536 static int
537 ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
538 int page_addr, int len)
539 {
540 u32 cmd_reg;
541 int err;
542
543 nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
544 column, page_addr, len);
545
546 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
547
548 if (nfc->small_page) {
549 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
550 } else {
551 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
552 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
553 }
554
555 err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
556 cmd_reg, nfc->ctrl_reg, false);
557
558 nfc_debug_data("[data] ", nfc->buf, len);
559
560 return err;
561 }
562
563 static void
564 ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
565 int page_addr)
566 {
567 u32 addr0, addr1;
568 u32 ctrl_reg;
569 u32 cmd_reg;
570
571 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
572
573 ctrl_reg = nfc->ctrl_reg;
574 if (nfc->small_page) {
575 /* override number of address cycles for the erase command */
576 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
577 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
578 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
579 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
580 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
581 ctrl_reg |= (nfc->addr_count0 + 1) <<
582 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
583 }
584
585 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
586 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
587 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
588
589 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
590 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
591
592 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
593 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
594 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
595 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
596
597 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
598 ar934x_nfc_wait_dev_ready(nfc);
599 }
600
601 static int
602 ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
603 int page_addr, int len)
604 {
605 u32 cmd_reg;
606
607 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
608 column, page_addr, len);
609
610 nfc_debug_data("[data] ", nfc->buf, len);
611
612 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
613 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
614 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
615
616 return ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
617 cmd_reg, nfc->ctrl_reg, true);
618 }
619
620 static void
621 ar934x_nfc_read_status(struct ar934x_nfc *nfc)
622 {
623 u32 cmd_reg;
624 u32 status;
625
626 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
627 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
628
629 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
630 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
631
632 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
633 ar934x_nfc_wait_dev_ready(nfc);
634
635 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
636
637 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
638 cmd_reg, (status & 0xff));
639
640 if (nfc->swap_dma)
641 nfc->buf[0 ^ 3] = status;
642 else
643 nfc->buf[0] = status;
644 }
645
646 static void
647 ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
648 int page_addr)
649 {
650 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
651 struct nand_chip *nand = mtd->priv;
652
653 nfc->read_id = false;
654 if (command != NAND_CMD_PAGEPROG)
655 nfc->buf_index = 0;
656
657 switch (command) {
658 case NAND_CMD_RESET:
659 ar934x_nfc_send_cmd(nfc, command);
660 break;
661
662 case NAND_CMD_READID:
663 nfc->read_id = true;
664 ar934x_nfc_send_readid(nfc, command);
665 break;
666
667 case NAND_CMD_READ0:
668 case NAND_CMD_READ1:
669 if (nfc->small_page) {
670 ar934x_nfc_send_read(nfc, command, column, page_addr,
671 mtd->writesize + mtd->oobsize);
672 } else {
673 ar934x_nfc_send_read(nfc, command, 0, page_addr,
674 mtd->writesize + mtd->oobsize);
675 nfc->buf_index = column;
676 nfc->rndout_page_addr = page_addr;
677 nfc->rndout_read_cmd = command;
678 }
679 break;
680
681 case NAND_CMD_READOOB:
682 if (nfc->small_page)
683 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
684 column, page_addr,
685 mtd->oobsize);
686 else
687 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
688 mtd->writesize, page_addr,
689 mtd->oobsize);
690 break;
691
692 case NAND_CMD_RNDOUT:
693 if (WARN_ON(nfc->small_page))
694 break;
695
696 /* emulate subpage read */
697 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
698 nfc->rndout_page_addr,
699 mtd->writesize + mtd->oobsize);
700 nfc->buf_index = column;
701 break;
702
703 case NAND_CMD_ERASE1:
704 nfc->erase1_page_addr = page_addr;
705 break;
706
707 case NAND_CMD_ERASE2:
708 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
709 break;
710
711 case NAND_CMD_STATUS:
712 ar934x_nfc_read_status(nfc);
713 break;
714
715 case NAND_CMD_SEQIN:
716 if (nfc->small_page) {
717 /* output read command */
718 if (column >= mtd->writesize) {
719 column -= mtd->writesize;
720 nfc->seqin_read_cmd = NAND_CMD_READOOB;
721 } else if (column < 256) {
722 nfc->seqin_read_cmd = NAND_CMD_READ0;
723 } else {
724 column -= 256;
725 nfc->seqin_read_cmd = NAND_CMD_READ1;
726 }
727 } else {
728 nfc->seqin_read_cmd = NAND_CMD_READ0;
729 }
730 nfc->seqin_column = column;
731 nfc->seqin_page_addr = page_addr;
732 break;
733
734 case NAND_CMD_PAGEPROG:
735 if (nand->ecc.mode == NAND_ECC_HW) {
736 /* the data is already written */
737 break;
738 }
739
740 if (nfc->small_page)
741 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
742
743 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
744 nfc->seqin_page_addr,
745 nfc->buf_index);
746 break;
747
748 default:
749 dev_err(nfc->parent,
750 "unsupported command: %x, column:%d page_addr=%d\n",
751 command, column, page_addr);
752 break;
753 }
754 }
755
756 static int
757 ar934x_nfc_dev_ready(struct mtd_info *mtd)
758 {
759 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
760
761 return __ar934x_nfc_dev_ready(nfc);
762 }
763
764 static void
765 ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
766 {
767 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
768
769 if (nfc->select_chip)
770 nfc->select_chip(chip_no);
771 }
772
773 static u8
774 ar934x_nfc_read_byte(struct mtd_info *mtd)
775 {
776 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
777 u8 data;
778
779 WARN_ON(nfc->buf_index >= nfc->buf_size);
780
781 if (nfc->swap_dma || nfc->read_id)
782 data = nfc->buf[nfc->buf_index ^ 3];
783 else
784 data = nfc->buf[nfc->buf_index];
785
786 nfc->buf_index++;
787
788 return data;
789 }
790
791 static void
792 ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
793 {
794 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
795 int i;
796
797 WARN_ON(nfc->buf_index + len > nfc->buf_size);
798
799 if (nfc->swap_dma) {
800 for (i = 0; i < len; i++) {
801 nfc->buf[nfc->buf_index ^ 3] = buf[i];
802 nfc->buf_index++;
803 }
804 } else {
805 for (i = 0; i < len; i++) {
806 nfc->buf[nfc->buf_index] = buf[i];
807 nfc->buf_index++;
808 }
809 }
810 }
811
812 static void
813 ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
814 {
815 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
816 int buf_index;
817 int i;
818
819 WARN_ON(nfc->buf_index + len > nfc->buf_size);
820
821 buf_index = nfc->buf_index;
822
823 if (nfc->swap_dma || nfc->read_id) {
824 for (i = 0; i < len; i++) {
825 buf[i] = nfc->buf[buf_index ^ 3];
826 buf_index++;
827 }
828 } else {
829 for (i = 0; i < len; i++) {
830 buf[i] = nfc->buf[buf_index];
831 buf_index++;
832 }
833 }
834
835 nfc->buf_index = buf_index;
836 }
837
838 static inline void
839 ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc)
840 {
841 nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN;
842 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
843 }
844
845 static inline void
846 ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
847 {
848 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN;
849 nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
850 }
851
852 static int
853 ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
854 int page)
855 {
856 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
857 int err;
858
859 nfc_dbg(nfc, "read_oob: page:%d\n", page);
860
861 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page,
862 mtd->oobsize);
863 if (err)
864 return err;
865
866 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
867
868 return 0;
869 }
870
871 static int
872 ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
873 int page)
874 {
875 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
876
877 nfc_dbg(nfc, "write_oob: page:%d\n", page);
878
879 memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
880
881 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize,
882 page, mtd->oobsize);
883 }
884
885 static int
886 ar934x_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
887 u8 *buf, int oob_required, int page)
888 {
889 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
890 int len;
891 int err;
892
893 nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required);
894
895 len = mtd->writesize;
896 if (oob_required)
897 len += mtd->oobsize;
898
899 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len);
900 if (err)
901 return err;
902
903 memcpy(buf, nfc->buf, mtd->writesize);
904
905 if (oob_required)
906 memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize);
907
908 return 0;
909 }
910
911 static int
912 ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
913 u8 *buf, int oob_required, int page)
914 {
915 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
916 u32 ecc_ctrl;
917 int max_bitflips = 0;
918 bool ecc_failed;
919 bool ecc_corrected;
920 int err;
921
922 nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required);
923
924 ar934x_nfc_enable_hwecc(nfc);
925 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page,
926 mtd->writesize);
927 ar934x_nfc_disable_hwecc(nfc);
928
929 if (err)
930 return err;
931
932 /* TODO: optimize to avoid memcpy */
933 memcpy(buf, nfc->buf, mtd->writesize);
934
935 /* read the ECC status */
936 ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL);
937 ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT;
938 ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT;
939
940 if (oob_required || ecc_failed) {
941 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize,
942 page, mtd->oobsize);
943 if (err)
944 return err;
945
946 if (oob_required)
947 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
948 }
949
950 if (ecc_failed) {
951 /*
952 * The hardware ECC engine reports uncorrectable errors
953 * on empty pages. Check the ECC bytes and the data. If
954 * both contains 0xff bytes only, dont report a failure.
955 *
956 * TODO: prebuild a buffer with 0xff bytes and use memcmp
957 * for better performance?
958 */
959 if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) ||
960 !is_all_ff(buf, mtd->writesize))
961 mtd->ecc_stats.failed++;
962 } else if (ecc_corrected) {
963 /*
964 * The hardware does not report the exact count of the
965 * corrected bitflips, use assumptions based on the
966 * threshold.
967 */
968 if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) {
969 /*
970 * The number of corrected bitflips exceeds the
971 * threshold. Assume the maximum.
972 */
973 max_bitflips = chip->ecc.strength * chip->ecc.steps;
974 } else {
975 max_bitflips = nfc->ecc_thres * chip->ecc.steps;
976 }
977
978 mtd->ecc_stats.corrected += max_bitflips;
979 }
980
981 return max_bitflips;
982 }
983
984 static int
985 ar934x_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
986 const u8 *buf, int oob_required)
987 {
988 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
989 int page;
990 int len;
991
992 page = nfc->seqin_page_addr;
993
994 nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
995
996 memcpy(nfc->buf, buf, mtd->writesize);
997 len = mtd->writesize;
998
999 if (oob_required) {
1000 memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize);
1001 len += mtd->oobsize;
1002 }
1003
1004 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
1005 }
1006
1007 static int
1008 ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1009 const u8 *buf, int oob_required)
1010 {
1011 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
1012 int page;
1013 int err;
1014
1015 page = nfc->seqin_page_addr;
1016
1017 nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
1018
1019 /* write OOB first */
1020 if (oob_required &&
1021 !is_all_ff(chip->oob_poi, mtd->oobsize)) {
1022 err = ar934x_nfc_write_oob(mtd, chip, page);
1023 if (err)
1024 return err;
1025 }
1026
1027 /* TODO: optimize to avoid memcopy */
1028 memcpy(nfc->buf, buf, mtd->writesize);
1029
1030 ar934x_nfc_enable_hwecc(nfc);
1031 err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page,
1032 mtd->writesize);
1033 ar934x_nfc_disable_hwecc(nfc);
1034
1035 return err;
1036 }
1037
1038 static void
1039 ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
1040 {
1041 struct ar934x_nfc_platform_data *pdata;
1042
1043 pdata = ar934x_nfc_get_platform_data(nfc);
1044 if (pdata->hw_reset) {
1045 pdata->hw_reset(true);
1046 pdata->hw_reset(false);
1047 }
1048
1049 /*
1050 * setup timings
1051 * TODO: make it configurable via platform data
1052 */
1053 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
1054 AR934X_NFC_TIME_SEQ_DEFAULT);
1055 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
1056 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
1057 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
1058 AR934X_NFC_TIMINGS_SYN_DEFAULT);
1059
1060 /* disable WP on all chips, and select chip 0 */
1061 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
1062
1063 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
1064
1065 /* initialize Control register */
1066 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1067 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1068
1069 if (nfc->small_page) {
1070 /* Setup generic sequence register for small page reads. */
1071 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
1072 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
1073 }
1074 }
1075
1076 static void
1077 ar934x_nfc_restart(struct ar934x_nfc *nfc)
1078 {
1079 u32 ctrl_reg;
1080
1081 if (nfc->select_chip)
1082 nfc->select_chip(-1);
1083
1084 ctrl_reg = nfc->ctrl_reg;
1085 ar934x_nfc_hw_init(nfc);
1086 nfc->ctrl_reg = ctrl_reg;
1087
1088 if (nfc->select_chip)
1089 nfc->select_chip(0);
1090
1091 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
1092 }
1093
1094 static irqreturn_t
1095 ar934x_nfc_irq_handler(int irq, void *data)
1096 {
1097 struct ar934x_nfc *nfc = data;
1098 u32 status;
1099
1100 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1101
1102 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
1103 /* flush write */
1104 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1105
1106 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
1107 if (status) {
1108 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
1109
1110 nfc->irq_status = status;
1111 nfc->spurious_irq_expected = true;
1112 wake_up(&nfc->irq_waitq);
1113 } else {
1114 if (nfc->spurious_irq_expected) {
1115 nfc->spurious_irq_expected = false;
1116 } else {
1117 dev_warn(nfc->parent, "spurious interrupt\n");
1118 }
1119 }
1120
1121 return IRQ_HANDLED;
1122 }
1123
1124 static int
1125 ar934x_nfc_init_tail(struct mtd_info *mtd)
1126 {
1127 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
1128 struct nand_chip *chip = &nfc->nand_chip;
1129 u32 ctrl;
1130 u32 t;
1131 int err;
1132
1133 switch (mtd->oobsize) {
1134 case 16:
1135 case 64:
1136 case 128:
1137 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
1138 break;
1139
1140 default:
1141 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
1142 mtd->oobsize);
1143 return -ENXIO;
1144 }
1145
1146 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1147
1148 switch (mtd->erasesize / mtd->writesize) {
1149 case 32:
1150 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
1151 break;
1152
1153 case 64:
1154 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
1155 break;
1156
1157 case 128:
1158 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
1159 break;
1160
1161 case 256:
1162 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
1163 break;
1164
1165 default:
1166 dev_err(nfc->parent, "unsupported block size: %u\n",
1167 mtd->erasesize / mtd->writesize);
1168 return -ENXIO;
1169 }
1170
1171 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
1172
1173 switch (mtd->writesize) {
1174 case 256:
1175 nfc->small_page = 1;
1176 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
1177 break;
1178
1179 case 512:
1180 nfc->small_page = 1;
1181 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
1182 break;
1183
1184 case 1024:
1185 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
1186 break;
1187
1188 case 2048:
1189 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
1190 break;
1191
1192 case 4096:
1193 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
1194 break;
1195
1196 case 8192:
1197 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
1198 break;
1199
1200 case 16384:
1201 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
1202 break;
1203
1204 default:
1205 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
1206 mtd->writesize);
1207 return -ENXIO;
1208 }
1209
1210 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
1211
1212 if (nfc->small_page) {
1213 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
1214
1215 if (chip->chipsize > (32 << 20)) {
1216 nfc->addr_count0 = 4;
1217 nfc->addr_count1 = 3;
1218 } else if (chip->chipsize > (2 << 16)) {
1219 nfc->addr_count0 = 3;
1220 nfc->addr_count1 = 2;
1221 } else {
1222 nfc->addr_count0 = 2;
1223 nfc->addr_count1 = 1;
1224 }
1225 } else {
1226 if (chip->chipsize > (128 << 20)) {
1227 nfc->addr_count0 = 5;
1228 nfc->addr_count1 = 3;
1229 } else if (chip->chipsize > (8 << 16)) {
1230 nfc->addr_count0 = 4;
1231 nfc->addr_count1 = 2;
1232 } else {
1233 nfc->addr_count0 = 3;
1234 nfc->addr_count1 = 1;
1235 }
1236 }
1237
1238 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
1239 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
1240
1241 nfc->ctrl_reg = ctrl;
1242 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1243
1244 ar934x_nfc_free_buf(nfc);
1245 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
1246
1247 return err;
1248 }
1249
1250 static struct nand_ecclayout ar934x_nfc_oob_64_hwecc = {
1251 .eccbytes = 28,
1252 .eccpos = {
1253 20, 21, 22, 23, 24, 25, 26,
1254 27, 28, 29, 30, 31, 32, 33,
1255 34, 35, 36, 37, 38, 39, 40,
1256 41, 42, 43, 44, 45, 46, 47,
1257 },
1258 .oobfree = {
1259 {
1260 .offset = 4,
1261 .length = 16,
1262 },
1263 {
1264 .offset = 48,
1265 .length = 16,
1266 },
1267 },
1268 };
1269
1270 static int
1271 ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
1272 {
1273 struct nand_chip *nand = &nfc->nand_chip;
1274 u32 ecc_cap;
1275 u32 ecc_thres;
1276
1277 if (!config_enabled(CONFIG_MTD_NAND_AR934X_HW_ECC)) {
1278 dev_err(nfc->parent, "hardware ECC support is disabled\n");
1279 return -EINVAL;
1280 }
1281
1282 switch (nfc->mtd.writesize) {
1283 case 2048:
1284 /*
1285 * Writing a subpage separately is not supported, because
1286 * the controller only does ECC on full-page accesses.
1287 */
1288 nand->options = NAND_NO_SUBPAGE_WRITE;
1289
1290 nand->ecc.size = 512;
1291 nand->ecc.bytes = 7;
1292 nand->ecc.strength = 4;
1293 nand->ecc.layout = &ar934x_nfc_oob_64_hwecc;
1294 break;
1295
1296 default:
1297 dev_err(nfc->parent,
1298 "hardware ECC is not available for %d byte pages\n",
1299 nfc->mtd.writesize);
1300 return -EINVAL;
1301 }
1302
1303 BUG_ON(!nand->ecc.layout);
1304
1305 switch (nand->ecc.strength) {
1306 case 4:
1307 ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4;
1308 ecc_thres = 4;
1309 break;
1310
1311 default:
1312 dev_err(nfc->parent, "unsupported ECC strength %u\n",
1313 nand->ecc.strength);
1314 return -EINVAL;
1315 }
1316
1317 nfc->ecc_thres = ecc_thres;
1318 nfc->ecc_oob_pos = nand->ecc.layout->eccpos[0];
1319
1320 nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;
1321 nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;
1322
1323 nfc->ecc_offset_reg = nfc->mtd.writesize + nfc->ecc_oob_pos;
1324
1325 nand->ecc.mode = NAND_ECC_HW;
1326 nand->ecc.read_page = ar934x_nfc_read_page;
1327 nand->ecc.read_page_raw = ar934x_nfc_read_page_raw;
1328 nand->ecc.write_page = ar934x_nfc_write_page;
1329 nand->ecc.write_page_raw = ar934x_nfc_write_page_raw;
1330 nand->ecc.read_oob = ar934x_nfc_read_oob;
1331 nand->ecc.write_oob = ar934x_nfc_write_oob;
1332
1333 return 0;
1334 }
1335
1336 static int
1337 ar934x_nfc_probe(struct platform_device *pdev)
1338 {
1339 static const char *part_probes[] = { "cmdlinepart", NULL, };
1340 struct ar934x_nfc_platform_data *pdata;
1341 struct ar934x_nfc *nfc;
1342 struct resource *res;
1343 struct mtd_info *mtd;
1344 struct nand_chip *nand;
1345 struct mtd_part_parser_data ppdata;
1346 int ret;
1347
1348 pdata = pdev->dev.platform_data;
1349 if (pdata == NULL) {
1350 dev_err(&pdev->dev, "no platform data defined\n");
1351 return -EINVAL;
1352 }
1353
1354 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1355 if (!res) {
1356 dev_err(&pdev->dev, "failed to get I/O memory\n");
1357 return -EINVAL;
1358 }
1359
1360 nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL);
1361 if (!nfc) {
1362 dev_err(&pdev->dev, "failed to allocate driver data\n");
1363 return -ENOMEM;
1364 }
1365
1366 nfc->base = devm_ioremap_resource(&pdev->dev, res);
1367 if (IS_ERR(nfc->base)) {
1368 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1369 return PTR_ERR(nfc->base);
1370 }
1371
1372 nfc->irq = platform_get_irq(pdev, 0);
1373 if (nfc->irq < 0) {
1374 dev_err(&pdev->dev, "no IRQ resource specified\n");
1375 return -EINVAL;
1376 }
1377
1378 init_waitqueue_head(&nfc->irq_waitq);
1379 ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, 0,
1380 dev_name(&pdev->dev), nfc);
1381 if (ret) {
1382 dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
1383 return ret;
1384 }
1385
1386 nfc->parent = &pdev->dev;
1387 nfc->select_chip = pdata->select_chip;
1388 nfc->swap_dma = pdata->swap_dma;
1389
1390 nand = &nfc->nand_chip;
1391 mtd = &nfc->mtd;
1392
1393 mtd->priv = nand;
1394 mtd->owner = THIS_MODULE;
1395 if (pdata->name)
1396 mtd->name = pdata->name;
1397 else
1398 mtd->name = dev_name(&pdev->dev);
1399
1400 nand->chip_delay = 25;
1401
1402 nand->dev_ready = ar934x_nfc_dev_ready;
1403 nand->cmdfunc = ar934x_nfc_cmdfunc;
1404 nand->read_byte = ar934x_nfc_read_byte;
1405 nand->write_buf = ar934x_nfc_write_buf;
1406 nand->read_buf = ar934x_nfc_read_buf;
1407 nand->select_chip = ar934x_nfc_select_chip;
1408
1409 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1410 if (ret)
1411 goto err_free_irq;
1412
1413 platform_set_drvdata(pdev, nfc);
1414
1415 ar934x_nfc_hw_init(nfc);
1416
1417 ret = nand_scan_ident(mtd, 1, NULL);
1418 if (ret) {
1419 dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
1420 goto err_free_buf;
1421 }
1422
1423 ret = ar934x_nfc_init_tail(mtd);
1424 if (ret) {
1425 dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
1426 goto err_free_buf;
1427 }
1428
1429 if (pdata->scan_fixup) {
1430 ret = pdata->scan_fixup(mtd);
1431 if (ret)
1432 goto err_free_buf;
1433 }
1434
1435 switch (pdata->ecc_mode) {
1436 case AR934X_NFC_ECC_SOFT:
1437 nand->ecc.mode = NAND_ECC_SOFT;
1438 break;
1439
1440 case AR934X_NFC_ECC_SOFT_BCH:
1441 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1442 break;
1443
1444 case AR934X_NFC_ECC_HW:
1445 ret = ar934x_nfc_setup_hwecc(nfc);
1446 if (ret)
1447 goto err_free_buf;
1448
1449 break;
1450
1451 default:
1452 dev_err(nfc->parent, "unknown ECC mode %d\n", pdata->ecc_mode);
1453 return -EINVAL;
1454 }
1455
1456 ret = nand_scan_tail(mtd);
1457 if (ret) {
1458 dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
1459 goto err_free_buf;
1460 }
1461
1462 memset(&ppdata, '\0', sizeof(ppdata));
1463 ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
1464 pdata->parts, pdata->nr_parts);
1465 if (ret) {
1466 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1467 goto err_free_buf;
1468 }
1469
1470 return 0;
1471
1472 err_free_buf:
1473 ar934x_nfc_free_buf(nfc);
1474 err_free_irq:
1475 free_irq(nfc->irq, nfc);
1476 return ret;
1477 }
1478
1479 static int
1480 ar934x_nfc_remove(struct platform_device *pdev)
1481 {
1482 struct ar934x_nfc *nfc;
1483
1484 nfc = platform_get_drvdata(pdev);
1485 if (nfc) {
1486 nand_release(&nfc->mtd);
1487 ar934x_nfc_free_buf(nfc);
1488 free_irq(nfc->irq, nfc);
1489 }
1490
1491 return 0;
1492 }
1493
1494 static struct platform_driver ar934x_nfc_driver = {
1495 .probe = ar934x_nfc_probe,
1496 .remove = ar934x_nfc_remove,
1497 .driver = {
1498 .name = AR934X_NFC_DRIVER_NAME,
1499 .owner = THIS_MODULE,
1500 },
1501 };
1502
1503 module_platform_driver(ar934x_nfc_driver);
1504
1505 MODULE_LICENSE("GPL v2");
1506 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1507 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1508 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
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