target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c

   1 /*
   2  *  NAND flash driver for the MikroTik RouterBOARD 91x series
   3  *
   4  *  Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/spinlock.h>
  13 #include <linux/module.h>
  14 #include <linux/mtd/rawnand.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/partitions.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/slab.h>
  20 #include <linux/gpio.h>
  21 #include <linux/platform_data/rb91x_nand.h>
  22 #include <linux/version.h>
  23
  24 #include <asm/mach-ath79/ar71xx_regs.h>
  25 #include <asm/mach-ath79/ath79.h>
  26
  27 #define DRV_DESC        "NAND flash driver for the RouterBOARD 91x series"
  28
  29 #define RB91X_NAND_NRWE         BIT(12)
  30
  31 #define RB91X_NAND_DATA_BITS    (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
  32                                  BIT(13) | BIT(14) | BIT(15))
  33
  34 #define RB91X_NAND_INPUT_BITS   (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
  35 #define RB91X_NAND_OUTPUT_BITS  (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
  36
  37 #define RB91X_NAND_LOW_DATA_MASK        0x1f
  38 #define RB91X_NAND_HIGH_DATA_MASK       0xe0
  39 #define RB91X_NAND_HIGH_DATA_SHIFT      8
  40
  41 struct rb91x_nand_info {
  42         struct nand_chip chip;
  43 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  44         struct mtd_info mtd;
  45 #endif
  46         struct device *dev;
  47
  48         int gpio_nce;
  49         int gpio_ale;
  50         int gpio_cle;
  51         int gpio_rdy;
  52         int gpio_read;
  53         int gpio_nrw;
  54         int gpio_nle;
  55 };
  56
  57 static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
  58 {
  59 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  60         return container_of(mtd, struct rb91x_nand_info, mtd);
  61 #else
  62         struct nand_chip *chip = mtd_to_nand(mtd);
  63
  64         return container_of(chip, struct rb91x_nand_info, chip);
  65 #endif
  66 }
  67
  68 static struct mtd_info *rbinfo_to_mtd(struct rb91x_nand_info *nfc)
  69 {
  70 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  71         return &nfc->mtd;
  72 #else
  73         return nand_to_mtd(&nfc->chip);
  74 #endif
  75 }
  76
  77
  78 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  79 /*
  80  * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  81  * will not be able to find the kernel that we load.
  82  */
  83 static struct nand_ecclayout rb91x_nand_ecclayout = {
  84         .eccbytes       = 6,
  85         .eccpos         = { 8, 9, 10, 13, 14, 15 },
  86         .oobavail       = 9,
  87         .oobfree        = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  88 };
  89
  90 #else
  91
  92 static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
  93                                struct mtd_oob_region *oobregion)
  94 {
  95         switch (section) {
  96         case 0:
  97                 oobregion->offset = 8;
  98                 oobregion->length = 3;
  99                 return 0;
 100         case 1:
 101                 oobregion->offset = 13;
 102                 oobregion->length = 3;
 103                 return 0;
 104         default:
 105                 return -ERANGE;
 106         }
 107 }
 108
 109 static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
 110                                 struct mtd_oob_region *oobregion)
 111 {
 112         switch (section) {
 113         case 0:
 114                 oobregion->offset = 0;
 115                 oobregion->length = 4;
 116                 return 0;
 117         case 1:
 118                 oobregion->offset = 4;
 119                 oobregion->length = 1;
 120                 return 0;
 121         case 2:
 122                 oobregion->offset = 6;
 123                 oobregion->length = 2;
 124                 return 0;
 125         case 3:
 126                 oobregion->offset = 11;
 127                 oobregion->length = 2;
 128                 return 0;
 129         default:
 130                 return -ERANGE;
 131         }
 132 }
 133
 134 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
 135         .ecc = rb91x_ooblayout_ecc,
 136         .free = rb91x_ooblayout_free,
 137 };
 138 #endif /* < 4.6 */
 139
 140 static struct mtd_partition rb91x_nand_partitions[] = {
 141         {
 142                 .name   = "booter",
 143                 .offset = 0,
 144                 .size   = (256 * 1024),
 145                 .mask_flags = MTD_WRITEABLE,
 146         }, {
 147                 .name   = "kernel",
 148                 .offset = (256 * 1024),
 149                 .size   = (4 * 1024 * 1024) - (256 * 1024),
 150         }, {
 151                 .name   = "ubi",
 152                 .offset = MTDPART_OFS_NXTBLK,
 153                 .size   = MTDPART_SIZ_FULL,
 154         },
 155 };
 156
 157 static void rb91x_nand_write(struct rb91x_nand_info *rbni,
 158                              const u8 *buf,
 159                              unsigned len)
 160 {
 161         void __iomem *base = ath79_gpio_base;
 162         u32 oe_reg;
 163         u32 out_reg;
 164         u32 out;
 165         unsigned i;
 166
 167         /* enable the latch */
 168         gpio_set_value_cansleep(rbni->gpio_nle, 0);
 169
 170         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 171         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 172
 173         /* set data lines to output mode */
 174         __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
 175                      base + AR71XX_GPIO_REG_OE);
 176
 177         out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
 178         for (i = 0; i != len; i++) {
 179                 u32 data;
 180
 181                 data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
 182                         RB91X_NAND_HIGH_DATA_SHIFT;
 183                 data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
 184                 data |= out;
 185                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 186
 187                 /* deactivate WE line */
 188                 data |= RB91X_NAND_NRWE;
 189                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 190                 /* flush write */
 191                 __raw_readl(base + AR71XX_GPIO_REG_OUT);
 192         }
 193
 194         /* restore  registers */
 195         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 196         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 197         /* flush write */
 198         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 199
 200         /* disable the latch */
 201         gpio_set_value_cansleep(rbni->gpio_nle, 1);
 202 }
 203
 204 static void rb91x_nand_read(struct rb91x_nand_info *rbni,
 205                             u8 *read_buf,
 206                             unsigned len)
 207 {
 208         void __iomem *base = ath79_gpio_base;
 209         u32 oe_reg;
 210         u32 out_reg;
 211         unsigned i;
 212
 213         /* enable read mode */
 214         gpio_set_value_cansleep(rbni->gpio_read, 1);
 215
 216         /* enable latch */
 217         gpio_set_value_cansleep(rbni->gpio_nle, 0);
 218
 219         /* save registers */
 220         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 221         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 222
 223         /* set data lines to input mode */
 224         __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
 225                      base + AR71XX_GPIO_REG_OE);
 226
 227         for (i = 0; i < len; i++) {
 228                 u32 in;
 229                 u8 data;
 230
 231                 /* activate RE line */
 232                 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
 233                 /* flush write */
 234                 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
 235
 236                 /* read input lines */
 237                 in = __raw_readl(base + AR71XX_GPIO_REG_IN);
 238
 239                 /* deactivate RE line */
 240                 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
 241
 242                 data = (in & RB91X_NAND_LOW_DATA_MASK);
 243                 data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
 244                         RB91X_NAND_HIGH_DATA_MASK;
 245
 246                 read_buf[i] = data;
 247         }
 248
 249         /* restore  registers */
 250         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 251         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 252         /* flush write */
 253         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 254
 255         /* disable latch */
 256         gpio_set_value_cansleep(rbni->gpio_nle, 1);
 257
 258         /* disable read mode */
 259         gpio_set_value_cansleep(rbni->gpio_read, 0);
 260 }
 261
 262 static int rb91x_nand_dev_ready(struct mtd_info *mtd)
 263 {
 264         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 265
 266         return gpio_get_value_cansleep(rbni->gpio_rdy);
 267 }
 268
 269 static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 270                                 unsigned int ctrl)
 271 {
 272         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 273
 274         if (ctrl & NAND_CTRL_CHANGE) {
 275                 gpio_set_value_cansleep(rbni->gpio_cle,
 276                                         (ctrl & NAND_CLE) ? 1 : 0);
 277                 gpio_set_value_cansleep(rbni->gpio_ale,
 278                                         (ctrl & NAND_ALE) ? 1 : 0);
 279                 gpio_set_value_cansleep(rbni->gpio_nce,
 280                                         (ctrl & NAND_NCE) ? 0 : 1);
 281         }
 282
 283         if (cmd != NAND_CMD_NONE) {
 284                 u8 t = cmd;
 285
 286                 rb91x_nand_write(rbni, &t, 1);
 287         }
 288 }
 289
 290 static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
 291 {
 292         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 293         u8 data = 0xff;
 294
 295         rb91x_nand_read(rbni, &data, 1);
 296
 297         return data;
 298 }
 299
 300 static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 301 {
 302         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 303
 304         rb91x_nand_read(rbni, buf, len);
 305 }
 306
 307 static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 308 {
 309         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 310
 311         rb91x_nand_write(rbni, buf, len);
 312 }
 313
 314 static int rb91x_nand_gpio_init(struct rb91x_nand_info *info)
 315 {
 316         int ret;
 317
 318         /*
 319          * Ensure that the LATCH is disabled before initializing
 320          * control lines.
 321          */
 322         ret = devm_gpio_request_one(info->dev, info->gpio_nle,
 323                                     GPIOF_OUT_INIT_HIGH, "LATCH enable");
 324         if (ret)
 325                 return ret;
 326
 327         ret = devm_gpio_request_one(info->dev, info->gpio_nce,
 328                                     GPIOF_OUT_INIT_HIGH, "NAND nCE");
 329         if (ret)
 330                 return ret;
 331
 332         ret = devm_gpio_request_one(info->dev, info->gpio_nrw,
 333                                     GPIOF_OUT_INIT_HIGH, "NAND nRW");
 334         if (ret)
 335                 return ret;
 336
 337         ret = devm_gpio_request_one(info->dev, info->gpio_cle,
 338                                     GPIOF_OUT_INIT_LOW, "NAND CLE");
 339         if (ret)
 340                 return ret;
 341
 342         ret = devm_gpio_request_one(info->dev, info->gpio_ale,
 343                                     GPIOF_OUT_INIT_LOW, "NAND ALE");
 344         if (ret)
 345                 return ret;
 346
 347         ret = devm_gpio_request_one(info->dev, info->gpio_read,
 348                                     GPIOF_OUT_INIT_LOW, "NAND READ");
 349         if (ret)
 350                 return ret;
 351
 352         ret = devm_gpio_request_one(info->dev, info->gpio_rdy,
 353                                     GPIOF_IN, "NAND RDY");
 354         return ret;
 355 }
 356
 357 static int rb91x_nand_probe(struct platform_device *pdev)
 358 {
 359         struct rb91x_nand_info  *rbni;
 360         struct rb91x_nand_platform_data *pdata;
 361         struct mtd_info *mtd;
 362         int ret;
 363
 364         pr_info(DRV_DESC "\n");
 365
 366         pdata = dev_get_platdata(&pdev->dev);
 367         if (!pdata)
 368                 return -EINVAL;
 369
 370         rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL);
 371         if (!rbni)
 372                 return -ENOMEM;
 373
 374         rbni->dev = &pdev->dev;
 375         rbni->gpio_nce = pdata->gpio_nce;
 376         rbni->gpio_ale = pdata->gpio_ale;
 377         rbni->gpio_cle = pdata->gpio_cle;
 378         rbni->gpio_read = pdata->gpio_read;
 379         rbni->gpio_nrw = pdata->gpio_nrw;
 380         rbni->gpio_rdy = pdata->gpio_rdy;
 381         rbni->gpio_nle = pdata->gpio_nle;
 382
 383         rbni->chip.priv = &rbni;
 384         mtd = rbinfo_to_mtd(rbni);
 385
 386 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 387         mtd->priv       = &rbni->chip;
 388 #endif
 389         mtd->owner      = THIS_MODULE;
 390
 391         rbni->chip.cmd_ctrl     = rb91x_nand_cmd_ctrl;
 392         rbni->chip.dev_ready    = rb91x_nand_dev_ready;
 393         rbni->chip.read_byte    = rb91x_nand_read_byte;
 394         rbni->chip.write_buf    = rb91x_nand_write_buf;
 395         rbni->chip.read_buf     = rb91x_nand_read_buf;
 396
 397         rbni->chip.chip_delay   = 25;
 398         rbni->chip.ecc.mode     = NAND_ECC_SOFT;
 399 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
 400         rbni->chip.ecc.algo = NAND_ECC_HAMMING;
 401 #endif
 402         rbni->chip.options = NAND_NO_SUBPAGE_WRITE;
 403
 404         platform_set_drvdata(pdev, rbni);
 405
 406         ret = rb91x_nand_gpio_init(rbni);
 407         if (ret)
 408                 return ret;
 409
 410         ret = nand_scan_ident(mtd, 1, NULL);
 411         if (ret)
 412                 return ret;
 413
 414         if (mtd->writesize == 512)
 415 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 416                 rbni->chip.ecc.layout = &rb91x_nand_ecclayout;
 417 #else
 418                 mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
 419 #endif
 420
 421         ret = nand_scan_tail(mtd);
 422         if (ret)
 423                 return ret;
 424
 425         ret = mtd_device_register(mtd, rb91x_nand_partitions,
 426                                  ARRAY_SIZE(rb91x_nand_partitions));
 427         if (ret)
 428                 goto err_release_nand;
 429
 430         return 0;
 431
 432 err_release_nand:
 433         nand_release(mtd);
 434         return ret;
 435 }
 436
 437 static int rb91x_nand_remove(struct platform_device *pdev)
 438 {
 439         struct rb91x_nand_info *info = platform_get_drvdata(pdev);
 440
 441         nand_release(rbinfo_to_mtd(info));
 442
 443         return 0;
 444 }
 445
 446 static struct platform_driver rb91x_nand_driver = {
 447         .probe  = rb91x_nand_probe,
 448         .remove = rb91x_nand_remove,
 449         .driver = {
 450                 .name   = RB91X_NAND_DRIVER_NAME,
 451                 .owner  = THIS_MODULE,
 452         },
 453 };
 454
 455 module_platform_driver(rb91x_nand_driver);
 456
 457 MODULE_DESCRIPTION(DRV_DESC);
 458 MODULE_VERSION(DRV_VERSION);
 459 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 460 MODULE_LICENSE("GPL v2");