projects / openwrt / openwrt.git / blob
? search:


9e0ce9b3e44d1d973bbea04458493c19de17966a
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33
34 #include <linux/bitops.h>
35
36 #include <asm/mach-ar71xx/ar71xx.h>
37 #include <asm/mach-ar71xx/platform.h>
38
39 #define AG71XX_DRV_NAME "ag71xx"
40 #define AG71XX_DRV_VERSION "0.5.35"
41
42 #define AG71XX_NAPI_WEIGHT 64
43 #define AG71XX_OOM_REFILL (1 + HZ/10)
44
45 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
46 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
47 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
48
49 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
50 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
51
52 #define AG71XX_TX_MTU_LEN 1540
53 #define AG71XX_RX_PKT_RESERVE 64
54 #define AG71XX_RX_PKT_SIZE \
55 (AG71XX_RX_PKT_RESERVE + ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
56
57 #define AG71XX_TX_RING_SIZE 64
58 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
59 #define AG71XX_TX_THRES_WAKEUP \
60 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
61
62 #define AG71XX_RX_RING_SIZE 128
63
64 #ifdef CONFIG_AG71XX_DEBUG
65 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
66 #else
67 #define DBG(fmt, args...) do {} while (0)
68 #endif
69
70 #define ag71xx_assert(_cond) \
71 do { \
72 if (_cond) \
73 break; \
74 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
75 BUG(); \
76 } while (0)
77
78 struct ag71xx_desc {
79 u32 data;
80 u32 ctrl;
81 #define DESC_EMPTY BIT(31)
82 #define DESC_MORE BIT(24)
83 #define DESC_PKTLEN_M 0xfff
84 u32 next;
85 u32 pad;
86 } __attribute__((aligned(4)));
87
88 struct ag71xx_buf {
89 struct sk_buff *skb;
90 struct ag71xx_desc *desc;
91 dma_addr_t dma_addr;
92 unsigned long timestamp;
93 };
94
95 struct ag71xx_ring {
96 struct ag71xx_buf *buf;
97 u8 *descs_cpu;
98 dma_addr_t descs_dma;
99 unsigned int desc_size;
100 unsigned int curr;
101 unsigned int dirty;
102 unsigned int size;
103 };
104
105 struct ag71xx_mdio {
106 struct mii_bus *mii_bus;
107 int mii_irq[PHY_MAX_ADDR];
108 void __iomem *mdio_base;
109 struct ag71xx_mdio_platform_data *pdata;
110 };
111
112 struct ag71xx_int_stats {
113 unsigned long rx_pr;
114 unsigned long rx_be;
115 unsigned long rx_of;
116 unsigned long tx_ps;
117 unsigned long tx_be;
118 unsigned long tx_ur;
119 unsigned long total;
120 };
121
122 struct ag71xx_napi_stats {
123 unsigned long napi_calls;
124 unsigned long rx_count;
125 unsigned long rx_packets;
126 unsigned long rx_packets_max;
127 unsigned long tx_count;
128 unsigned long tx_packets;
129 unsigned long tx_packets_max;
130
131 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
132 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
133 };
134
135 struct ag71xx_debug {
136 struct dentry *debugfs_dir;
137
138 struct ag71xx_int_stats int_stats;
139 struct ag71xx_napi_stats napi_stats;
140 };
141
142 struct ag71xx {
143 void __iomem *mac_base;
144 void __iomem *mii_ctrl;
145
146 spinlock_t lock;
147 struct platform_device *pdev;
148 struct net_device *dev;
149 struct napi_struct napi;
150 u32 msg_enable;
151
152 struct ag71xx_ring rx_ring;
153 struct ag71xx_ring tx_ring;
154
155 struct mii_bus *mii_bus;
156 struct phy_device *phy_dev;
157 void *phy_priv;
158
159 unsigned int link;
160 unsigned int speed;
161 int duplex;
162
163 struct work_struct restart_work;
164 struct delayed_work link_work;
165 struct timer_list oom_timer;
166
167 #ifdef CONFIG_AG71XX_DEBUG_FS
168 struct ag71xx_debug debug;
169 #endif
170 };
171
172 extern struct ethtool_ops ag71xx_ethtool_ops;
173 void ag71xx_link_adjust(struct ag71xx *ag);
174
175 int ag71xx_mdio_driver_init(void) __init;
176 void ag71xx_mdio_driver_exit(void);
177
178 int ag71xx_phy_connect(struct ag71xx *ag);
179 void ag71xx_phy_disconnect(struct ag71xx *ag);
180 void ag71xx_phy_start(struct ag71xx *ag);
181 void ag71xx_phy_stop(struct ag71xx *ag);
182
183 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
184 {
185 return ag->pdev->dev.platform_data;
186 }
187
188 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
189 {
190 return (desc->ctrl & DESC_EMPTY) != 0;
191 }
192
193 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
194 {
195 return desc->ctrl & DESC_PKTLEN_M;
196 }
197
198 /* Register offsets */
199 #define AG71XX_REG_MAC_CFG1 0x0000
200 #define AG71XX_REG_MAC_CFG2 0x0004
201 #define AG71XX_REG_MAC_IPG 0x0008
202 #define AG71XX_REG_MAC_HDX 0x000c
203 #define AG71XX_REG_MAC_MFL 0x0010
204 #define AG71XX_REG_MII_CFG 0x0020
205 #define AG71XX_REG_MII_CMD 0x0024
206 #define AG71XX_REG_MII_ADDR 0x0028
207 #define AG71XX_REG_MII_CTRL 0x002c
208 #define AG71XX_REG_MII_STATUS 0x0030
209 #define AG71XX_REG_MII_IND 0x0034
210 #define AG71XX_REG_MAC_IFCTL 0x0038
211 #define AG71XX_REG_MAC_ADDR1 0x0040
212 #define AG71XX_REG_MAC_ADDR2 0x0044
213 #define AG71XX_REG_FIFO_CFG0 0x0048
214 #define AG71XX_REG_FIFO_CFG1 0x004c
215 #define AG71XX_REG_FIFO_CFG2 0x0050
216 #define AG71XX_REG_FIFO_CFG3 0x0054
217 #define AG71XX_REG_FIFO_CFG4 0x0058
218 #define AG71XX_REG_FIFO_CFG5 0x005c
219 #define AG71XX_REG_FIFO_RAM0 0x0060
220 #define AG71XX_REG_FIFO_RAM1 0x0064
221 #define AG71XX_REG_FIFO_RAM2 0x0068
222 #define AG71XX_REG_FIFO_RAM3 0x006c
223 #define AG71XX_REG_FIFO_RAM4 0x0070
224 #define AG71XX_REG_FIFO_RAM5 0x0074
225 #define AG71XX_REG_FIFO_RAM6 0x0078
226 #define AG71XX_REG_FIFO_RAM7 0x007c
227
228 #define AG71XX_REG_TX_CTRL 0x0180
229 #define AG71XX_REG_TX_DESC 0x0184
230 #define AG71XX_REG_TX_STATUS 0x0188
231 #define AG71XX_REG_RX_CTRL 0x018c
232 #define AG71XX_REG_RX_DESC 0x0190
233 #define AG71XX_REG_RX_STATUS 0x0194
234 #define AG71XX_REG_INT_ENABLE 0x0198
235 #define AG71XX_REG_INT_STATUS 0x019c
236
237 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
238 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
239 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
240 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
241 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
242 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
243 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
244 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
245
246 #define MAC_CFG2_FDX BIT(0)
247 #define MAC_CFG2_CRC_EN BIT(1)
248 #define MAC_CFG2_PAD_CRC_EN BIT(2)
249 #define MAC_CFG2_LEN_CHECK BIT(4)
250 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
251 #define MAC_CFG2_IF_1000 BIT(9)
252 #define MAC_CFG2_IF_10_100 BIT(8)
253
254 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
255 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
256 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
257 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
258 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
259 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
260 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
261
262 #define FIFO_CFG0_ENABLE_SHIFT 8
263
264 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
265 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
266 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
267 #define FIFO_CFG4_CE BIT(3) /* Code Error */
268 #define FIFO_CFG4_CR BIT(4) /* CRC error */
269 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
270 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
271 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
272 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
273 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
274 #define FIFO_CFG4_DR BIT(10) /* Dribble */
275 #define FIFO_CFG4_LE BIT(11) /* Long Event */
276 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
277 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
278 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
279 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
280 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
281 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
282
283 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
284 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
285 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
286 #define FIFO_CFG5_CE BIT(3) /* Code Error */
287 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
288 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
289 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
290 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
291 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
292 #define FIFO_CFG5_DR BIT(9) /* Dribble */
293 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
294 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
295 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
296 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
297 #define FIFO_CFG5_LE BIT(14) /* Long Event */
298 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
299 #define FIFO_CFG5_16 BIT(16) /* unknown */
300 #define FIFO_CFG5_17 BIT(17) /* unknown */
301 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
302 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
303
304 #define AG71XX_INT_TX_PS BIT(0)
305 #define AG71XX_INT_TX_UR BIT(1)
306 #define AG71XX_INT_TX_BE BIT(3)
307 #define AG71XX_INT_RX_PR BIT(4)
308 #define AG71XX_INT_RX_OF BIT(6)
309 #define AG71XX_INT_RX_BE BIT(7)
310
311 #define MAC_IFCTL_SPEED BIT(16)
312
313 #define MII_CFG_CLK_DIV_4 0
314 #define MII_CFG_CLK_DIV_6 2
315 #define MII_CFG_CLK_DIV_8 3
316 #define MII_CFG_CLK_DIV_10 4
317 #define MII_CFG_CLK_DIV_14 5
318 #define MII_CFG_CLK_DIV_20 6
319 #define MII_CFG_CLK_DIV_28 7
320 #define MII_CFG_RESET BIT(31)
321
322 #define MII_CMD_WRITE 0x0
323 #define MII_CMD_READ 0x1
324 #define MII_ADDR_SHIFT 8
325 #define MII_IND_BUSY BIT(0)
326 #define MII_IND_INVALID BIT(2)
327
328 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
329
330 #define TX_STATUS_PS BIT(0) /* Packet Sent */
331 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
332 #define TX_STATUS_BE BIT(3) /* Bus Error */
333
334 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
335
336 #define RX_STATUS_PR BIT(0) /* Packet Received */
337 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
338 #define RX_STATUS_BE BIT(3) /* Bus Error */
339
340 #define MII_CTRL_IF_MASK 3
341 #define MII_CTRL_SPEED_SHIFT 4
342 #define MII_CTRL_SPEED_MASK 3
343 #define MII_CTRL_SPEED_10 0
344 #define MII_CTRL_SPEED_100 1
345 #define MII_CTRL_SPEED_1000 2
346
347 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
348 {
349 switch (reg) {
350 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
351 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
352 break;
353
354 default:
355 BUG();
356 }
357 }
358
359 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
360 {
361 ag71xx_check_reg_offset(ag, reg);
362
363 __raw_writel(value, ag->mac_base + reg);
364 /* flush write */
365 (void) __raw_readl(ag->mac_base + reg);
366 }
367
368 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
369 {
370 ag71xx_check_reg_offset(ag, reg);
371
372 return __raw_readl(ag->mac_base + reg);
373 }
374
375 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
376 {
377 void __iomem *r;
378
379 ag71xx_check_reg_offset(ag, reg);
380
381 r = ag->mac_base + reg;
382 __raw_writel(__raw_readl(r) | mask, r);
383 /* flush write */
384 (void)__raw_readl(r);
385 }
386
387 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
388 {
389 void __iomem *r;
390
391 ag71xx_check_reg_offset(ag, reg);
392
393 r = ag->mac_base + reg;
394 __raw_writel(__raw_readl(r) & ~mask, r);
395 /* flush write */
396 (void) __raw_readl(r);
397 }
398
399 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
400 {
401 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
402 }
403
404 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
405 {
406 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
407 }
408
409 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
410 {
411 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
412
413 if (pdata->is_ar724x)
414 return;
415
416 __raw_writel(value, ag->mii_ctrl);
417
418 /* flush write */
419 __raw_readl(ag->mii_ctrl);
420 }
421
422 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
423 {
424 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
425
426 if (pdata->is_ar724x)
427 return 0xffffffff;
428
429 return __raw_readl(ag->mii_ctrl);
430 }
431
432 static inline void ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
433 unsigned int mii_if)
434 {
435 u32 t;
436
437 t = ag71xx_mii_ctrl_rr(ag);
438 t &= ~(MII_CTRL_IF_MASK);
439 t |= (mii_if & MII_CTRL_IF_MASK);
440 ag71xx_mii_ctrl_wr(ag, t);
441 }
442
443 static inline void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
444 unsigned int speed)
445 {
446 u32 t;
447
448 t = ag71xx_mii_ctrl_rr(ag);
449 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
450 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
451 ag71xx_mii_ctrl_wr(ag, t);
452 }
453
454 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
455 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
456 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
457 int pktlen);
458 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
459 {
460 return ag71xx_get_pdata(ag)->has_ar8216;
461 }
462 #else
463 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
464 struct sk_buff *skb)
465 {
466 }
467
468 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
469 struct sk_buff *skb,
470 int pktlen)
471 {
472 return 0;
473 }
474 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
475 {
476 return 0;
477 }
478 #endif
479
480 #ifdef CONFIG_AG71XX_DEBUG_FS
481 int ag71xx_debugfs_root_init(void);
482 void ag71xx_debugfs_root_exit(void);
483 int ag71xx_debugfs_init(struct ag71xx *ag);
484 void ag71xx_debugfs_exit(struct ag71xx *ag);
485 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
486 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
487 #else
488 static inline int ag71xx_debugfs_root_init(void) { return 0; }
489 static inline void ag71xx_debugfs_root_exit(void) {}
490 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
491 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
492 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
493 u32 status) {}
494 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
495 int rx, int tx) {}
496 #endif /* CONFIG_AG71XX_DEBUG_FS */
497
498 void ag71xx_ar7240_start(struct ag71xx *ag);
499 void ag71xx_ar7240_stop(struct ag71xx *ag);
500 int ag71xx_ar7240_init(struct ag71xx *ag);
501 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
502
503 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
504 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
505
506 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
507 unsigned reg_addr);
508 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
509 unsigned reg_addr, u16 reg_val);
510
511 #endif /* _AG71XX_H */
OpenWrt Source Repository