target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #ifndef __AG71XX_H
  15 #define __AG71XX_H
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/types.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/phy.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/bitops.h>
  31
  32 #include <asm/mach-ar71xx/ar71xx.h>
  33 #include <asm/mach-ar71xx/platform.h>
  34
  35 #define ETH_FCS_LEN     4
  36
  37 #define AG71XX_DRV_NAME         "ag71xx"
  38 #define AG71XX_DRV_VERSION      "0.3.9"
  39
  40 #define AG71XX_NAPI_TX          1
  41
  42 #define AG71XX_NAPI_WEIGHT      64
  43
  44 #define AG71XX_INT_ERR  (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  45 #define AG71XX_INT_TX   (AG71XX_INT_TX_PS)
  46 #define AG71XX_INT_RX   (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  47
  48 #ifdef AG71XX_NAPI_TX
  49 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  50 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  51 #else
  52 #define AG71XX_INT_POLL (AG71XX_INT_RX)
  53 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
  54 #endif
  55
  56 #define AG71XX_TX_FIFO_LEN      2048
  57 #define AG71XX_TX_MTU_LEN       1536
  58 #define AG71XX_RX_PKT_RESERVE   64
  59 #define AG71XX_RX_PKT_SIZE      \
  60         (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
  61
  62 #define AG71XX_TX_RING_SIZE     64
  63 #define AG71XX_TX_THRES_STOP    (AG71XX_TX_RING_SIZE - 4)
  64 #define AG71XX_TX_THRES_WAKEUP  \
  65                 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
  66
  67 #define AG71XX_RX_RING_SIZE     128
  68
  69 #undef DEBUG
  70 #ifdef DEBUG
  71 #define DBG(fmt, args...)       printk(KERN_DEBUG fmt, ## args)
  72 #else
  73 #define DBG(fmt, args...)       do {} while (0)
  74 #endif
  75
  76 #define ag71xx_assert(_cond)                                            \
  77 do {                                                                    \
  78         if (_cond)                                                      \
  79                 break;                                                  \
  80         printk("%s,%d: assertion failed\n", __FILE__, __LINE__);        \
  81         BUG();                                                          \
  82 } while (0)
  83
  84 struct ag71xx_desc {
  85         u32     data;
  86         u32     ctrl;
  87 #define DESC_EMPTY      BIT(31)
  88 #define DESC_MORE       BIT(24)
  89 #define DESC_PKTLEN_M   0x1fff
  90         u32     next;
  91 };
  92
  93 struct ag71xx_buf {
  94         struct sk_buff  *skb;
  95 };
  96
  97 struct ag71xx_ring {
  98         struct ag71xx_buf       *buf;
  99         struct ag71xx_desc      *descs;
 100         dma_addr_t              descs_dma;
 101         unsigned int            curr;
 102         unsigned int            dirty;
 103         unsigned int            size;
 104 };
 105
 106 struct ag71xx {
 107         void __iomem            *mac_base;
 108         void __iomem            *mii_ctrl;
 109
 110         spinlock_t              lock;
 111         struct platform_device  *pdev;
 112         struct net_device       *dev;
 113         struct napi_struct      napi;
 114
 115         struct ag71xx_ring      rx_ring;
 116         struct ag71xx_ring      tx_ring;
 117
 118         struct phy_device       *phy_dev;
 119         struct mii_bus          mii_bus;
 120
 121         unsigned int            link;
 122         unsigned int            speed;
 123         int                     duplex;
 124 };
 125
 126 extern struct ethtool_ops ag71xx_ethtool_ops;
 127
 128 extern int ag71xx_mdio_init(struct ag71xx *ag, int id);
 129 extern void ag71xx_mdio_cleanup(struct ag71xx *ag);
 130 extern int ag71xx_mii_peek(struct ag71xx *ag);
 131 extern void ag71xx_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if);
 132 extern void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, unsigned int speed);
 133 extern void ag71xx_link_update(struct ag71xx *ag);
 134
 135 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
 136 {
 137         return ag->pdev->dev.platform_data;
 138 }
 139
 140 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 141 {
 142         __raw_writel(value, ag->mac_base + reg);
 143 }
 144
 145 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 146 {
 147         return __raw_readl(ag->mac_base + reg);
 148 }
 149
 150 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
 151 {
 152         void __iomem *r = ag->mac_base + reg;
 153
 154         __raw_writel(__raw_readl(r) | mask, r);
 155 }
 156
 157 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
 158 {
 159         void __iomem *r = ag->mac_base + reg;
 160
 161         __raw_writel(__raw_readl(r) & ~mask, r);
 162 }
 163
 164 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
 165 {
 166         return ((desc->ctrl & DESC_EMPTY) != 0);
 167 }
 168
 169 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 170 {
 171         return (desc->ctrl & DESC_PKTLEN_M);
 172 }
 173
 174 /* Register offsets */
 175 #define AG71XX_REG_MAC_CFG1     0x0000
 176 #define AG71XX_REG_MAC_CFG2     0x0004
 177 #define AG71XX_REG_MAC_IPG      0x0008
 178 #define AG71XX_REG_MAC_HDX      0x000c
 179 #define AG71XX_REG_MAC_MFL      0x0010
 180 #define AG71XX_REG_MII_CFG      0x0020
 181 #define AG71XX_REG_MII_CMD      0x0024
 182 #define AG71XX_REG_MII_ADDR     0x0028
 183 #define AG71XX_REG_MII_CTRL     0x002c
 184 #define AG71XX_REG_MII_STATUS   0x0030
 185 #define AG71XX_REG_MII_IND      0x0034
 186 #define AG71XX_REG_MAC_IFCTL    0x0038
 187 #define AG71XX_REG_MAC_ADDR1    0x0040
 188 #define AG71XX_REG_MAC_ADDR2    0x0044
 189 #define AG71XX_REG_FIFO_CFG0    0x0048
 190 #define AG71XX_REG_FIFO_CFG1    0x004c
 191 #define AG71XX_REG_FIFO_CFG2    0x0050
 192 #define AG71XX_REG_FIFO_CFG3    0x0054
 193 #define AG71XX_REG_FIFO_CFG4    0x0058
 194 #define AG71XX_REG_FIFO_CFG5    0x005c
 195 #define AG71XX_REG_FIFO_RAM0    0x0060
 196 #define AG71XX_REG_FIFO_RAM1    0x0064
 197 #define AG71XX_REG_FIFO_RAM2    0x0068
 198 #define AG71XX_REG_FIFO_RAM3    0x006c
 199 #define AG71XX_REG_FIFO_RAM4    0x0070
 200 #define AG71XX_REG_FIFO_RAM5    0x0074
 201 #define AG71XX_REG_FIFO_RAM6    0x0078
 202 #define AG71XX_REG_FIFO_RAM7    0x007c
 203
 204 #define AG71XX_REG_TX_CTRL      0x0180
 205 #define AG71XX_REG_TX_DESC      0x0184
 206 #define AG71XX_REG_TX_STATUS    0x0188
 207 #define AG71XX_REG_RX_CTRL      0x018c
 208 #define AG71XX_REG_RX_DESC      0x0190
 209 #define AG71XX_REG_RX_STATUS    0x0194
 210 #define AG71XX_REG_INT_ENABLE   0x0198
 211 #define AG71XX_REG_INT_STATUS   0x019c
 212
 213 #define MAC_CFG1_TXE            BIT(0)
 214 #define MAC_CFG1_STX            BIT(1)
 215 #define MAC_CFG1_RXE            BIT(2)
 216 #define MAC_CFG1_SRX            BIT(3)
 217 #define MAC_CFG1_LB             BIT(8)
 218 #define MAC_CFG1_SR             BIT(31)
 219
 220 #define MAC_CFG2_FDX            BIT(0)
 221 #define MAC_CFG2_CRC_EN         BIT(1)
 222 #define MAC_CFG2_PAD_CRC_EN     BIT(2)
 223 #define MAC_CFG2_LEN_CHECK      BIT(4)
 224 #define MAC_CFG2_HUGE_FRAME_EN  BIT(5)
 225 #define MAC_CFG2_IF_1000        BIT(9)
 226 #define MAC_CFG2_IF_10_100      BIT(8)
 227
 228 #define AG71XX_INT_TX_PS        BIT(0)
 229 #define AG71XX_INT_TX_UR        BIT(1)
 230 #define AG71XX_INT_TX_BE        BIT(3)
 231 #define AG71XX_INT_RX_PR        BIT(4)
 232 #define AG71XX_INT_RX_OF        BIT(6)
 233 #define AG71XX_INT_RX_BE        BIT(7)
 234
 235 #define MAC_IFCTL_SPEED         BIT(16)
 236
 237 #define MII_CFG_CLK_DIV_4       0
 238 #define MII_CFG_CLK_DIV_6       2
 239 #define MII_CFG_CLK_DIV_8       3
 240 #define MII_CFG_CLK_DIV_10      4
 241 #define MII_CFG_CLK_DIV_14      5
 242 #define MII_CFG_CLK_DIV_20      6
 243 #define MII_CFG_CLK_DIV_28      7
 244
 245 #define MII_CMD_WRITE           0x0
 246 #define MII_CMD_READ            0x1
 247 #define MII_ADDR_S              8
 248 #define MII_IND_BUSY            BIT(0)
 249 #define MII_IND_INVALID         BIT(2)
 250
 251 #define TX_CTRL_TXE             BIT(0)
 252
 253 #define TX_STATUS_PS            BIT(0)
 254 #define TX_STATUS_UR            BIT(1)
 255 #define TX_STATUS_BE            BIT(3)
 256
 257 #define RX_CTRL_RXE             BIT(0)
 258
 259 #define RX_STATUS_PR            BIT(0)
 260 #define RX_STATUS_OF            BIT(1)
 261 #define RX_STATUS_BE            BIT(3)
 262
 263 #define FIFO_CFG5_BYTE_PER_CLK  BIT(19)
 264
 265 #define MII_CTRL_SPEED_S        4
 266 #define MII_CTRL_SPEED_M        3
 267 #define MII_CTRL_SPEED_10       0
 268 #define MII_CTRL_SPEED_100      1
 269 #define MII_CTRL_SPEED_1000     2
 270
 271 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
 272 {
 273         ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
 274 }
 275
 276 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 277 {
 278         ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
 279 }
 280
 281 #endif /* _AG71XX_H */