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ag71xx driver: rename ag71xx_debug module parameter
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/cache.h>
15 #include "ag71xx.h"
16
17 #define AG71XX_DEFAULT_MSG_ENABLE \
18 ( NETIF_MSG_DRV \
19 | NETIF_MSG_PROBE \
20 | NETIF_MSG_LINK \
21 | NETIF_MSG_TIMER \
22 | NETIF_MSG_IFDOWN \
23 | NETIF_MSG_IFUP \
24 | NETIF_MSG_RX_ERR \
25 | NETIF_MSG_TX_ERR )
26
27 static int ag71xx_msg_level = -1;
28
29 module_param_named(msg_level, ag71xx_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31
32 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 {
34 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag->dev->name,
36 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
37 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
38 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39
40 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
45 }
46
47 static void ag71xx_dump_regs(struct ag71xx *ag)
48 {
49 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
52 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
53 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
54 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
55 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
56 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag->dev->name,
58 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
60 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
61 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag->dev->name,
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
65 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
66 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag->dev->name,
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
71 }
72
73 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 {
75 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
76 ag->dev->name, label, intr,
77 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
78 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
79 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
80 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
81 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
82 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
83 }
84
85 static void ag71xx_ring_free(struct ag71xx_ring *ring)
86 {
87 kfree(ring->buf);
88
89 if (ring->descs_cpu)
90 dma_free_coherent(NULL, ring->size * ring->desc_size,
91 ring->descs_cpu, ring->descs_dma);
92 }
93
94 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
95 {
96 int err;
97 int i;
98
99 ring->desc_size = sizeof(struct ag71xx_desc);
100 if (ring->desc_size % cache_line_size()) {
101 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
102 ring, ring->desc_size,
103 roundup(ring->desc_size, cache_line_size()));
104 ring->desc_size = roundup(ring->desc_size, cache_line_size());
105 }
106
107 ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
108 &ring->descs_dma, GFP_ATOMIC);
109 if (!ring->descs_cpu) {
110 err = -ENOMEM;
111 goto err;
112 }
113
114 ring->size = size;
115
116 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
117 if (!ring->buf) {
118 err = -ENOMEM;
119 goto err;
120 }
121
122 for (i = 0; i < size; i++) {
123 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
124 DBG("ag71xx: ring %p, desc %d at %p\n",
125 ring, i, ring->buf[i].desc);
126 }
127
128 return 0;
129
130 err:
131 return err;
132 }
133
134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
135 {
136 struct ag71xx_ring *ring = &ag->tx_ring;
137 struct net_device *dev = ag->dev;
138
139 while (ring->curr != ring->dirty) {
140 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
141
142 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143 ring->buf[i].desc->ctrl = 0;
144 dev->stats.tx_errors++;
145 }
146
147 if (ring->buf[i].skb)
148 dev_kfree_skb_any(ring->buf[i].skb);
149
150 ring->buf[i].skb = NULL;
151
152 ring->dirty++;
153 }
154
155 /* flush descriptors */
156 wmb();
157
158 }
159
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
161 {
162 struct ag71xx_ring *ring = &ag->tx_ring;
163 int i;
164
165 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
166 ring->buf[i].desc->next = (u32) (ring->descs_dma +
167 ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
168
169 ring->buf[i].desc->ctrl = DESC_EMPTY;
170 ring->buf[i].skb = NULL;
171 }
172
173 /* flush descriptors */
174 wmb();
175
176 ring->curr = 0;
177 ring->dirty = 0;
178 }
179
180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
181 {
182 struct ag71xx_ring *ring = &ag->rx_ring;
183 int i;
184
185 if (!ring->buf)
186 return;
187
188 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
189 if (ring->buf[i].skb)
190 kfree_skb(ring->buf[i].skb);
191
192 }
193
194 static int ag71xx_ring_rx_init(struct ag71xx *ag)
195 {
196 struct ag71xx_ring *ring = &ag->rx_ring;
197 unsigned int i;
198 int ret;
199
200 ret = 0;
201 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
202 ring->buf[i].desc->next = (u32) (ring->descs_dma +
203 ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
204
205 DBG("ag71xx: RX desc at %p, next is %08x\n",
206 ring->buf[i].desc,
207 ring->buf[i].desc->next);
208 }
209
210 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
211 struct sk_buff *skb;
212
213 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
214 if (!skb) {
215 ret = -ENOMEM;
216 break;
217 }
218
219 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
220 DMA_FROM_DEVICE);
221
222 skb->dev = ag->dev;
223 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
224
225 ring->buf[i].skb = skb;
226 ring->buf[i].desc->data = virt_to_phys(skb->data);
227 ring->buf[i].desc->ctrl = DESC_EMPTY;
228 }
229
230 /* flush descriptors */
231 wmb();
232
233 ring->curr = 0;
234 ring->dirty = 0;
235
236 return ret;
237 }
238
239 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
240 {
241 struct ag71xx_ring *ring = &ag->rx_ring;
242 unsigned int count;
243
244 count = 0;
245 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
246 unsigned int i;
247
248 i = ring->dirty % AG71XX_RX_RING_SIZE;
249
250 if (ring->buf[i].skb == NULL) {
251 struct sk_buff *skb;
252
253 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
254 if (skb == NULL)
255 break;
256
257 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
258 DMA_FROM_DEVICE);
259
260 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
261 skb->dev = ag->dev;
262
263 ring->buf[i].skb = skb;
264 ring->buf[i].desc->data = virt_to_phys(skb->data);
265 }
266
267 ring->buf[i].desc->ctrl = DESC_EMPTY;
268 count++;
269 }
270
271 /* flush descriptors */
272 wmb();
273
274 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
275
276 return count;
277 }
278
279 static int ag71xx_rings_init(struct ag71xx *ag)
280 {
281 int ret;
282
283 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
284 if (ret)
285 return ret;
286
287 ag71xx_ring_tx_init(ag);
288
289 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
290 if (ret)
291 return ret;
292
293 ret = ag71xx_ring_rx_init(ag);
294 return ret;
295 }
296
297 static void ag71xx_rings_cleanup(struct ag71xx *ag)
298 {
299 ag71xx_ring_rx_clean(ag);
300 ag71xx_ring_free(&ag->rx_ring);
301
302 ag71xx_ring_tx_clean(ag);
303 ag71xx_ring_free(&ag->tx_ring);
304 }
305
306 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
307 {
308 u32 t;
309
310 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
311 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
312
313 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
314
315 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
316 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
317 }
318
319 static void ag71xx_dma_reset(struct ag71xx *ag)
320 {
321 int i;
322
323 ag71xx_dump_dma_regs(ag);
324
325 /* stop RX and TX */
326 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
327 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
328
329 /* clear descriptor addresses */
330 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
331 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
332
333 /* clear pending RX/TX interrupts */
334 for (i = 0; i < 256; i++) {
335 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
336 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
337 }
338
339 /* clear pending errors */
340 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
341 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
342
343 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
344 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
345 ag->dev->name);
346
347 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
348 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
349 ag->dev->name);
350
351 ag71xx_dump_dma_regs(ag);
352 }
353
354 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
355 MAC_CFG1_SRX | MAC_CFG1_STX)
356
357 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
358
359 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
360 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
361 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
362 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
363 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
364 FIFO_CFG4_VT)
365
366 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
367 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
368 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
369 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
370 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
371 FIFO_CFG5_17 | FIFO_CFG5_SF)
372
373 static void ag71xx_hw_init(struct ag71xx *ag)
374 {
375 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
376
377 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
378 udelay(20);
379
380 ar71xx_device_stop(pdata->reset_bit);
381 mdelay(100);
382 ar71xx_device_start(pdata->reset_bit);
383 mdelay(100);
384
385 /* setup MAC configuration registers */
386 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
387 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
388 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
389
390 /* setup max frame length */
391 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
392
393 /* setup MII interface type */
394 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
395
396 /* setup FIFO configuration registers */
397 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
398 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
399 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
400 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
401 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
402
403 ag71xx_dma_reset(ag);
404 }
405
406 static void ag71xx_hw_start(struct ag71xx *ag)
407 {
408 /* start RX engine */
409 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
410
411 /* enable interrupts */
412 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
413 }
414
415 static void ag71xx_hw_stop(struct ag71xx *ag)
416 {
417 /* disable all interrupts */
418 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
419
420 ag71xx_dma_reset(ag);
421 }
422
423 static int ag71xx_open(struct net_device *dev)
424 {
425 struct ag71xx *ag = netdev_priv(dev);
426 int ret;
427
428 ret = ag71xx_rings_init(ag);
429 if (ret)
430 goto err;
431
432 napi_enable(&ag->napi);
433
434 netif_carrier_off(dev);
435 ag71xx_phy_start(ag);
436
437 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
438 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
439
440 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
441
442 ag71xx_hw_start(ag);
443
444 netif_start_queue(dev);
445
446 return 0;
447
448 err:
449 ag71xx_rings_cleanup(ag);
450 return ret;
451 }
452
453 static int ag71xx_stop(struct net_device *dev)
454 {
455 struct ag71xx *ag = netdev_priv(dev);
456 unsigned long flags;
457
458 spin_lock_irqsave(&ag->lock, flags);
459
460 netif_stop_queue(dev);
461
462 ag71xx_hw_stop(ag);
463
464 netif_carrier_off(dev);
465 ag71xx_phy_stop(ag);
466
467 napi_disable(&ag->napi);
468 del_timer_sync(&ag->oom_timer);
469
470 spin_unlock_irqrestore(&ag->lock, flags);
471
472 ag71xx_rings_cleanup(ag);
473
474 return 0;
475 }
476
477 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
478 {
479 struct ag71xx *ag = netdev_priv(dev);
480 struct ag71xx_ring *ring = &ag->tx_ring;
481 struct ag71xx_desc *desc;
482 int i;
483
484 i = ring->curr % AG71XX_TX_RING_SIZE;
485 desc = ring->buf[i].desc;
486
487 if (!ag71xx_desc_empty(desc))
488 goto err_drop;
489
490 ag71xx_add_ar8216_header(ag, skb);
491
492 if (skb->len <= 0) {
493 DBG("%s: packet len is too small\n", ag->dev->name);
494 goto err_drop;
495 }
496
497 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
498
499 ring->buf[i].skb = skb;
500
501 /* setup descriptor fields */
502 desc->data = virt_to_phys(skb->data);
503 desc->ctrl = (skb->len & DESC_PKTLEN_M);
504
505 /* flush descriptor */
506 wmb();
507
508 ring->curr++;
509 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
510 DBG("%s: tx queue full\n", ag->dev->name);
511 netif_stop_queue(dev);
512 }
513
514 DBG("%s: packet injected into TX queue\n", ag->dev->name);
515
516 /* enable TX engine */
517 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
518
519 dev->trans_start = jiffies;
520
521 return 0;
522
523 err_drop:
524 dev->stats.tx_dropped++;
525
526 dev_kfree_skb(skb);
527 return 0;
528 }
529
530 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
531 {
532 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
533 struct ag71xx *ag = netdev_priv(dev);
534 int ret;
535
536 switch (cmd) {
537 case SIOCETHTOOL:
538 if (ag->phy_dev == NULL)
539 break;
540
541 spin_lock_irq(&ag->lock);
542 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
543 spin_unlock_irq(&ag->lock);
544 return ret;
545
546 case SIOCSIFHWADDR:
547 if (copy_from_user
548 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
549 return -EFAULT;
550 return 0;
551
552 case SIOCGIFHWADDR:
553 if (copy_to_user
554 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
555 return -EFAULT;
556 return 0;
557
558 case SIOCGMIIPHY:
559 case SIOCGMIIREG:
560 case SIOCSMIIREG:
561 if (ag->phy_dev == NULL)
562 break;
563
564 return phy_mii_ioctl(ag->phy_dev, data, cmd);
565
566 default:
567 break;
568 }
569
570 return -EOPNOTSUPP;
571 }
572
573 static void ag71xx_oom_timer_handler(unsigned long data)
574 {
575 struct net_device *dev = (struct net_device *) data;
576 struct ag71xx *ag = netdev_priv(dev);
577
578 netif_rx_schedule(dev, &ag->napi);
579 }
580
581 static void ag71xx_tx_timeout(struct net_device *dev)
582 {
583 struct ag71xx *ag = netdev_priv(dev);
584
585 if (netif_msg_tx_err(ag))
586 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
587
588 schedule_work(&ag->restart_work);
589 }
590
591 static void ag71xx_restart_work_func(struct work_struct *work)
592 {
593 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
594
595 ag71xx_stop(ag->dev);
596 ag71xx_open(ag->dev);
597 }
598
599 static void ag71xx_tx_packets(struct ag71xx *ag)
600 {
601 struct ag71xx_ring *ring = &ag->tx_ring;
602 unsigned int sent;
603
604 DBG("%s: processing TX ring\n", ag->dev->name);
605
606 sent = 0;
607 while (ring->dirty != ring->curr) {
608 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
609 struct ag71xx_desc *desc = ring->buf[i].desc;
610 struct sk_buff *skb = ring->buf[i].skb;
611
612 if (!ag71xx_desc_empty(desc))
613 break;
614
615 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
616
617 ag->dev->stats.tx_bytes += skb->len;
618 ag->dev->stats.tx_packets++;
619
620 dev_kfree_skb_any(skb);
621 ring->buf[i].skb = NULL;
622
623 ring->dirty++;
624 sent++;
625 }
626
627 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
628
629 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
630 netif_wake_queue(ag->dev);
631
632 }
633
634 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
635 {
636 struct net_device *dev = ag->dev;
637 struct ag71xx_ring *ring = &ag->rx_ring;
638 int done = 0;
639
640 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
641 dev->name, limit, ring->curr, ring->dirty);
642
643 while (done < limit) {
644 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
645 struct ag71xx_desc *desc = ring->buf[i].desc;
646 struct sk_buff *skb;
647 int pktlen;
648
649 if (ag71xx_desc_empty(desc))
650 break;
651
652 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
653 ag71xx_assert(0);
654 break;
655 }
656
657 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
658
659 skb = ring->buf[i].skb;
660 pktlen = ag71xx_desc_pktlen(desc);
661 pktlen -= ETH_FCS_LEN;
662
663 skb_put(skb, pktlen);
664
665 skb->dev = dev;
666 skb->ip_summed = CHECKSUM_NONE;
667
668 dev->last_rx = jiffies;
669 dev->stats.rx_packets++;
670 dev->stats.rx_bytes += pktlen;
671
672 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
673 dev->stats.rx_dropped++;
674 kfree_skb(skb);
675 } else {
676 skb->protocol = eth_type_trans(skb, dev);
677 netif_receive_skb(skb);
678 }
679
680 ring->buf[i].skb = NULL;
681 done++;
682
683 ring->curr++;
684 }
685
686 ag71xx_ring_rx_refill(ag);
687
688 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
689 dev->name, ring->curr, ring->dirty, done);
690
691 return done;
692 }
693
694 static int ag71xx_poll(struct napi_struct *napi, int limit)
695 {
696 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
697 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
698 struct net_device *dev = ag->dev;
699 struct ag71xx_ring *rx_ring;
700 unsigned long flags;
701 u32 status;
702 int done;
703
704 pdata->ddr_flush();
705 ag71xx_tx_packets(ag);
706
707 DBG("%s: processing RX ring\n", dev->name);
708 done = ag71xx_rx_packets(ag, limit);
709
710 rx_ring = &ag->rx_ring;
711 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
712 goto oom;
713
714 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
715 if (unlikely(status & RX_STATUS_OF)) {
716 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
717 dev->stats.rx_fifo_errors++;
718
719 /* restart RX */
720 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
721 }
722
723 if (done < limit) {
724 if (status & RX_STATUS_PR)
725 goto more;
726
727 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
728 if (status & TX_STATUS_PS)
729 goto more;
730
731 DBG("%s: disable polling mode, done=%d, limit=%d\n",
732 dev->name, done, limit);
733
734 netif_rx_complete(dev, napi);
735
736 /* enable interrupts */
737 spin_lock_irqsave(&ag->lock, flags);
738 ag71xx_int_enable(ag, AG71XX_INT_POLL);
739 spin_unlock_irqrestore(&ag->lock, flags);
740 return done;
741 }
742
743 more:
744 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
745 dev->name, done, limit);
746 return done;
747
748 oom:
749 if (netif_msg_rx_err(ag))
750 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
751
752 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
753 netif_rx_complete(dev, napi);
754 return 0;
755 }
756
757 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
758 {
759 struct net_device *dev = dev_id;
760 struct ag71xx *ag = netdev_priv(dev);
761 u32 status;
762
763 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
764 ag71xx_dump_intr(ag, "raw", status);
765
766 if (unlikely(!status))
767 return IRQ_NONE;
768
769 if (unlikely(status & AG71XX_INT_ERR)) {
770 if (status & AG71XX_INT_TX_BE) {
771 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
772 dev_err(&dev->dev, "TX BUS error\n");
773 }
774 if (status & AG71XX_INT_RX_BE) {
775 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
776 dev_err(&dev->dev, "RX BUS error\n");
777 }
778 }
779
780 if (likely(status & AG71XX_INT_POLL)) {
781 ag71xx_int_disable(ag, AG71XX_INT_POLL);
782 DBG("%s: enable polling mode\n", dev->name);
783 netif_rx_schedule(dev, &ag->napi);
784 }
785
786 return IRQ_HANDLED;
787 }
788
789 static void ag71xx_set_multicast_list(struct net_device *dev)
790 {
791 /* TODO */
792 }
793
794 static int __init ag71xx_probe(struct platform_device *pdev)
795 {
796 struct net_device *dev;
797 struct resource *res;
798 struct ag71xx *ag;
799 struct ag71xx_platform_data *pdata;
800 int err;
801
802 pdata = pdev->dev.platform_data;
803 if (!pdata) {
804 dev_err(&pdev->dev, "no platform data specified\n");
805 err = -ENXIO;
806 goto err_out;
807 }
808
809 dev = alloc_etherdev(sizeof(*ag));
810 if (!dev) {
811 dev_err(&pdev->dev, "alloc_etherdev failed\n");
812 err = -ENOMEM;
813 goto err_out;
814 }
815
816 SET_NETDEV_DEV(dev, &pdev->dev);
817
818 ag = netdev_priv(dev);
819 ag->pdev = pdev;
820 ag->dev = dev;
821 ag->mii_bus = ag71xx_mdio_bus->mii_bus;
822 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
823 AG71XX_DEFAULT_MSG_ENABLE);
824 spin_lock_init(&ag->lock);
825
826 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
827 if (!res) {
828 dev_err(&pdev->dev, "no mac_base resource found\n");
829 err = -ENXIO;
830 goto err_out;
831 }
832
833 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
834 if (!ag->mac_base) {
835 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
836 err = -ENOMEM;
837 goto err_free_dev;
838 }
839
840 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
841 if (!res) {
842 dev_err(&pdev->dev, "no mac_base2 resource found\n");
843 err = -ENXIO;
844 goto err_unmap_base1;
845 }
846
847 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
848 if (!ag->mac_base) {
849 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
850 err = -ENOMEM;
851 goto err_unmap_base1;
852 }
853
854 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
855 if (!res) {
856 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
857 err = -ENXIO;
858 goto err_unmap_base2;
859 }
860
861 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
862 if (!ag->mii_ctrl) {
863 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
864 err = -ENOMEM;
865 goto err_unmap_base2;
866 }
867
868 dev->irq = platform_get_irq(pdev, 0);
869 err = request_irq(dev->irq, ag71xx_interrupt,
870 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
871 dev->name, dev);
872 if (err) {
873 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
874 goto err_unmap_mii_ctrl;
875 }
876
877 dev->base_addr = (unsigned long)ag->mac_base;
878 dev->open = ag71xx_open;
879 dev->stop = ag71xx_stop;
880 dev->hard_start_xmit = ag71xx_hard_start_xmit;
881 dev->set_multicast_list = ag71xx_set_multicast_list;
882 dev->do_ioctl = ag71xx_do_ioctl;
883 dev->ethtool_ops = &ag71xx_ethtool_ops;
884
885 dev->tx_timeout = ag71xx_tx_timeout;
886 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
887
888 init_timer(&ag->oom_timer);
889 ag->oom_timer.data = (unsigned long) dev;
890 ag->oom_timer.function = ag71xx_oom_timer_handler;
891
892 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
893
894 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
895
896 err = register_netdev(dev);
897 if (err) {
898 dev_err(&pdev->dev, "unable to register net device\n");
899 goto err_free_irq;
900 }
901
902 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
903 dev->name, dev->base_addr, dev->irq);
904
905 ag71xx_dump_regs(ag);
906
907 ag71xx_hw_init(ag);
908
909 ag71xx_dump_regs(ag);
910
911 /* Reset the mdio bus explicitly */
912 if (ag->mii_bus) {
913 mutex_lock(&ag->mii_bus->mdio_lock);
914 ag->mii_bus->reset(ag->mii_bus);
915 mutex_unlock(&ag->mii_bus->mdio_lock);
916 }
917
918 err = ag71xx_phy_connect(ag);
919 if (err)
920 goto err_unregister_netdev;
921
922 platform_set_drvdata(pdev, dev);
923
924 return 0;
925
926 err_unregister_netdev:
927 unregister_netdev(dev);
928 err_free_irq:
929 free_irq(dev->irq, dev);
930 err_unmap_mii_ctrl:
931 iounmap(ag->mii_ctrl);
932 err_unmap_base2:
933 iounmap(ag->mac_base2);
934 err_unmap_base1:
935 iounmap(ag->mac_base);
936 err_free_dev:
937 kfree(dev);
938 err_out:
939 platform_set_drvdata(pdev, NULL);
940 return err;
941 }
942
943 static int __exit ag71xx_remove(struct platform_device *pdev)
944 {
945 struct net_device *dev = platform_get_drvdata(pdev);
946
947 if (dev) {
948 struct ag71xx *ag = netdev_priv(dev);
949
950 ag71xx_phy_disconnect(ag);
951 unregister_netdev(dev);
952 free_irq(dev->irq, dev);
953 iounmap(ag->mii_ctrl);
954 iounmap(ag->mac_base2);
955 iounmap(ag->mac_base);
956 kfree(dev);
957 platform_set_drvdata(pdev, NULL);
958 }
959
960 return 0;
961 }
962
963 static struct platform_driver ag71xx_driver = {
964 .probe = ag71xx_probe,
965 .remove = __exit_p(ag71xx_remove),
966 .driver = {
967 .name = AG71XX_DRV_NAME,
968 }
969 };
970
971 static int __init ag71xx_module_init(void)
972 {
973 int ret;
974
975 ret = ag71xx_mdio_driver_init();
976 if (ret)
977 goto err_out;
978
979 ret = platform_driver_register(&ag71xx_driver);
980 if (ret)
981 goto err_mdio_exit;
982
983 return 0;
984
985 err_mdio_exit:
986 ag71xx_mdio_driver_exit();
987 err_out:
988 return ret;
989 }
990
991 static void __exit ag71xx_module_exit(void)
992 {
993 platform_driver_unregister(&ag71xx_driver);
994 ag71xx_mdio_driver_exit();
995 }
996
997 module_init(ag71xx_module_init);
998 module_exit(ag71xx_module_exit);
999
1000 MODULE_VERSION(AG71XX_DRV_VERSION);
1001 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1002 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1003 MODULE_LICENSE("GPL v2");
1004 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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