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ar71xx: add support for external mii_bus
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/cache.h>
15 #include "ag71xx.h"
16
17 #define AG71XX_DEFAULT_MSG_ENABLE \
18 ( NETIF_MSG_DRV \
19 | NETIF_MSG_PROBE \
20 | NETIF_MSG_LINK \
21 | NETIF_MSG_TIMER \
22 | NETIF_MSG_IFDOWN \
23 | NETIF_MSG_IFUP \
24 | NETIF_MSG_RX_ERR \
25 | NETIF_MSG_TX_ERR )
26
27 static int ag71xx_msg_level = -1;
28
29 module_param_named(msg_level, ag71xx_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31
32 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 {
34 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag->dev->name,
36 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
37 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
38 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39
40 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
45 }
46
47 static void ag71xx_dump_regs(struct ag71xx *ag)
48 {
49 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
52 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
53 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
54 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
55 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
56 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag->dev->name,
58 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
60 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
61 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag->dev->name,
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
65 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
66 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag->dev->name,
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
71 }
72
73 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 {
75 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
76 ag->dev->name, label, intr,
77 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
78 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
79 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
80 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
81 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
82 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
83 }
84
85 static void ag71xx_ring_free(struct ag71xx_ring *ring)
86 {
87 kfree(ring->buf);
88
89 if (ring->descs_cpu)
90 dma_free_coherent(NULL, ring->size * ring->desc_size,
91 ring->descs_cpu, ring->descs_dma);
92 }
93
94 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
95 {
96 int err;
97 int i;
98
99 ring->desc_size = sizeof(struct ag71xx_desc);
100 if (ring->desc_size % cache_line_size()) {
101 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
102 ring, ring->desc_size,
103 roundup(ring->desc_size, cache_line_size()));
104 ring->desc_size = roundup(ring->desc_size, cache_line_size());
105 }
106
107 ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
108 &ring->descs_dma, GFP_ATOMIC);
109 if (!ring->descs_cpu) {
110 err = -ENOMEM;
111 goto err;
112 }
113
114 ring->size = size;
115
116 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
117 if (!ring->buf) {
118 err = -ENOMEM;
119 goto err;
120 }
121
122 for (i = 0; i < size; i++) {
123 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
124 DBG("ag71xx: ring %p, desc %d at %p\n",
125 ring, i, ring->buf[i].desc);
126 }
127
128 return 0;
129
130 err:
131 return err;
132 }
133
134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
135 {
136 struct ag71xx_ring *ring = &ag->tx_ring;
137 struct net_device *dev = ag->dev;
138
139 while (ring->curr != ring->dirty) {
140 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
141
142 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143 ring->buf[i].desc->ctrl = 0;
144 dev->stats.tx_errors++;
145 }
146
147 if (ring->buf[i].skb)
148 dev_kfree_skb_any(ring->buf[i].skb);
149
150 ring->buf[i].skb = NULL;
151
152 ring->dirty++;
153 }
154
155 /* flush descriptors */
156 wmb();
157
158 }
159
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
161 {
162 struct ag71xx_ring *ring = &ag->tx_ring;
163 int i;
164
165 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
166 ring->buf[i].desc->next = (u32) (ring->descs_dma +
167 ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
168
169 ring->buf[i].desc->ctrl = DESC_EMPTY;
170 ring->buf[i].skb = NULL;
171 }
172
173 /* flush descriptors */
174 wmb();
175
176 ring->curr = 0;
177 ring->dirty = 0;
178 }
179
180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
181 {
182 struct ag71xx_ring *ring = &ag->rx_ring;
183 int i;
184
185 if (!ring->buf)
186 return;
187
188 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
189 if (ring->buf[i].skb)
190 kfree_skb(ring->buf[i].skb);
191
192 }
193
194 static int ag71xx_ring_rx_init(struct ag71xx *ag)
195 {
196 struct ag71xx_ring *ring = &ag->rx_ring;
197 unsigned int i;
198 int ret;
199
200 ret = 0;
201 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
202 ring->buf[i].desc->next = (u32) (ring->descs_dma +
203 ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
204
205 DBG("ag71xx: RX desc at %p, next is %08x\n",
206 ring->buf[i].desc,
207 ring->buf[i].desc->next);
208 }
209
210 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
211 struct sk_buff *skb;
212
213 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
214 if (!skb) {
215 ret = -ENOMEM;
216 break;
217 }
218
219 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
220 DMA_FROM_DEVICE);
221
222 skb->dev = ag->dev;
223 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
224
225 ring->buf[i].skb = skb;
226 ring->buf[i].desc->data = virt_to_phys(skb->data);
227 ring->buf[i].desc->ctrl = DESC_EMPTY;
228 }
229
230 /* flush descriptors */
231 wmb();
232
233 ring->curr = 0;
234 ring->dirty = 0;
235
236 return ret;
237 }
238
239 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
240 {
241 struct ag71xx_ring *ring = &ag->rx_ring;
242 unsigned int count;
243
244 count = 0;
245 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
246 unsigned int i;
247
248 i = ring->dirty % AG71XX_RX_RING_SIZE;
249
250 if (ring->buf[i].skb == NULL) {
251 struct sk_buff *skb;
252
253 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
254 if (skb == NULL)
255 break;
256
257 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
258 DMA_FROM_DEVICE);
259
260 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
261 skb->dev = ag->dev;
262
263 ring->buf[i].skb = skb;
264 ring->buf[i].desc->data = virt_to_phys(skb->data);
265 }
266
267 ring->buf[i].desc->ctrl = DESC_EMPTY;
268 count++;
269 }
270
271 /* flush descriptors */
272 wmb();
273
274 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
275
276 return count;
277 }
278
279 static int ag71xx_rings_init(struct ag71xx *ag)
280 {
281 int ret;
282
283 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
284 if (ret)
285 return ret;
286
287 ag71xx_ring_tx_init(ag);
288
289 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
290 if (ret)
291 return ret;
292
293 ret = ag71xx_ring_rx_init(ag);
294 return ret;
295 }
296
297 static void ag71xx_rings_cleanup(struct ag71xx *ag)
298 {
299 ag71xx_ring_rx_clean(ag);
300 ag71xx_ring_free(&ag->rx_ring);
301
302 ag71xx_ring_tx_clean(ag);
303 ag71xx_ring_free(&ag->tx_ring);
304 }
305
306 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
307 {
308 u32 t;
309
310 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
311 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
312
313 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
314
315 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
316 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
317 }
318
319 static void ag71xx_dma_reset(struct ag71xx *ag)
320 {
321 u32 val;
322 int i;
323
324 ag71xx_dump_dma_regs(ag);
325
326 /* stop RX and TX */
327 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
328 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
329
330 /* clear descriptor addresses */
331 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
332 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
333
334 /* clear pending RX/TX interrupts */
335 for (i = 0; i < 256; i++) {
336 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
337 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
338 }
339
340 /* clear pending errors */
341 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
342 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
343
344 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
345 if (val)
346 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
347 ag->dev->name, val);
348
349 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
350
351 /* mask out reserved bits */
352 val &= ~0xff000000;
353
354 if (val)
355 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
356 ag->dev->name, val);
357
358 ag71xx_dump_dma_regs(ag);
359 }
360
361 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
362 MAC_CFG1_SRX | MAC_CFG1_STX)
363
364 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
365
366 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
367 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
368 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
369 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
370 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
371 FIFO_CFG4_VT)
372
373 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
374 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
375 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
376 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
377 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
378 FIFO_CFG5_17 | FIFO_CFG5_SF)
379
380 static void ag71xx_hw_init(struct ag71xx *ag)
381 {
382 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
383
384 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
385 udelay(20);
386
387 ar71xx_device_stop(pdata->reset_bit);
388 mdelay(100);
389 ar71xx_device_start(pdata->reset_bit);
390 mdelay(100);
391
392 /* setup MAC configuration registers */
393 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
394 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
395 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
396
397 /* setup max frame length */
398 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
399
400 /* setup MII interface type */
401 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
402
403 /* setup FIFO configuration registers */
404 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
405 if (pdata->is_ar724x) {
406 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
407 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
408 } else {
409 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
410 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
411 }
412 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
413 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
414
415 ag71xx_dma_reset(ag);
416 }
417
418 static void ag71xx_hw_start(struct ag71xx *ag)
419 {
420 /* start RX engine */
421 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
422
423 /* enable interrupts */
424 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
425 }
426
427 static void ag71xx_hw_stop(struct ag71xx *ag)
428 {
429 /* disable all interrupts */
430 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
431
432 ag71xx_dma_reset(ag);
433 }
434
435 static int ag71xx_open(struct net_device *dev)
436 {
437 struct ag71xx *ag = netdev_priv(dev);
438 int err;
439
440 err = ag71xx_phy_connect(ag);
441 if (err)
442 goto err;
443
444 err = ag71xx_rings_init(ag);
445 if (err)
446 goto err_ring_cleanup;
447
448 napi_enable(&ag->napi);
449
450 netif_carrier_off(dev);
451 ag71xx_phy_start(ag);
452
453 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
454 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
455
456 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
457
458 ag71xx_hw_start(ag);
459
460 netif_start_queue(dev);
461
462 return 0;
463
464 err_ring_cleanup:
465 ag71xx_rings_cleanup(ag);
466 err:
467 return err;
468 }
469
470 static int ag71xx_stop(struct net_device *dev)
471 {
472 struct ag71xx *ag = netdev_priv(dev);
473 unsigned long flags;
474
475 spin_lock_irqsave(&ag->lock, flags);
476
477 netif_stop_queue(dev);
478
479 ag71xx_hw_stop(ag);
480
481 netif_carrier_off(dev);
482 ag71xx_phy_stop(ag);
483
484 napi_disable(&ag->napi);
485 del_timer_sync(&ag->oom_timer);
486
487 spin_unlock_irqrestore(&ag->lock, flags);
488
489 ag71xx_rings_cleanup(ag);
490 ag71xx_phy_disconnect(ag);
491
492 return 0;
493 }
494
495 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
496 {
497 struct ag71xx *ag = netdev_priv(dev);
498 struct ag71xx_ring *ring = &ag->tx_ring;
499 struct ag71xx_desc *desc;
500 int i;
501
502 i = ring->curr % AG71XX_TX_RING_SIZE;
503 desc = ring->buf[i].desc;
504
505 if (!ag71xx_desc_empty(desc))
506 goto err_drop;
507
508 ag71xx_add_ar8216_header(ag, skb);
509
510 if (skb->len <= 0) {
511 DBG("%s: packet len is too small\n", ag->dev->name);
512 goto err_drop;
513 }
514
515 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
516
517 ring->buf[i].skb = skb;
518
519 /* setup descriptor fields */
520 desc->data = virt_to_phys(skb->data);
521 desc->ctrl = (skb->len & DESC_PKTLEN_M);
522
523 /* flush descriptor */
524 wmb();
525
526 ring->curr++;
527 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
528 DBG("%s: tx queue full\n", ag->dev->name);
529 netif_stop_queue(dev);
530 }
531
532 DBG("%s: packet injected into TX queue\n", ag->dev->name);
533
534 /* enable TX engine */
535 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
536
537 dev->trans_start = jiffies;
538
539 return 0;
540
541 err_drop:
542 dev->stats.tx_dropped++;
543
544 dev_kfree_skb(skb);
545 return 0;
546 }
547
548 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
549 {
550 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
551 struct ag71xx *ag = netdev_priv(dev);
552 int ret;
553
554 switch (cmd) {
555 case SIOCETHTOOL:
556 if (ag->phy_dev == NULL)
557 break;
558
559 spin_lock_irq(&ag->lock);
560 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
561 spin_unlock_irq(&ag->lock);
562 return ret;
563
564 case SIOCSIFHWADDR:
565 if (copy_from_user
566 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
567 return -EFAULT;
568 return 0;
569
570 case SIOCGIFHWADDR:
571 if (copy_to_user
572 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
573 return -EFAULT;
574 return 0;
575
576 case SIOCGMIIPHY:
577 case SIOCGMIIREG:
578 case SIOCSMIIREG:
579 if (ag->phy_dev == NULL)
580 break;
581
582 return phy_mii_ioctl(ag->phy_dev, data, cmd);
583
584 default:
585 break;
586 }
587
588 return -EOPNOTSUPP;
589 }
590
591 static void ag71xx_oom_timer_handler(unsigned long data)
592 {
593 struct net_device *dev = (struct net_device *) data;
594 struct ag71xx *ag = netdev_priv(dev);
595
596 netif_rx_schedule(dev, &ag->napi);
597 }
598
599 static void ag71xx_tx_timeout(struct net_device *dev)
600 {
601 struct ag71xx *ag = netdev_priv(dev);
602
603 if (netif_msg_tx_err(ag))
604 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
605
606 schedule_work(&ag->restart_work);
607 }
608
609 static void ag71xx_restart_work_func(struct work_struct *work)
610 {
611 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
612
613 ag71xx_stop(ag->dev);
614 ag71xx_open(ag->dev);
615 }
616
617 static void ag71xx_tx_packets(struct ag71xx *ag)
618 {
619 struct ag71xx_ring *ring = &ag->tx_ring;
620 unsigned int sent;
621
622 DBG("%s: processing TX ring\n", ag->dev->name);
623
624 sent = 0;
625 while (ring->dirty != ring->curr) {
626 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
627 struct ag71xx_desc *desc = ring->buf[i].desc;
628 struct sk_buff *skb = ring->buf[i].skb;
629
630 if (!ag71xx_desc_empty(desc))
631 break;
632
633 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
634
635 ag->dev->stats.tx_bytes += skb->len;
636 ag->dev->stats.tx_packets++;
637
638 dev_kfree_skb_any(skb);
639 ring->buf[i].skb = NULL;
640
641 ring->dirty++;
642 sent++;
643 }
644
645 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
646
647 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
648 netif_wake_queue(ag->dev);
649
650 }
651
652 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
653 {
654 struct net_device *dev = ag->dev;
655 struct ag71xx_ring *ring = &ag->rx_ring;
656 int done = 0;
657
658 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
659 dev->name, limit, ring->curr, ring->dirty);
660
661 while (done < limit) {
662 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
663 struct ag71xx_desc *desc = ring->buf[i].desc;
664 struct sk_buff *skb;
665 int pktlen;
666
667 if (ag71xx_desc_empty(desc))
668 break;
669
670 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
671 ag71xx_assert(0);
672 break;
673 }
674
675 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
676
677 skb = ring->buf[i].skb;
678 pktlen = ag71xx_desc_pktlen(desc);
679 pktlen -= ETH_FCS_LEN;
680
681 skb_put(skb, pktlen);
682
683 skb->dev = dev;
684 skb->ip_summed = CHECKSUM_NONE;
685
686 dev->last_rx = jiffies;
687 dev->stats.rx_packets++;
688 dev->stats.rx_bytes += pktlen;
689
690 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
691 dev->stats.rx_dropped++;
692 kfree_skb(skb);
693 } else {
694 skb->protocol = eth_type_trans(skb, dev);
695 netif_receive_skb(skb);
696 }
697
698 ring->buf[i].skb = NULL;
699 done++;
700
701 ring->curr++;
702 }
703
704 ag71xx_ring_rx_refill(ag);
705
706 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
707 dev->name, ring->curr, ring->dirty, done);
708
709 return done;
710 }
711
712 static int ag71xx_poll(struct napi_struct *napi, int limit)
713 {
714 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
715 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
716 struct net_device *dev = ag->dev;
717 struct ag71xx_ring *rx_ring;
718 unsigned long flags;
719 u32 status;
720 int done;
721
722 pdata->ddr_flush();
723 ag71xx_tx_packets(ag);
724
725 DBG("%s: processing RX ring\n", dev->name);
726 done = ag71xx_rx_packets(ag, limit);
727
728 rx_ring = &ag->rx_ring;
729 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
730 goto oom;
731
732 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
733 if (unlikely(status & RX_STATUS_OF)) {
734 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
735 dev->stats.rx_fifo_errors++;
736
737 /* restart RX */
738 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
739 }
740
741 if (done < limit) {
742 if (status & RX_STATUS_PR)
743 goto more;
744
745 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
746 if (status & TX_STATUS_PS)
747 goto more;
748
749 DBG("%s: disable polling mode, done=%d, limit=%d\n",
750 dev->name, done, limit);
751
752 netif_rx_complete(dev, napi);
753
754 /* enable interrupts */
755 spin_lock_irqsave(&ag->lock, flags);
756 ag71xx_int_enable(ag, AG71XX_INT_POLL);
757 spin_unlock_irqrestore(&ag->lock, flags);
758 return done;
759 }
760
761 more:
762 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
763 dev->name, done, limit);
764 return done;
765
766 oom:
767 if (netif_msg_rx_err(ag))
768 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
769
770 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
771 netif_rx_complete(dev, napi);
772 return 0;
773 }
774
775 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
776 {
777 struct net_device *dev = dev_id;
778 struct ag71xx *ag = netdev_priv(dev);
779 u32 status;
780
781 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
782 ag71xx_dump_intr(ag, "raw", status);
783
784 if (unlikely(!status))
785 return IRQ_NONE;
786
787 if (unlikely(status & AG71XX_INT_ERR)) {
788 if (status & AG71XX_INT_TX_BE) {
789 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
790 dev_err(&dev->dev, "TX BUS error\n");
791 }
792 if (status & AG71XX_INT_RX_BE) {
793 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
794 dev_err(&dev->dev, "RX BUS error\n");
795 }
796 }
797
798 if (likely(status & AG71XX_INT_POLL)) {
799 ag71xx_int_disable(ag, AG71XX_INT_POLL);
800 DBG("%s: enable polling mode\n", dev->name);
801 netif_rx_schedule(dev, &ag->napi);
802 }
803
804 return IRQ_HANDLED;
805 }
806
807 static void ag71xx_set_multicast_list(struct net_device *dev)
808 {
809 /* TODO */
810 }
811
812 static int __init ag71xx_probe(struct platform_device *pdev)
813 {
814 struct net_device *dev;
815 struct resource *res;
816 struct ag71xx *ag;
817 struct ag71xx_platform_data *pdata;
818 int err;
819
820 pdata = pdev->dev.platform_data;
821 if (!pdata) {
822 dev_err(&pdev->dev, "no platform data specified\n");
823 err = -ENXIO;
824 goto err_out;
825 }
826
827 if (pdata->mii_bus_dev == NULL) {
828 dev_err(&pdev->dev, "no MII bus device specified\n");
829 err = -EINVAL;
830 goto err_out;
831 }
832
833 dev = alloc_etherdev(sizeof(*ag));
834 if (!dev) {
835 dev_err(&pdev->dev, "alloc_etherdev failed\n");
836 err = -ENOMEM;
837 goto err_out;
838 }
839
840 SET_NETDEV_DEV(dev, &pdev->dev);
841
842 ag = netdev_priv(dev);
843 ag->pdev = pdev;
844 ag->dev = dev;
845 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
846 AG71XX_DEFAULT_MSG_ENABLE);
847 spin_lock_init(&ag->lock);
848
849 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
850 if (!res) {
851 dev_err(&pdev->dev, "no mac_base resource found\n");
852 err = -ENXIO;
853 goto err_out;
854 }
855
856 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
857 if (!ag->mac_base) {
858 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
859 err = -ENOMEM;
860 goto err_free_dev;
861 }
862
863 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
864 if (!res) {
865 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
866 err = -ENXIO;
867 goto err_unmap_base;
868 }
869
870 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
871 if (!ag->mii_ctrl) {
872 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
873 err = -ENOMEM;
874 goto err_unmap_base;
875 }
876
877 dev->irq = platform_get_irq(pdev, 0);
878 err = request_irq(dev->irq, ag71xx_interrupt,
879 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
880 dev->name, dev);
881 if (err) {
882 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
883 goto err_unmap_mii_ctrl;
884 }
885
886 dev->base_addr = (unsigned long)ag->mac_base;
887 dev->open = ag71xx_open;
888 dev->stop = ag71xx_stop;
889 dev->hard_start_xmit = ag71xx_hard_start_xmit;
890 dev->set_multicast_list = ag71xx_set_multicast_list;
891 dev->do_ioctl = ag71xx_do_ioctl;
892 dev->ethtool_ops = &ag71xx_ethtool_ops;
893
894 dev->tx_timeout = ag71xx_tx_timeout;
895 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
896
897 init_timer(&ag->oom_timer);
898 ag->oom_timer.data = (unsigned long) dev;
899 ag->oom_timer.function = ag71xx_oom_timer_handler;
900
901 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
902
903 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
904
905 err = register_netdev(dev);
906 if (err) {
907 dev_err(&pdev->dev, "unable to register net device\n");
908 goto err_free_irq;
909 }
910
911 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
912 dev->name, dev->base_addr, dev->irq);
913
914 ag71xx_dump_regs(ag);
915
916 ag71xx_hw_init(ag);
917
918 ag71xx_dump_regs(ag);
919
920 /* Reset the mdio bus explicitly */
921 if (ag->mii_bus) {
922 mutex_lock(&ag->mii_bus->mdio_lock);
923 ag->mii_bus->reset(ag->mii_bus);
924 mutex_unlock(&ag->mii_bus->mdio_lock);
925 }
926
927 platform_set_drvdata(pdev, dev);
928
929 return 0;
930
931 err_free_irq:
932 free_irq(dev->irq, dev);
933 err_unmap_mii_ctrl:
934 iounmap(ag->mii_ctrl);
935 err_unmap_base:
936 iounmap(ag->mac_base);
937 err_free_dev:
938 kfree(dev);
939 err_out:
940 platform_set_drvdata(pdev, NULL);
941 return err;
942 }
943
944 static int __exit ag71xx_remove(struct platform_device *pdev)
945 {
946 struct net_device *dev = platform_get_drvdata(pdev);
947
948 if (dev) {
949 struct ag71xx *ag = netdev_priv(dev);
950
951 unregister_netdev(dev);
952 free_irq(dev->irq, dev);
953 iounmap(ag->mii_ctrl);
954 iounmap(ag->mac_base);
955 kfree(dev);
956 platform_set_drvdata(pdev, NULL);
957 }
958
959 return 0;
960 }
961
962 static struct platform_driver ag71xx_driver = {
963 .probe = ag71xx_probe,
964 .remove = __exit_p(ag71xx_remove),
965 .driver = {
966 .name = AG71XX_DRV_NAME,
967 }
968 };
969
970 static int __init ag71xx_module_init(void)
971 {
972 int ret;
973
974 ret = ag71xx_mdio_driver_init();
975 if (ret)
976 goto err_out;
977
978 ret = platform_driver_register(&ag71xx_driver);
979 if (ret)
980 goto err_mdio_exit;
981
982 return 0;
983
984 err_mdio_exit:
985 ag71xx_mdio_driver_exit();
986 err_out:
987 return ret;
988 }
989
990 static void __exit ag71xx_module_exit(void)
991 {
992 platform_driver_unregister(&ag71xx_driver);
993 ag71xx_mdio_driver_exit();
994 }
995
996 module_init(ag71xx_module_init);
997 module_exit(ag71xx_module_exit);
998
999 MODULE_VERSION(AG71XX_DRV_VERSION);
1000 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1001 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1002 MODULE_LICENSE("GPL v2");
1003 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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