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ar71xx: fix up alignment handling
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113 ring->size = size;
114
115 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
116 if (!ring->buf) {
117 err = -ENOMEM;
118 goto err;
119 }
120
121 for (i = 0; i < size; i++) {
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
140
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
144 }
145
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
148
149 ring->buf[i].skb = NULL;
150
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161 struct ag71xx_ring *ring = &ag->tx_ring;
162 int i;
163
164 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
167
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
170 }
171
172 /* flush descriptors */
173 wmb();
174
175 ring->curr = 0;
176 ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 int i;
183
184 if (!ring->buf)
185 return;
186
187 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
192 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197 int reserve = 0;
198
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
201 reserve = 2;
202
203 if (ag->phy_dev)
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206 reserve %= 4;
207 }
208
209 return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
217 unsigned int i;
218 int ret;
219
220 ret = 0;
221 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 ring->buf[i].desc,
227 ring->buf[i].desc->next);
228 }
229
230 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235 if (!skb) {
236 ret = -ENOMEM;
237 break;
238 }
239
240 skb->dev = ag->dev;
241 skb_reserve(skb, reserve);
242
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244 AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
250 }
251
252 /* flush descriptors */
253 wmb();
254
255 ring->curr = 0;
256 ring->dirty = 0;
257
258 return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
265 unsigned int count;
266
267 count = 0;
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269 unsigned int i;
270
271 i = ring->dirty % AG71XX_RX_RING_SIZE;
272
273 if (ring->buf[i].skb == NULL) {
274 dma_addr_t dma_addr;
275 struct sk_buff *skb;
276
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278 if (skb == NULL)
279 break;
280
281 skb_reserve(skb, reserve);
282 skb->dev = ag->dev;
283
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285 AG71XX_RX_PKT_SIZE,
286 DMA_FROM_DEVICE);
287
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
291 }
292
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
294 count++;
295 }
296
297 /* flush descriptors */
298 wmb();
299
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302 return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307 int ret;
308
309 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
310 if (ret)
311 return ret;
312
313 ag71xx_ring_tx_init(ag);
314
315 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
316 if (ret)
317 return ret;
318
319 ret = ag71xx_ring_rx_init(ag);
320 return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
327
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334 switch (ag->speed) {
335 case SPEED_1000:
336 return "1000";
337 case SPEED_100:
338 return "100";
339 case SPEED_10:
340 return "10";
341 }
342
343 return "?";
344 }
345
346 void ag71xx_link_adjust(struct ag71xx *ag)
347 {
348 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
349 u32 cfg2;
350 u32 ifctl;
351 u32 fifo5;
352 u32 mii_speed;
353
354 if (!ag->link) {
355 netif_carrier_off(ag->dev);
356 if (netif_msg_link(ag))
357 printk(KERN_INFO "%s: link down\n", ag->dev->name);
358 return;
359 }
360
361 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
362 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
363 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
364
365 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
366 ifctl &= ~(MAC_IFCTL_SPEED);
367
368 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
369 fifo5 &= ~FIFO_CFG5_BM;
370
371 switch (ag->speed) {
372 case SPEED_1000:
373 mii_speed = MII_CTRL_SPEED_1000;
374 cfg2 |= MAC_CFG2_IF_1000;
375 fifo5 |= FIFO_CFG5_BM;
376 break;
377 case SPEED_100:
378 mii_speed = MII_CTRL_SPEED_100;
379 cfg2 |= MAC_CFG2_IF_10_100;
380 ifctl |= MAC_IFCTL_SPEED;
381 break;
382 case SPEED_10:
383 mii_speed = MII_CTRL_SPEED_10;
384 cfg2 |= MAC_CFG2_IF_10_100;
385 break;
386 default:
387 BUG();
388 return;
389 }
390
391 if (pdata->is_ar91xx)
392 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
393 else if (pdata->is_ar724x)
394 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
395 else
396 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
397
398 if (pdata->set_pll)
399 pdata->set_pll(ag->speed);
400
401 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
402
403 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
404 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
405 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
406
407 netif_carrier_on(ag->dev);
408 if (netif_msg_link(ag))
409 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
410 ag->dev->name,
411 ag71xx_speed_str(ag),
412 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
413
414 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
415 ag->dev->name,
416 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
417 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
418 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
419
420 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
421 ag->dev->name,
422 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
423 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
424 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
425
426 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
427 ag->dev->name,
428 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
429 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
430 ag71xx_mii_ctrl_rr(ag));
431 }
432
433 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
434 {
435 u32 t;
436
437 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
438 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
439
440 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
441
442 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
443 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
444 }
445
446 static void ag71xx_dma_reset(struct ag71xx *ag)
447 {
448 u32 val;
449 int i;
450
451 ag71xx_dump_dma_regs(ag);
452
453 /* stop RX and TX */
454 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
455 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
456
457 /* clear descriptor addresses */
458 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
459 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
460
461 /* clear pending RX/TX interrupts */
462 for (i = 0; i < 256; i++) {
463 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
464 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
465 }
466
467 /* clear pending errors */
468 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
469 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
470
471 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
472 if (val)
473 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
474 ag->dev->name, val);
475
476 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
477
478 /* mask out reserved bits */
479 val &= ~0xff000000;
480
481 if (val)
482 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
483 ag->dev->name, val);
484
485 ag71xx_dump_dma_regs(ag);
486 }
487
488 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
489 MAC_CFG1_SRX | MAC_CFG1_STX)
490
491 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
492
493 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
494 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
495 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
496 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
497 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
498 FIFO_CFG4_VT)
499
500 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
501 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
502 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
503 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
504 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
505 FIFO_CFG5_17 | FIFO_CFG5_SF)
506
507 static void ag71xx_hw_init(struct ag71xx *ag)
508 {
509 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
510
511 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
512 udelay(20);
513
514 ar71xx_device_stop(pdata->reset_bit);
515 mdelay(100);
516 ar71xx_device_start(pdata->reset_bit);
517 mdelay(100);
518
519 /* setup MAC configuration registers */
520 if (pdata->is_ar724x)
521 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
522 MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
523 else
524 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
525
526 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
527 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
528
529 /* setup max frame length */
530 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
531
532 /* setup MII interface type */
533 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
534
535 /* setup FIFO configuration registers */
536 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
537 if (pdata->is_ar724x) {
538 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
539 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
540 } else {
541 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
542 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
543 }
544 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
545 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
546
547 ag71xx_dma_reset(ag);
548 }
549
550 static void ag71xx_hw_start(struct ag71xx *ag)
551 {
552 /* start RX engine */
553 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
554
555 /* enable interrupts */
556 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
557 }
558
559 static void ag71xx_hw_stop(struct ag71xx *ag)
560 {
561 /* disable all interrupts */
562 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
563
564 ag71xx_dma_reset(ag);
565 }
566
567 static int ag71xx_open(struct net_device *dev)
568 {
569 struct ag71xx *ag = netdev_priv(dev);
570 int ret;
571
572 ret = ag71xx_rings_init(ag);
573 if (ret)
574 goto err;
575
576 napi_enable(&ag->napi);
577
578 netif_carrier_off(dev);
579 ag71xx_phy_start(ag);
580
581 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
582 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
583
584 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
585
586 ag71xx_hw_start(ag);
587
588 netif_start_queue(dev);
589
590 return 0;
591
592 err:
593 ag71xx_rings_cleanup(ag);
594 return ret;
595 }
596
597 static int ag71xx_stop(struct net_device *dev)
598 {
599 struct ag71xx *ag = netdev_priv(dev);
600 unsigned long flags;
601
602 netif_carrier_off(dev);
603 ag71xx_phy_stop(ag);
604
605 spin_lock_irqsave(&ag->lock, flags);
606
607 netif_stop_queue(dev);
608
609 ag71xx_hw_stop(ag);
610
611 napi_disable(&ag->napi);
612 del_timer_sync(&ag->oom_timer);
613
614 spin_unlock_irqrestore(&ag->lock, flags);
615
616 ag71xx_rings_cleanup(ag);
617
618 return 0;
619 }
620
621 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
622 struct net_device *dev)
623 {
624 struct ag71xx *ag = netdev_priv(dev);
625 struct ag71xx_ring *ring = &ag->tx_ring;
626 struct ag71xx_desc *desc;
627 dma_addr_t dma_addr;
628 int i;
629
630 i = ring->curr % AG71XX_TX_RING_SIZE;
631 desc = ring->buf[i].desc;
632
633 if (!ag71xx_desc_empty(desc))
634 goto err_drop;
635
636 if (ag71xx_has_ar8216(ag))
637 ag71xx_add_ar8216_header(ag, skb);
638
639 if (skb->len <= 0) {
640 DBG("%s: packet len is too small\n", ag->dev->name);
641 goto err_drop;
642 }
643
644 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
645 DMA_TO_DEVICE);
646
647 ring->buf[i].skb = skb;
648
649 /* setup descriptor fields */
650 desc->data = (u32) dma_addr;
651 desc->ctrl = (skb->len & DESC_PKTLEN_M);
652
653 /* flush descriptor */
654 wmb();
655
656 ring->curr++;
657 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
658 DBG("%s: tx queue full\n", ag->dev->name);
659 netif_stop_queue(dev);
660 }
661
662 DBG("%s: packet injected into TX queue\n", ag->dev->name);
663
664 /* enable TX engine */
665 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
666
667 return NETDEV_TX_OK;
668
669 err_drop:
670 dev->stats.tx_dropped++;
671
672 dev_kfree_skb(skb);
673 return NETDEV_TX_OK;
674 }
675
676 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
677 {
678 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
679 struct ag71xx *ag = netdev_priv(dev);
680 int ret;
681
682 switch (cmd) {
683 case SIOCETHTOOL:
684 if (ag->phy_dev == NULL)
685 break;
686
687 spin_lock_irq(&ag->lock);
688 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
689 spin_unlock_irq(&ag->lock);
690 return ret;
691
692 case SIOCSIFHWADDR:
693 if (copy_from_user
694 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
695 return -EFAULT;
696 return 0;
697
698 case SIOCGIFHWADDR:
699 if (copy_to_user
700 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
701 return -EFAULT;
702 return 0;
703
704 case SIOCGMIIPHY:
705 case SIOCGMIIREG:
706 case SIOCSMIIREG:
707 if (ag->phy_dev == NULL)
708 break;
709
710 return phy_mii_ioctl(ag->phy_dev, data, cmd);
711
712 default:
713 break;
714 }
715
716 return -EOPNOTSUPP;
717 }
718
719 static void ag71xx_oom_timer_handler(unsigned long data)
720 {
721 struct net_device *dev = (struct net_device *) data;
722 struct ag71xx *ag = netdev_priv(dev);
723
724 napi_schedule(&ag->napi);
725 }
726
727 static void ag71xx_tx_timeout(struct net_device *dev)
728 {
729 struct ag71xx *ag = netdev_priv(dev);
730
731 if (netif_msg_tx_err(ag))
732 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
733
734 schedule_work(&ag->restart_work);
735 }
736
737 static void ag71xx_restart_work_func(struct work_struct *work)
738 {
739 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
740
741 ag71xx_stop(ag->dev);
742 ag71xx_open(ag->dev);
743 }
744
745 static int ag71xx_tx_packets(struct ag71xx *ag)
746 {
747 struct ag71xx_ring *ring = &ag->tx_ring;
748 int sent;
749
750 DBG("%s: processing TX ring\n", ag->dev->name);
751
752 sent = 0;
753 while (ring->dirty != ring->curr) {
754 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
755 struct ag71xx_desc *desc = ring->buf[i].desc;
756 struct sk_buff *skb = ring->buf[i].skb;
757
758 if (!ag71xx_desc_empty(desc))
759 break;
760
761 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
762
763 ag->dev->stats.tx_bytes += skb->len;
764 ag->dev->stats.tx_packets++;
765
766 dev_kfree_skb_any(skb);
767 ring->buf[i].skb = NULL;
768
769 ring->dirty++;
770 sent++;
771 }
772
773 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
774
775 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
776 netif_wake_queue(ag->dev);
777
778 return sent;
779 }
780
781 static void ag71xx_rx_align_skb(struct ag71xx *ag, struct sk_buff *skb, int len)
782 {
783 int offset = ((unsigned long) skb->data) % 4;
784 void *data;
785
786 if (offset == 2)
787 return;
788
789 if (ag->phy_dev && ag->phy_dev->pkt_align != 0)
790 return;
791
792 if (len > 128)
793 return;
794
795 if (WARN_ON(skb_headroom(skb) < 2))
796 return;
797
798 data = skb->data;
799 skb->data -= 2;
800 memmove(skb->data, data, len);
801 }
802
803 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
804 {
805 struct net_device *dev = ag->dev;
806 struct ag71xx_ring *ring = &ag->rx_ring;
807 int done = 0;
808
809 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
810 dev->name, limit, ring->curr, ring->dirty);
811
812 while (done < limit) {
813 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
814 struct ag71xx_desc *desc = ring->buf[i].desc;
815 struct sk_buff *skb;
816 int pktlen;
817 int err = 0;
818
819 if (ag71xx_desc_empty(desc))
820 break;
821
822 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
823 ag71xx_assert(0);
824 break;
825 }
826
827 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
828
829 skb = ring->buf[i].skb;
830 pktlen = ag71xx_desc_pktlen(desc);
831 pktlen -= ETH_FCS_LEN;
832
833 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
834 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
835
836 dev->last_rx = jiffies;
837 dev->stats.rx_packets++;
838 dev->stats.rx_bytes += pktlen;
839
840 skb_put(skb, pktlen);
841 if (ag71xx_has_ar8216(ag))
842 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
843
844 ag71xx_rx_align_skb(ag, skb, pktlen);
845
846 if (err) {
847 dev->stats.rx_dropped++;
848 kfree_skb(skb);
849 } else {
850 skb->dev = dev;
851 skb->ip_summed = CHECKSUM_NONE;
852 if (ag->phy_dev) {
853 ag->phy_dev->netif_receive_skb(skb);
854 } else {
855 skb->protocol = eth_type_trans(skb, dev);
856 netif_receive_skb(skb);
857 }
858 }
859
860 ring->buf[i].skb = NULL;
861 done++;
862
863 ring->curr++;
864 }
865
866 ag71xx_ring_rx_refill(ag);
867
868 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
869 dev->name, ring->curr, ring->dirty, done);
870
871 return done;
872 }
873
874 static int ag71xx_poll(struct napi_struct *napi, int limit)
875 {
876 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
877 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
878 struct net_device *dev = ag->dev;
879 struct ag71xx_ring *rx_ring;
880 unsigned long flags;
881 u32 status;
882 int tx_done;
883 int rx_done;
884
885 pdata->ddr_flush();
886 tx_done = ag71xx_tx_packets(ag);
887
888 DBG("%s: processing RX ring\n", dev->name);
889 rx_done = ag71xx_rx_packets(ag, limit);
890
891 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
892
893 rx_ring = &ag->rx_ring;
894 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
895 goto oom;
896
897 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
898 if (unlikely(status & RX_STATUS_OF)) {
899 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
900 dev->stats.rx_fifo_errors++;
901
902 /* restart RX */
903 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
904 }
905
906 if (rx_done < limit) {
907 if (status & RX_STATUS_PR)
908 goto more;
909
910 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
911 if (status & TX_STATUS_PS)
912 goto more;
913
914 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
915 dev->name, rx_done, tx_done, limit);
916
917 napi_complete(napi);
918
919 /* enable interrupts */
920 spin_lock_irqsave(&ag->lock, flags);
921 ag71xx_int_enable(ag, AG71XX_INT_POLL);
922 spin_unlock_irqrestore(&ag->lock, flags);
923 return rx_done;
924 }
925
926 more:
927 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
928 dev->name, rx_done, tx_done, limit);
929 return rx_done;
930
931 oom:
932 if (netif_msg_rx_err(ag))
933 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
934
935 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
936 napi_complete(napi);
937 return 0;
938 }
939
940 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
941 {
942 struct net_device *dev = dev_id;
943 struct ag71xx *ag = netdev_priv(dev);
944 u32 status;
945
946 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
947 ag71xx_dump_intr(ag, "raw", status);
948
949 if (unlikely(!status))
950 return IRQ_NONE;
951
952 if (unlikely(status & AG71XX_INT_ERR)) {
953 if (status & AG71XX_INT_TX_BE) {
954 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
955 dev_err(&dev->dev, "TX BUS error\n");
956 }
957 if (status & AG71XX_INT_RX_BE) {
958 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
959 dev_err(&dev->dev, "RX BUS error\n");
960 }
961 }
962
963 if (likely(status & AG71XX_INT_POLL)) {
964 ag71xx_int_disable(ag, AG71XX_INT_POLL);
965 DBG("%s: enable polling mode\n", dev->name);
966 napi_schedule(&ag->napi);
967 }
968
969 ag71xx_debugfs_update_int_stats(ag, status);
970
971 return IRQ_HANDLED;
972 }
973
974 static void ag71xx_set_multicast_list(struct net_device *dev)
975 {
976 /* TODO */
977 }
978
979 #ifdef CONFIG_NET_POLL_CONTROLLER
980 /*
981 * Polling 'interrupt' - used by things like netconsole to send skbs
982 * without having to re-enable interrupts. It's not called while
983 * the interrupt routine is executing.
984 */
985 static void ag71xx_netpoll(struct net_device *dev)
986 {
987 disable_irq(dev->irq);
988 ag71xx_interrupt(dev->irq, dev);
989 enable_irq(dev->irq);
990 }
991 #endif
992
993 static const struct net_device_ops ag71xx_netdev_ops = {
994 .ndo_open = ag71xx_open,
995 .ndo_stop = ag71xx_stop,
996 .ndo_start_xmit = ag71xx_hard_start_xmit,
997 .ndo_set_multicast_list = ag71xx_set_multicast_list,
998 .ndo_do_ioctl = ag71xx_do_ioctl,
999 .ndo_tx_timeout = ag71xx_tx_timeout,
1000 .ndo_change_mtu = eth_change_mtu,
1001 .ndo_set_mac_address = eth_mac_addr,
1002 .ndo_validate_addr = eth_validate_addr,
1003 #ifdef CONFIG_NET_POLL_CONTROLLER
1004 .ndo_poll_controller = ag71xx_netpoll,
1005 #endif
1006 };
1007
1008 static int __init ag71xx_probe(struct platform_device *pdev)
1009 {
1010 struct net_device *dev;
1011 struct resource *res;
1012 struct ag71xx *ag;
1013 struct ag71xx_platform_data *pdata;
1014 int err;
1015
1016 pdata = pdev->dev.platform_data;
1017 if (!pdata) {
1018 dev_err(&pdev->dev, "no platform data specified\n");
1019 err = -ENXIO;
1020 goto err_out;
1021 }
1022
1023 if (pdata->mii_bus_dev == NULL) {
1024 dev_err(&pdev->dev, "no MII bus device specified\n");
1025 err = -EINVAL;
1026 goto err_out;
1027 }
1028
1029 dev = alloc_etherdev(sizeof(*ag));
1030 if (!dev) {
1031 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1032 err = -ENOMEM;
1033 goto err_out;
1034 }
1035
1036 SET_NETDEV_DEV(dev, &pdev->dev);
1037
1038 ag = netdev_priv(dev);
1039 ag->pdev = pdev;
1040 ag->dev = dev;
1041 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1042 AG71XX_DEFAULT_MSG_ENABLE);
1043 spin_lock_init(&ag->lock);
1044
1045 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1046 if (!res) {
1047 dev_err(&pdev->dev, "no mac_base resource found\n");
1048 err = -ENXIO;
1049 goto err_out;
1050 }
1051
1052 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1053 if (!ag->mac_base) {
1054 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1055 err = -ENOMEM;
1056 goto err_free_dev;
1057 }
1058
1059 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1060 if (!res) {
1061 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1062 err = -ENXIO;
1063 goto err_unmap_base;
1064 }
1065
1066 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1067 if (!ag->mii_ctrl) {
1068 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1069 err = -ENOMEM;
1070 goto err_unmap_base;
1071 }
1072
1073 dev->irq = platform_get_irq(pdev, 0);
1074 err = request_irq(dev->irq, ag71xx_interrupt,
1075 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
1076 dev->name, dev);
1077 if (err) {
1078 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1079 goto err_unmap_mii_ctrl;
1080 }
1081
1082 dev->base_addr = (unsigned long)ag->mac_base;
1083 dev->netdev_ops = &ag71xx_netdev_ops;
1084 dev->ethtool_ops = &ag71xx_ethtool_ops;
1085
1086 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1087
1088 init_timer(&ag->oom_timer);
1089 ag->oom_timer.data = (unsigned long) dev;
1090 ag->oom_timer.function = ag71xx_oom_timer_handler;
1091
1092 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1093
1094 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1095
1096 err = register_netdev(dev);
1097 if (err) {
1098 dev_err(&pdev->dev, "unable to register net device\n");
1099 goto err_free_irq;
1100 }
1101
1102 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1103 dev->name, dev->base_addr, dev->irq);
1104
1105 ag71xx_dump_regs(ag);
1106
1107 ag71xx_hw_init(ag);
1108
1109 ag71xx_dump_regs(ag);
1110
1111 err = ag71xx_phy_connect(ag);
1112 if (err)
1113 goto err_unregister_netdev;
1114
1115 err = ag71xx_debugfs_init(ag);
1116 if (err)
1117 goto err_phy_disconnect;
1118
1119 platform_set_drvdata(pdev, dev);
1120
1121 return 0;
1122
1123 err_phy_disconnect:
1124 ag71xx_phy_disconnect(ag);
1125 err_unregister_netdev:
1126 unregister_netdev(dev);
1127 err_free_irq:
1128 free_irq(dev->irq, dev);
1129 err_unmap_mii_ctrl:
1130 iounmap(ag->mii_ctrl);
1131 err_unmap_base:
1132 iounmap(ag->mac_base);
1133 err_free_dev:
1134 kfree(dev);
1135 err_out:
1136 platform_set_drvdata(pdev, NULL);
1137 return err;
1138 }
1139
1140 static int __exit ag71xx_remove(struct platform_device *pdev)
1141 {
1142 struct net_device *dev = platform_get_drvdata(pdev);
1143
1144 if (dev) {
1145 struct ag71xx *ag = netdev_priv(dev);
1146
1147 ag71xx_debugfs_exit(ag);
1148 ag71xx_phy_disconnect(ag);
1149 unregister_netdev(dev);
1150 free_irq(dev->irq, dev);
1151 iounmap(ag->mii_ctrl);
1152 iounmap(ag->mac_base);
1153 kfree(dev);
1154 platform_set_drvdata(pdev, NULL);
1155 }
1156
1157 return 0;
1158 }
1159
1160 static struct platform_driver ag71xx_driver = {
1161 .probe = ag71xx_probe,
1162 .remove = __exit_p(ag71xx_remove),
1163 .driver = {
1164 .name = AG71XX_DRV_NAME,
1165 }
1166 };
1167
1168 static int __init ag71xx_module_init(void)
1169 {
1170 int ret;
1171
1172 ret = ag71xx_debugfs_root_init();
1173 if (ret)
1174 goto err_out;
1175
1176 ret = ag71xx_mdio_driver_init();
1177 if (ret)
1178 goto err_debugfs_exit;
1179
1180 ret = platform_driver_register(&ag71xx_driver);
1181 if (ret)
1182 goto err_mdio_exit;
1183
1184 return 0;
1185
1186 err_mdio_exit:
1187 ag71xx_mdio_driver_exit();
1188 err_debugfs_exit:
1189 ag71xx_debugfs_root_exit();
1190 err_out:
1191 return ret;
1192 }
1193
1194 static void __exit ag71xx_module_exit(void)
1195 {
1196 platform_driver_unregister(&ag71xx_driver);
1197 ag71xx_mdio_driver_exit();
1198 ag71xx_debugfs_root_exit();
1199 }
1200
1201 module_init(ag71xx_module_init);
1202 module_exit(ag71xx_module_exit);
1203
1204 MODULE_VERSION(AG71XX_DRV_VERSION);
1205 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1206 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1207 MODULE_LICENSE("GPL v2");
1208 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository