move random MAC address generation into the platform initialization code
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs)
89 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
90 ring->descs, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95 int err;
96
97 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
98 &ring->descs_dma,
99 GFP_ATOMIC);
100 if (!ring->descs) {
101 err = -ENOMEM;
102 goto err;
103 }
104
105 ring->size = size;
106
107 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
108 if (!ring->buf) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113 return 0;
114
115 err:
116 return err;
117 }
118
119 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
120 {
121 struct ag71xx_ring *ring = &ag->tx_ring;
122 struct net_device *dev = ag->dev;
123
124 while (ring->curr != ring->dirty) {
125 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
126
127 if (!ag71xx_desc_empty(&ring->descs[i])) {
128 ring->descs[i].ctrl = 0;
129 dev->stats.tx_errors++;
130 }
131
132 if (ring->buf[i].skb)
133 dev_kfree_skb_any(ring->buf[i].skb);
134
135 ring->buf[i].skb = NULL;
136
137 ring->dirty++;
138 }
139
140 /* flush descriptors */
141 wmb();
142
143 }
144
145 static void ag71xx_ring_tx_init(struct ag71xx *ag)
146 {
147 struct ag71xx_ring *ring = &ag->tx_ring;
148 int i;
149
150 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
151 ring->descs[i].next = (u32) (ring->descs_dma +
152 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
153
154 ring->descs[i].ctrl = DESC_EMPTY;
155 ring->buf[i].skb = NULL;
156 }
157
158 /* flush descriptors */
159 wmb();
160
161 ring->curr = 0;
162 ring->dirty = 0;
163 }
164
165 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
166 {
167 struct ag71xx_ring *ring = &ag->rx_ring;
168 int i;
169
170 if (!ring->buf)
171 return;
172
173 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
174 if (ring->buf[i].skb)
175 kfree_skb(ring->buf[i].skb);
176
177 }
178
179 static int ag71xx_ring_rx_init(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 unsigned int i;
183 int ret;
184
185 ret = 0;
186 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
187 ring->descs[i].next = (u32) (ring->descs_dma +
188 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
189
190 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
191 struct sk_buff *skb;
192
193 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
194 if (!skb) {
195 ret = -ENOMEM;
196 break;
197 }
198
199 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
200 DMA_FROM_DEVICE);
201
202 skb->dev = ag->dev;
203 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
204
205 ring->buf[i].skb = skb;
206 ring->descs[i].data = virt_to_phys(skb->data);
207 ring->descs[i].ctrl = DESC_EMPTY;
208 }
209
210 /* flush descriptors */
211 wmb();
212
213 ring->curr = 0;
214 ring->dirty = 0;
215
216 return ret;
217 }
218
219 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
220 {
221 struct ag71xx_ring *ring = &ag->rx_ring;
222 unsigned int count;
223
224 count = 0;
225 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
226 unsigned int i;
227
228 i = ring->dirty % AG71XX_RX_RING_SIZE;
229
230 if (ring->buf[i].skb == NULL) {
231 struct sk_buff *skb;
232
233 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
234 if (skb == NULL)
235 break;
236
237 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
238 DMA_FROM_DEVICE);
239
240 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
241 skb->dev = ag->dev;
242
243 ring->buf[i].skb = skb;
244 ring->descs[i].data = virt_to_phys(skb->data);
245 }
246
247 ring->descs[i].ctrl = DESC_EMPTY;
248 count++;
249 }
250
251 /* flush descriptors */
252 wmb();
253
254 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
255
256 return count;
257 }
258
259 static int ag71xx_rings_init(struct ag71xx *ag)
260 {
261 int ret;
262
263 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
264 if (ret)
265 return ret;
266
267 ag71xx_ring_tx_init(ag);
268
269 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
270 if (ret)
271 return ret;
272
273 ret = ag71xx_ring_rx_init(ag);
274 return ret;
275 }
276
277 static void ag71xx_rings_cleanup(struct ag71xx *ag)
278 {
279 ag71xx_ring_rx_clean(ag);
280 ag71xx_ring_free(&ag->rx_ring);
281
282 ag71xx_ring_tx_clean(ag);
283 ag71xx_ring_free(&ag->tx_ring);
284 }
285
286 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
287 {
288 u32 t;
289
290 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
291 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
292
293 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
294
295 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
296 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
297 }
298
299 static void ag71xx_dma_reset(struct ag71xx *ag)
300 {
301 int i;
302
303 ag71xx_dump_dma_regs(ag);
304
305 /* stop RX and TX */
306 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
307 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
308
309 /* clear descriptor addresses */
310 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
311 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
312
313 /* clear pending RX/TX interrupts */
314 for (i = 0; i < 256; i++) {
315 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
316 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
317 }
318
319 /* clear pending errors */
320 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
321 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
322
323 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
324 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
325 ag->dev->name);
326
327 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
328 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
329 ag->dev->name);
330
331 ag71xx_dump_dma_regs(ag);
332 }
333
334 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
335 MAC_CFG1_SRX | MAC_CFG1_STX)
336
337 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
338
339 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
340 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
341 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
342 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
343 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
344 FIFO_CFG4_VT)
345
346 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
347 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
348 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
349 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
350 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
351 FIFO_CFG5_17 | FIFO_CFG5_SF)
352
353 static void ag71xx_hw_init(struct ag71xx *ag)
354 {
355 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
356
357 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
358 udelay(20);
359
360 ar71xx_device_stop(pdata->reset_bit);
361 mdelay(100);
362 ar71xx_device_start(pdata->reset_bit);
363 mdelay(100);
364
365 /* setup MAC configuration registers */
366 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
367 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
368 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
369
370 /* setup max frame length */
371 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
372
373 /* setup MII interface type */
374 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
375
376 /* setup FIFO configuration registers */
377 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
378 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
379 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
380 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
381 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
382
383 ag71xx_dma_reset(ag);
384 }
385
386 static void ag71xx_hw_start(struct ag71xx *ag)
387 {
388 /* start RX engine */
389 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
390
391 /* enable interrupts */
392 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
393 }
394
395 static void ag71xx_hw_stop(struct ag71xx *ag)
396 {
397 /* disable all interrupts */
398 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
399
400 ag71xx_dma_reset(ag);
401 }
402
403 static int ag71xx_open(struct net_device *dev)
404 {
405 struct ag71xx *ag = netdev_priv(dev);
406 int ret;
407
408 ret = ag71xx_rings_init(ag);
409 if (ret)
410 goto err;
411
412 napi_enable(&ag->napi);
413
414 netif_carrier_off(dev);
415 ag71xx_phy_start(ag);
416
417 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
418 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
419
420 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
421
422 ag71xx_hw_start(ag);
423
424 netif_start_queue(dev);
425
426 return 0;
427
428 err:
429 ag71xx_rings_cleanup(ag);
430 return ret;
431 }
432
433 static int ag71xx_stop(struct net_device *dev)
434 {
435 struct ag71xx *ag = netdev_priv(dev);
436 unsigned long flags;
437
438 spin_lock_irqsave(&ag->lock, flags);
439
440 netif_stop_queue(dev);
441
442 ag71xx_hw_stop(ag);
443
444 netif_carrier_off(dev);
445 ag71xx_phy_stop(ag);
446
447 napi_disable(&ag->napi);
448 del_timer_sync(&ag->oom_timer);
449
450 spin_unlock_irqrestore(&ag->lock, flags);
451
452 ag71xx_rings_cleanup(ag);
453
454 return 0;
455 }
456
457 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
458 {
459 struct ag71xx *ag = netdev_priv(dev);
460 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
461 struct ag71xx_ring *ring = &ag->tx_ring;
462 struct ag71xx_desc *desc;
463 unsigned long flags;
464 int i;
465
466 i = ring->curr % AG71XX_TX_RING_SIZE;
467 desc = &ring->descs[i];
468
469 spin_lock_irqsave(&ag->lock, flags);
470 pdata->ddr_flush();
471 spin_unlock_irqrestore(&ag->lock, flags);
472
473 if (!ag71xx_desc_empty(desc))
474 goto err_drop;
475
476 if (skb->len <= 0) {
477 DBG("%s: packet len is too small\n", ag->dev->name);
478 goto err_drop;
479 }
480
481 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
482
483 ring->buf[i].skb = skb;
484
485 /* setup descriptor fields */
486 desc->data = virt_to_phys(skb->data);
487 desc->ctrl = (skb->len & DESC_PKTLEN_M);
488
489 /* flush descriptor */
490 wmb();
491
492 ring->curr++;
493 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
494 DBG("%s: tx queue full\n", ag->dev->name);
495 netif_stop_queue(dev);
496 }
497
498 DBG("%s: packet injected into TX queue\n", ag->dev->name);
499
500 /* enable TX engine */
501 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
502
503 dev->trans_start = jiffies;
504
505 return 0;
506
507 err_drop:
508 dev->stats.tx_dropped++;
509
510 dev_kfree_skb(skb);
511 return 0;
512 }
513
514 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
515 {
516 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
517 struct ag71xx *ag = netdev_priv(dev);
518 int ret;
519
520 switch (cmd) {
521 case SIOCETHTOOL:
522 if (ag->phy_dev == NULL)
523 break;
524
525 spin_lock_irq(&ag->lock);
526 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
527 spin_unlock_irq(&ag->lock);
528 return ret;
529
530 case SIOCSIFHWADDR:
531 if (copy_from_user
532 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
533 return -EFAULT;
534 return 0;
535
536 case SIOCGIFHWADDR:
537 if (copy_to_user
538 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
539 return -EFAULT;
540 return 0;
541
542 case SIOCGMIIPHY:
543 case SIOCGMIIREG:
544 case SIOCSMIIREG:
545 if (ag->phy_dev == NULL)
546 break;
547
548 return phy_mii_ioctl(ag->phy_dev, data, cmd);
549
550 default:
551 break;
552 }
553
554 return -EOPNOTSUPP;
555 }
556
557 static void ag71xx_oom_timer_handler(unsigned long data)
558 {
559 struct net_device *dev = (struct net_device *) data;
560 struct ag71xx *ag = netdev_priv(dev);
561
562 netif_rx_schedule(dev, &ag->napi);
563 }
564
565 static void ag71xx_tx_timeout(struct net_device *dev)
566 {
567 struct ag71xx *ag = netdev_priv(dev);
568
569 if (netif_msg_tx_err(ag))
570 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
571
572 schedule_work(&ag->restart_work);
573 }
574
575 static void ag71xx_restart_work_func(struct work_struct *work)
576 {
577 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
578
579 ag71xx_stop(ag->dev);
580 ag71xx_open(ag->dev);
581 }
582
583 static void ag71xx_tx_packets(struct ag71xx *ag)
584 {
585 struct ag71xx_ring *ring = &ag->tx_ring;
586 unsigned int sent;
587
588 DBG("%s: processing TX ring\n", ag->dev->name);
589
590 sent = 0;
591 while (ring->dirty != ring->curr) {
592 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
593 struct ag71xx_desc *desc = &ring->descs[i];
594 struct sk_buff *skb = ring->buf[i].skb;
595
596 if (!ag71xx_desc_empty(desc))
597 break;
598
599 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
600
601 ag->dev->stats.tx_bytes += skb->len;
602 ag->dev->stats.tx_packets++;
603
604 dev_kfree_skb_any(skb);
605 ring->buf[i].skb = NULL;
606
607 ring->dirty++;
608 sent++;
609 }
610
611 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
612
613 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
614 netif_wake_queue(ag->dev);
615
616 }
617
618 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
619 {
620 struct net_device *dev = ag->dev;
621 struct ag71xx_ring *ring = &ag->rx_ring;
622 int done = 0;
623
624 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
625 dev->name, limit, ring->curr, ring->dirty);
626
627 while (done < limit) {
628 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
629 struct ag71xx_desc *desc = &ring->descs[i];
630 struct sk_buff *skb;
631 int pktlen;
632
633 if (ag71xx_desc_empty(desc))
634 break;
635
636 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
637 ag71xx_assert(0);
638 break;
639 }
640
641 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
642
643 skb = ring->buf[i].skb;
644 pktlen = ag71xx_desc_pktlen(desc);
645 pktlen -= ETH_FCS_LEN;
646
647 skb_put(skb, pktlen);
648
649 skb->dev = dev;
650 skb->protocol = eth_type_trans(skb, dev);
651 skb->ip_summed = CHECKSUM_NONE;
652
653 netif_receive_skb(skb);
654
655 dev->last_rx = jiffies;
656 dev->stats.rx_packets++;
657 dev->stats.rx_bytes += pktlen;
658
659 ring->buf[i].skb = NULL;
660 done++;
661
662 ring->curr++;
663 }
664
665 ag71xx_ring_rx_refill(ag);
666
667 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
668 dev->name, ring->curr, ring->dirty, done);
669
670 return done;
671 }
672
673 static int ag71xx_poll(struct napi_struct *napi, int limit)
674 {
675 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
676 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
677 struct net_device *dev = ag->dev;
678 struct ag71xx_ring *rx_ring;
679 unsigned long flags;
680 u32 status;
681 int done;
682
683 pdata->ddr_flush();
684 ag71xx_tx_packets(ag);
685
686 DBG("%s: processing RX ring\n", dev->name);
687 done = ag71xx_rx_packets(ag, limit);
688
689 rx_ring = &ag->rx_ring;
690 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
691 goto oom;
692
693 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
694 if (unlikely(status & RX_STATUS_OF)) {
695 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
696 dev->stats.rx_fifo_errors++;
697
698 /* restart RX */
699 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
700 }
701
702 if (done < limit) {
703 if (status & RX_STATUS_PR)
704 goto more;
705
706 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
707 if (status & TX_STATUS_PS)
708 goto more;
709
710 DBG("%s: disable polling mode, done=%d, limit=%d\n",
711 dev->name, done, limit);
712
713 netif_rx_complete(dev, napi);
714
715 /* enable interrupts */
716 spin_lock_irqsave(&ag->lock, flags);
717 ag71xx_int_enable(ag, AG71XX_INT_POLL);
718 spin_unlock_irqrestore(&ag->lock, flags);
719 return 0;
720 }
721
722 more:
723 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
724 dev->name, done, limit);
725 return 1;
726
727 oom:
728 if (netif_msg_rx_err(ag))
729 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
730
731 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
732 netif_rx_complete(dev, napi);
733 return 0;
734 }
735
736 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
737 {
738 struct net_device *dev = dev_id;
739 struct ag71xx *ag = netdev_priv(dev);
740 u32 status;
741
742 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
743 ag71xx_dump_intr(ag, "raw", status);
744
745 if (unlikely(!status))
746 return IRQ_NONE;
747
748 if (unlikely(status & AG71XX_INT_ERR)) {
749 if (status & AG71XX_INT_TX_BE) {
750 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
751 dev_err(&dev->dev, "TX BUS error\n");
752 }
753 if (status & AG71XX_INT_RX_BE) {
754 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
755 dev_err(&dev->dev, "RX BUS error\n");
756 }
757 }
758
759 if (likely(status & AG71XX_INT_POLL)) {
760 ag71xx_int_disable(ag, AG71XX_INT_POLL);
761 DBG("%s: enable polling mode\n", dev->name);
762 netif_rx_schedule(dev, &ag->napi);
763 }
764
765 return IRQ_HANDLED;
766 }
767
768 static void ag71xx_set_multicast_list(struct net_device *dev)
769 {
770 /* TODO */
771 }
772
773 static int __init ag71xx_probe(struct platform_device *pdev)
774 {
775 struct net_device *dev;
776 struct resource *res;
777 struct ag71xx *ag;
778 struct ag71xx_platform_data *pdata;
779 int err;
780
781 pdata = pdev->dev.platform_data;
782 if (!pdata) {
783 dev_err(&pdev->dev, "no platform data specified\n");
784 err = -ENXIO;
785 goto err_out;
786 }
787
788 dev = alloc_etherdev(sizeof(*ag));
789 if (!dev) {
790 dev_err(&pdev->dev, "alloc_etherdev failed\n");
791 err = -ENOMEM;
792 goto err_out;
793 }
794
795 SET_NETDEV_DEV(dev, &pdev->dev);
796
797 ag = netdev_priv(dev);
798 ag->pdev = pdev;
799 ag->dev = dev;
800 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
801 ag->msg_enable = netif_msg_init(ag71xx_debug,
802 AG71XX_DEFAULT_MSG_ENABLE);
803 spin_lock_init(&ag->lock);
804
805 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
806 if (!res) {
807 dev_err(&pdev->dev, "no mac_base resource found\n");
808 err = -ENXIO;
809 goto err_out;
810 }
811
812 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
813 if (!ag->mac_base) {
814 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
815 err = -ENOMEM;
816 goto err_free_dev;
817 }
818
819 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
820 if (!res) {
821 dev_err(&pdev->dev, "no mac_base2 resource found\n");
822 err = -ENXIO;
823 goto err_unmap_base1;
824 }
825
826 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
827 if (!ag->mac_base) {
828 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
829 err = -ENOMEM;
830 goto err_unmap_base1;
831 }
832
833 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
834 if (!res) {
835 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
836 err = -ENXIO;
837 goto err_unmap_base2;
838 }
839
840 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
841 if (!ag->mii_ctrl) {
842 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
843 err = -ENOMEM;
844 goto err_unmap_base2;
845 }
846
847 dev->irq = platform_get_irq(pdev, 0);
848 err = request_irq(dev->irq, ag71xx_interrupt,
849 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
850 dev->name, dev);
851 if (err) {
852 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
853 goto err_unmap_mii_ctrl;
854 }
855
856 dev->base_addr = (unsigned long)ag->mac_base;
857 dev->open = ag71xx_open;
858 dev->stop = ag71xx_stop;
859 dev->hard_start_xmit = ag71xx_hard_start_xmit;
860 dev->set_multicast_list = ag71xx_set_multicast_list;
861 dev->do_ioctl = ag71xx_do_ioctl;
862 dev->ethtool_ops = &ag71xx_ethtool_ops;
863
864 dev->tx_timeout = ag71xx_tx_timeout;
865 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
866
867 init_timer(&ag->oom_timer);
868 ag->oom_timer.data = (unsigned long) dev;
869 ag->oom_timer.function = ag71xx_oom_timer_handler;
870
871 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
872
873 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
874
875 err = register_netdev(dev);
876 if (err) {
877 dev_err(&pdev->dev, "unable to register net device\n");
878 goto err_free_irq;
879 }
880
881 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
882 dev->name, dev->base_addr, dev->irq);
883
884 ag71xx_dump_regs(ag);
885
886 ag71xx_hw_init(ag);
887
888 ag71xx_dump_regs(ag);
889
890 /* Reset the mdio bus explicitly */
891 if (ag->mii_bus) {
892 mutex_lock(&ag->mii_bus->mdio_lock);
893 ag->mii_bus->reset(ag->mii_bus);
894 mutex_unlock(&ag->mii_bus->mdio_lock);
895 }
896
897 err = ag71xx_phy_connect(ag);
898 if (err)
899 goto err_unregister_netdev;
900
901 platform_set_drvdata(pdev, dev);
902
903 return 0;
904
905 err_unregister_netdev:
906 unregister_netdev(dev);
907 err_free_irq:
908 free_irq(dev->irq, dev);
909 err_unmap_mii_ctrl:
910 iounmap(ag->mii_ctrl);
911 err_unmap_base2:
912 iounmap(ag->mac_base2);
913 err_unmap_base1:
914 iounmap(ag->mac_base);
915 err_free_dev:
916 kfree(dev);
917 err_out:
918 platform_set_drvdata(pdev, NULL);
919 return err;
920 }
921
922 static int __exit ag71xx_remove(struct platform_device *pdev)
923 {
924 struct net_device *dev = platform_get_drvdata(pdev);
925
926 if (dev) {
927 struct ag71xx *ag = netdev_priv(dev);
928
929 ag71xx_phy_disconnect(ag);
930 unregister_netdev(dev);
931 free_irq(dev->irq, dev);
932 iounmap(ag->mii_ctrl);
933 iounmap(ag->mac_base2);
934 iounmap(ag->mac_base);
935 kfree(dev);
936 platform_set_drvdata(pdev, NULL);
937 }
938
939 return 0;
940 }
941
942 static struct platform_driver ag71xx_driver = {
943 .probe = ag71xx_probe,
944 .remove = __exit_p(ag71xx_remove),
945 .driver = {
946 .name = AG71XX_DRV_NAME,
947 }
948 };
949
950 static int __init ag71xx_module_init(void)
951 {
952 int ret;
953
954 ret = ag71xx_mdio_driver_init();
955 if (ret)
956 goto err_out;
957
958 ret = platform_driver_register(&ag71xx_driver);
959 if (ret)
960 goto err_mdio_exit;
961
962 return 0;
963
964 err_mdio_exit:
965 ag71xx_mdio_driver_exit();
966 err_out:
967 return ret;
968 }
969
970 static void __exit ag71xx_module_exit(void)
971 {
972 platform_driver_unregister(&ag71xx_driver);
973 ag71xx_mdio_driver_exit();
974 }
975
976 module_init(ag71xx_module_init);
977 module_exit(ag71xx_module_exit);
978
979 MODULE_VERSION(AG71XX_DRV_VERSION);
980 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
981 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
982 MODULE_LICENSE("GPL v2");
983 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);