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ag71xx driver: interrupt status is masked by hw, don't mask it again
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs)
89 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
90 ring->descs, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95 int err;
96
97 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
98 &ring->descs_dma,
99 GFP_ATOMIC);
100 if (!ring->descs) {
101 err = -ENOMEM;
102 goto err;
103 }
104
105 ring->size = size;
106
107 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
108 if (!ring->buf) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113 return 0;
114
115 err:
116 return err;
117 }
118
119 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
120 {
121 struct ag71xx_ring *ring = &ag->tx_ring;
122 struct net_device *dev = ag->dev;
123
124 while (ring->curr != ring->dirty) {
125 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
126
127 if (!ag71xx_desc_empty(&ring->descs[i])) {
128 ring->descs[i].ctrl = 0;
129 dev->stats.tx_errors++;
130 }
131
132 if (ring->buf[i].skb)
133 dev_kfree_skb_any(ring->buf[i].skb);
134
135 ring->buf[i].skb = NULL;
136
137 ring->dirty++;
138 }
139
140 /* flush descriptors */
141 wmb();
142
143 }
144
145 static void ag71xx_ring_tx_init(struct ag71xx *ag)
146 {
147 struct ag71xx_ring *ring = &ag->tx_ring;
148 int i;
149
150 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
151 ring->descs[i].next = (u32) (ring->descs_dma +
152 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
153
154 ring->descs[i].ctrl = DESC_EMPTY;
155 ring->buf[i].skb = NULL;
156 }
157
158 /* flush descriptors */
159 wmb();
160
161 ring->curr = 0;
162 ring->dirty = 0;
163 }
164
165 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
166 {
167 struct ag71xx_ring *ring = &ag->rx_ring;
168 int i;
169
170 if (!ring->buf)
171 return;
172
173 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
174 if (ring->buf[i].skb)
175 kfree_skb(ring->buf[i].skb);
176
177 }
178
179 static int ag71xx_ring_rx_init(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 unsigned int i;
183 int ret;
184
185 ret = 0;
186 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
187 ring->descs[i].next = (u32) (ring->descs_dma +
188 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
189
190 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
191 struct sk_buff *skb;
192
193 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
194 if (!skb) {
195 ret = -ENOMEM;
196 break;
197 }
198
199 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
200 DMA_FROM_DEVICE);
201
202 skb->dev = ag->dev;
203 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
204
205 ring->buf[i].skb = skb;
206 ring->descs[i].data = virt_to_phys(skb->data);
207 ring->descs[i].ctrl = DESC_EMPTY;
208 }
209
210 /* flush descriptors */
211 wmb();
212
213 ring->curr = 0;
214 ring->dirty = 0;
215
216 return ret;
217 }
218
219 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
220 {
221 struct ag71xx_ring *ring = &ag->rx_ring;
222 unsigned int count;
223
224 count = 0;
225 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
226 unsigned int i;
227
228 i = ring->dirty % AG71XX_RX_RING_SIZE;
229
230 if (ring->buf[i].skb == NULL) {
231 struct sk_buff *skb;
232
233 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
234 if (skb == NULL) {
235 printk(KERN_ERR "%s: no memory for skb\n",
236 ag->dev->name);
237 break;
238 }
239
240 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
241 DMA_FROM_DEVICE);
242
243 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
244 skb->dev = ag->dev;
245
246 ring->buf[i].skb = skb;
247 ring->descs[i].data = virt_to_phys(skb->data);
248 }
249
250 ring->descs[i].ctrl = DESC_EMPTY;
251 count++;
252 }
253
254 /* flush descriptors */
255 wmb();
256
257 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
258
259 return count;
260 }
261
262 static int ag71xx_rings_init(struct ag71xx *ag)
263 {
264 int ret;
265
266 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
267 if (ret)
268 return ret;
269
270 ag71xx_ring_tx_init(ag);
271
272 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
273 if (ret)
274 return ret;
275
276 ret = ag71xx_ring_rx_init(ag);
277 return ret;
278 }
279
280 static void ag71xx_rings_cleanup(struct ag71xx *ag)
281 {
282 ag71xx_ring_rx_clean(ag);
283 ag71xx_ring_free(&ag->rx_ring);
284
285 ag71xx_ring_tx_clean(ag);
286 ag71xx_ring_free(&ag->tx_ring);
287 }
288
289 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
290 {
291 u32 t;
292
293 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
294 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
295
296 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
297
298 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
299 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
300 }
301
302 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
303 MAC_CFG1_SRX | MAC_CFG1_STX)
304 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
305
306 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
307 MAC_CFG1_SRX | MAC_CFG1_STX | \
308 MAC_CFG1_TFC | MAC_CFG1_RFC)
309 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
310
311 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
312
313 static void ag71xx_dma_reset(struct ag71xx *ag)
314 {
315 int i;
316
317 ag71xx_dump_dma_regs(ag);
318
319 /* stop RX and TX */
320 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
321 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
322
323 /* clear descriptor addresses */
324 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
325 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
326
327 /* clear pending RX/TX interrupts */
328 for (i = 0; i < 256; i++) {
329 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
330 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
331 }
332
333 /* clear pending errors */
334 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
335 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
336
337 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
338 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
339 ag->dev->name);
340
341 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
342 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
343 ag->dev->name);
344
345 ag71xx_dump_dma_regs(ag);
346 }
347
348 static void ag71xx_hw_init(struct ag71xx *ag)
349 {
350 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
351
352 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
353 udelay(20);
354
355 ar71xx_device_stop(pdata->reset_bit);
356 mdelay(100);
357 ar71xx_device_start(pdata->reset_bit);
358 mdelay(100);
359
360 /* setup MAC configuration registers */
361 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
362 pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
363 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
364 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
365
366 /* setup max frame length */
367 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
368
369 /* setup MII interface type */
370 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
371
372 /* setup FIFO configuration registers */
373 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
374 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
375 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
376 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
377 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
378 pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
379 : AR71XX_FIFO_CFG5_INIT);
380
381 ag71xx_dma_reset(ag);
382 }
383
384 static void ag71xx_hw_start(struct ag71xx *ag)
385 {
386 /* start RX engine */
387 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
388
389 /* enable interrupts */
390 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
391 }
392
393 static void ag71xx_hw_stop(struct ag71xx *ag)
394 {
395 /* disable all interrupts */
396 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
397
398 ag71xx_dma_reset(ag);
399 }
400
401 static int ag71xx_open(struct net_device *dev)
402 {
403 struct ag71xx *ag = netdev_priv(dev);
404 int ret;
405
406 ret = ag71xx_rings_init(ag);
407 if (ret)
408 goto err;
409
410 napi_enable(&ag->napi);
411
412 netif_carrier_off(dev);
413 ag71xx_phy_start(ag);
414
415 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
416 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
417
418 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
419
420 ag71xx_hw_start(ag);
421
422 netif_start_queue(dev);
423
424 return 0;
425
426 err:
427 ag71xx_rings_cleanup(ag);
428 return ret;
429 }
430
431 static int ag71xx_stop(struct net_device *dev)
432 {
433 struct ag71xx *ag = netdev_priv(dev);
434 unsigned long flags;
435
436 spin_lock_irqsave(&ag->lock, flags);
437
438 netif_stop_queue(dev);
439
440 ag71xx_hw_stop(ag);
441
442 netif_carrier_off(dev);
443 ag71xx_phy_stop(ag);
444
445 napi_disable(&ag->napi);
446
447 spin_unlock_irqrestore(&ag->lock, flags);
448
449 ag71xx_rings_cleanup(ag);
450
451 return 0;
452 }
453
454 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
455 {
456 struct ag71xx *ag = netdev_priv(dev);
457 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
458 struct ag71xx_ring *ring = &ag->tx_ring;
459 struct ag71xx_desc *desc;
460 unsigned long flags;
461 int i;
462
463 i = ring->curr % AG71XX_TX_RING_SIZE;
464 desc = &ring->descs[i];
465
466 spin_lock_irqsave(&ag->lock, flags);
467 pdata->ddr_flush();
468 spin_unlock_irqrestore(&ag->lock, flags);
469
470 if (!ag71xx_desc_empty(desc))
471 goto err_drop;
472
473 if (skb->len <= 0) {
474 DBG("%s: packet len is too small\n", ag->dev->name);
475 goto err_drop;
476 }
477
478 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
479
480 ring->buf[i].skb = skb;
481
482 /* setup descriptor fields */
483 desc->data = virt_to_phys(skb->data);
484 desc->ctrl = (skb->len & DESC_PKTLEN_M);
485
486 /* flush descriptor */
487 wmb();
488
489 ring->curr++;
490 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
491 DBG("%s: tx queue full\n", ag->dev->name);
492 netif_stop_queue(dev);
493 }
494
495 DBG("%s: packet injected into TX queue\n", ag->dev->name);
496
497 /* enable TX engine */
498 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
499
500 dev->trans_start = jiffies;
501
502 return 0;
503
504 err_drop:
505 dev->stats.tx_dropped++;
506
507 dev_kfree_skb(skb);
508 return 0;
509 }
510
511 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
512 {
513 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
514 struct ag71xx *ag = netdev_priv(dev);
515 int ret;
516
517 switch (cmd) {
518 case SIOCETHTOOL:
519 if (ag->phy_dev == NULL)
520 break;
521
522 spin_lock_irq(&ag->lock);
523 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
524 spin_unlock_irq(&ag->lock);
525 return ret;
526
527 case SIOCSIFHWADDR:
528 if (copy_from_user
529 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
530 return -EFAULT;
531 return 0;
532
533 case SIOCGIFHWADDR:
534 if (copy_to_user
535 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
536 return -EFAULT;
537 return 0;
538
539 case SIOCGMIIPHY:
540 case SIOCGMIIREG:
541 case SIOCSMIIREG:
542 if (ag->phy_dev == NULL)
543 break;
544
545 return phy_mii_ioctl(ag->phy_dev, data, cmd);
546
547 default:
548 break;
549 }
550
551 return -EOPNOTSUPP;
552 }
553
554 static void ag71xx_tx_timeout(struct net_device *dev)
555 {
556 struct ag71xx *ag = netdev_priv(dev);
557
558 if (netif_msg_tx_err(ag))
559 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
560
561 schedule_work(&ag->restart_work);
562 }
563
564 static void ag71xx_restart_work_func(struct work_struct *work)
565 {
566 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
567
568 ag71xx_stop(ag->dev);
569 ag71xx_open(ag->dev);
570 }
571
572 static void ag71xx_tx_packets(struct ag71xx *ag)
573 {
574 struct ag71xx_ring *ring = &ag->tx_ring;
575 unsigned int sent;
576
577 DBG("%s: processing TX ring\n", ag->dev->name);
578
579 sent = 0;
580 while (ring->dirty != ring->curr) {
581 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
582 struct ag71xx_desc *desc = &ring->descs[i];
583 struct sk_buff *skb = ring->buf[i].skb;
584
585 if (!ag71xx_desc_empty(desc))
586 break;
587
588 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
589
590 ag->dev->stats.tx_bytes += skb->len;
591 ag->dev->stats.tx_packets++;
592
593 dev_kfree_skb_any(skb);
594 ring->buf[i].skb = NULL;
595
596 ring->dirty++;
597 sent++;
598 }
599
600 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
601
602 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
603 netif_wake_queue(ag->dev);
604
605 }
606
607 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
608 {
609 struct net_device *dev = ag->dev;
610 struct ag71xx_ring *ring = &ag->rx_ring;
611 int done = 0;
612
613 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
614 dev->name, limit, ring->curr, ring->dirty);
615
616 while (done < limit) {
617 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
618 struct ag71xx_desc *desc = &ring->descs[i];
619 struct sk_buff *skb;
620 int pktlen;
621
622 if (ag71xx_desc_empty(desc))
623 break;
624
625 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
626 ag71xx_assert(0);
627 break;
628 }
629
630 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
631
632 skb = ring->buf[i].skb;
633 pktlen = ag71xx_desc_pktlen(desc);
634 pktlen -= ETH_FCS_LEN;
635
636 skb_put(skb, pktlen);
637
638 skb->dev = dev;
639 skb->protocol = eth_type_trans(skb, dev);
640 skb->ip_summed = CHECKSUM_NONE;
641
642 netif_receive_skb(skb);
643
644 dev->last_rx = jiffies;
645 dev->stats.rx_packets++;
646 dev->stats.rx_bytes += pktlen;
647
648 ring->buf[i].skb = NULL;
649 done++;
650
651 ring->curr++;
652 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
653 ag71xx_ring_rx_refill(ag);
654 }
655
656 ag71xx_ring_rx_refill(ag);
657
658 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
659 dev->name, ring->curr, ring->dirty, done);
660
661 return done;
662 }
663
664 static int ag71xx_poll(struct napi_struct *napi, int limit)
665 {
666 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
667 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
668 struct net_device *dev = ag->dev;
669 unsigned long flags;
670 u32 status;
671 int done;
672
673 pdata->ddr_flush();
674 ag71xx_tx_packets(ag);
675
676 DBG("%s: processing RX ring\n", dev->name);
677 done = ag71xx_rx_packets(ag, limit);
678
679 /* TODO: add OOM handler */
680
681 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
682 if (unlikely(status & RX_STATUS_OF)) {
683 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
684 dev->stats.rx_fifo_errors++;
685
686 /* restart RX */
687 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
688 }
689
690 if (done < limit) {
691 if (status & RX_STATUS_PR)
692 goto more;
693
694 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
695 if (status & TX_STATUS_PS)
696 goto more;
697
698 DBG("%s: disable polling mode, done=%d, limit=%d\n",
699 dev->name, done, limit);
700
701 netif_rx_complete(dev, napi);
702
703 /* enable interrupts */
704 spin_lock_irqsave(&ag->lock, flags);
705 ag71xx_int_enable(ag, AG71XX_INT_POLL);
706 spin_unlock_irqrestore(&ag->lock, flags);
707 return done;
708 }
709
710 more:
711 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
712 dev->name, done, limit);
713 return done;
714 }
715
716 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
717 {
718 struct net_device *dev = dev_id;
719 struct ag71xx *ag = netdev_priv(dev);
720 u32 status;
721
722 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
723 ag71xx_dump_intr(ag, "raw", status);
724
725 if (unlikely(!status))
726 return IRQ_NONE;
727
728 if (unlikely(status & AG71XX_INT_ERR)) {
729 if (status & AG71XX_INT_TX_BE) {
730 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
731 dev_err(&dev->dev, "TX BUS error\n");
732 }
733 if (status & AG71XX_INT_RX_BE) {
734 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
735 dev_err(&dev->dev, "RX BUS error\n");
736 }
737 }
738
739 if (likely(status & AG71XX_INT_POLL)) {
740 ag71xx_int_disable(ag, AG71XX_INT_POLL);
741 DBG("%s: enable polling mode\n", dev->name);
742 netif_rx_schedule(dev, &ag->napi);
743 }
744
745 return IRQ_HANDLED;
746 }
747
748 static void ag71xx_set_multicast_list(struct net_device *dev)
749 {
750 /* TODO */
751 }
752
753 static int __init ag71xx_probe(struct platform_device *pdev)
754 {
755 struct net_device *dev;
756 struct resource *res;
757 struct ag71xx *ag;
758 struct ag71xx_platform_data *pdata;
759 int err;
760
761 pdata = pdev->dev.platform_data;
762 if (!pdata) {
763 dev_err(&pdev->dev, "no platform data specified\n");
764 err = -ENXIO;
765 goto err_out;
766 }
767
768 dev = alloc_etherdev(sizeof(*ag));
769 if (!dev) {
770 dev_err(&pdev->dev, "alloc_etherdev failed\n");
771 err = -ENOMEM;
772 goto err_out;
773 }
774
775 SET_NETDEV_DEV(dev, &pdev->dev);
776
777 ag = netdev_priv(dev);
778 ag->pdev = pdev;
779 ag->dev = dev;
780 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
781 ag->msg_enable = netif_msg_init(ag71xx_debug,
782 AG71XX_DEFAULT_MSG_ENABLE);
783 spin_lock_init(&ag->lock);
784
785 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
786 if (!res) {
787 dev_err(&pdev->dev, "no mac_base resource found\n");
788 err = -ENXIO;
789 goto err_out;
790 }
791
792 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
793 if (!ag->mac_base) {
794 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
795 err = -ENOMEM;
796 goto err_free_dev;
797 }
798
799 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
800 if (!res) {
801 dev_err(&pdev->dev, "no mac_base2 resource found\n");
802 err = -ENXIO;
803 goto err_unmap_base1;
804 }
805
806 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
807 if (!ag->mac_base) {
808 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
809 err = -ENOMEM;
810 goto err_unmap_base1;
811 }
812
813 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
814 if (!res) {
815 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
816 err = -ENXIO;
817 goto err_unmap_base2;
818 }
819
820 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
821 if (!ag->mii_ctrl) {
822 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
823 err = -ENOMEM;
824 goto err_unmap_base2;
825 }
826
827 dev->irq = platform_get_irq(pdev, 0);
828 err = request_irq(dev->irq, ag71xx_interrupt,
829 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
830 dev->name, dev);
831 if (err) {
832 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
833 goto err_unmap_mii_ctrl;
834 }
835
836 dev->base_addr = (unsigned long)ag->mac_base;
837 dev->open = ag71xx_open;
838 dev->stop = ag71xx_stop;
839 dev->hard_start_xmit = ag71xx_hard_start_xmit;
840 dev->set_multicast_list = ag71xx_set_multicast_list;
841 dev->do_ioctl = ag71xx_do_ioctl;
842 dev->ethtool_ops = &ag71xx_ethtool_ops;
843
844 dev->tx_timeout = ag71xx_tx_timeout;
845 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
846
847 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
848
849 if (is_valid_ether_addr(pdata->mac_addr))
850 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
851 else {
852 dev->dev_addr[0] = 0xde;
853 dev->dev_addr[1] = 0xad;
854 get_random_bytes(&dev->dev_addr[2], 3);
855 dev->dev_addr[5] = pdev->id & 0xff;
856 }
857
858 err = register_netdev(dev);
859 if (err) {
860 dev_err(&pdev->dev, "unable to register net device\n");
861 goto err_free_irq;
862 }
863
864 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
865 dev->name, dev->base_addr, dev->irq);
866
867 ag71xx_dump_regs(ag);
868
869 ag71xx_hw_init(ag);
870
871 ag71xx_dump_regs(ag);
872
873 /* Reset the mdio bus explicitly */
874 if (ag->mii_bus) {
875 mutex_lock(&ag->mii_bus->mdio_lock);
876 ag->mii_bus->reset(ag->mii_bus);
877 mutex_unlock(&ag->mii_bus->mdio_lock);
878 }
879
880 err = ag71xx_phy_connect(ag);
881 if (err)
882 goto err_unregister_netdev;
883
884 platform_set_drvdata(pdev, dev);
885
886 return 0;
887
888 err_unregister_netdev:
889 unregister_netdev(dev);
890 err_free_irq:
891 free_irq(dev->irq, dev);
892 err_unmap_mii_ctrl:
893 iounmap(ag->mii_ctrl);
894 err_unmap_base2:
895 iounmap(ag->mac_base2);
896 err_unmap_base1:
897 iounmap(ag->mac_base);
898 err_free_dev:
899 kfree(dev);
900 err_out:
901 platform_set_drvdata(pdev, NULL);
902 return err;
903 }
904
905 static int __exit ag71xx_remove(struct platform_device *pdev)
906 {
907 struct net_device *dev = platform_get_drvdata(pdev);
908
909 if (dev) {
910 struct ag71xx *ag = netdev_priv(dev);
911
912 ag71xx_phy_disconnect(ag);
913 unregister_netdev(dev);
914 free_irq(dev->irq, dev);
915 iounmap(ag->mii_ctrl);
916 iounmap(ag->mac_base2);
917 iounmap(ag->mac_base);
918 kfree(dev);
919 platform_set_drvdata(pdev, NULL);
920 }
921
922 return 0;
923 }
924
925 static struct platform_driver ag71xx_driver = {
926 .probe = ag71xx_probe,
927 .remove = __exit_p(ag71xx_remove),
928 .driver = {
929 .name = AG71XX_DRV_NAME,
930 }
931 };
932
933 static int __init ag71xx_module_init(void)
934 {
935 int ret;
936
937 ret = ag71xx_mdio_driver_init();
938 if (ret)
939 goto err_out;
940
941 ret = platform_driver_register(&ag71xx_driver);
942 if (ret)
943 goto err_mdio_exit;
944
945 return 0;
946
947 err_mdio_exit:
948 ag71xx_mdio_driver_exit();
949 err_out:
950 return ret;
951 }
952
953 static void __exit ag71xx_module_exit(void)
954 {
955 platform_driver_unregister(&ag71xx_driver);
956 ag71xx_mdio_driver_exit();
957 }
958
959 module_init(ag71xx_module_init);
960 module_exit(ag71xx_module_exit);
961
962 MODULE_VERSION(AG71XX_DRV_VERSION);
963 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
964 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
965 MODULE_LICENSE("GPL v2");
966 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository