target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #ifndef __AG71XX_H
  15 #define __AG71XX_H
  16
  17 #include <linux/kernel.h>
  18 #include <linux/version.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/types.h>
  22 #include <linux/random.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/phy.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/workqueue.h>
  33
  34 #include <linux/bitops.h>
  35
  36 #include <asm/mach-ath79/ar71xx_regs.h>
  37 #include <asm/mach-ath79/ath79.h>
  38 #include <asm/mach-ath79/ag71xx_platform.h>
  39
  40 #define AG71XX_DRV_NAME         "ag71xx"
  41 #define AG71XX_DRV_VERSION      "0.5.35"
  42
  43 /*
  44  * For our NAPI weight bigger does *NOT* mean better - it means more
  45  * D-cache misses and lots more wasted cycles than we'll ever
  46  * possibly gain from saving instructions.
  47  */
  48 #define AG71XX_NAPI_WEIGHT      32
  49 #define AG71XX_OOM_REFILL       (1 + HZ/10)
  50
  51 #define AG71XX_INT_ERR  (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  52 #define AG71XX_INT_TX   (AG71XX_INT_TX_PS)
  53 #define AG71XX_INT_RX   (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  54
  55 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  56 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  57
  58 #define AG71XX_TX_MTU_LEN       1540
  59
  60 #define AG71XX_TX_RING_SPLIT            512
  61 #define AG71XX_TX_RING_DS_PER_PKT       DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
  62                                                      AG71XX_TX_RING_SPLIT)
  63 #define AG71XX_TX_RING_SIZE_DEFAULT     128
  64 #define AG71XX_RX_RING_SIZE_DEFAULT     256
  65
  66 #define AG71XX_TX_RING_SIZE_MAX         128
  67 #define AG71XX_RX_RING_SIZE_MAX         256
  68
  69 #ifdef CONFIG_AG71XX_DEBUG
  70 #define DBG(fmt, args...)       pr_debug(fmt, ## args)
  71 #else
  72 #define DBG(fmt, args...)       do {} while (0)
  73 #endif
  74
  75 #define ag71xx_assert(_cond)                                            \
  76 do {                                                                    \
  77         if (_cond)                                                      \
  78                 break;                                                  \
  79         printk("%s,%d: assertion failed\n", __FILE__, __LINE__);        \
  80         BUG();                                                          \
  81 } while (0)
  82
  83 struct ag71xx_desc {
  84         u32     data;
  85         u32     ctrl;
  86 #define DESC_EMPTY      BIT(31)
  87 #define DESC_MORE       BIT(24)
  88 #define DESC_PKTLEN_M   0xfff
  89         u32     next;
  90         u32     pad;
  91 } __attribute__((aligned(4)));
  92
  93 #define AG71XX_DESC_SIZE        roundup(sizeof(struct ag71xx_desc), \
  94                                         L1_CACHE_BYTES)
  95
  96 struct ag71xx_buf {
  97         union {
  98                 struct sk_buff  *skb;
  99                 void            *rx_buf;
 100         };
 101         union {
 102                 dma_addr_t      dma_addr;
 103                 unsigned int            len;
 104         };
 105 };
 106
 107 struct ag71xx_ring {
 108         struct ag71xx_buf       *buf;
 109         u8                      *descs_cpu;
 110         dma_addr_t              descs_dma;
 111         u16                     desc_split;
 112         u16                     order;
 113         unsigned int            curr;
 114         unsigned int            dirty;
 115 };
 116
 117 struct ag71xx_mdio {
 118         struct mii_bus          *mii_bus;
 119 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
 120         int                     mii_irq[PHY_MAX_ADDR];
 121 #endif
 122         void __iomem            *mdio_base;
 123         struct ag71xx_mdio_platform_data *pdata;
 124 };
 125
 126 struct ag71xx_int_stats {
 127         unsigned long           rx_pr;
 128         unsigned long           rx_be;
 129         unsigned long           rx_of;
 130         unsigned long           tx_ps;
 131         unsigned long           tx_be;
 132         unsigned long           tx_ur;
 133         unsigned long           total;
 134 };
 135
 136 struct ag71xx_napi_stats {
 137         unsigned long           napi_calls;
 138         unsigned long           rx_count;
 139         unsigned long           rx_packets;
 140         unsigned long           rx_packets_max;
 141         unsigned long           tx_count;
 142         unsigned long           tx_packets;
 143         unsigned long           tx_packets_max;
 144
 145         unsigned long           rx[AG71XX_NAPI_WEIGHT + 1];
 146         unsigned long           tx[AG71XX_NAPI_WEIGHT + 1];
 147 };
 148
 149 struct ag71xx_debug {
 150         struct dentry           *debugfs_dir;
 151
 152         struct ag71xx_int_stats int_stats;
 153         struct ag71xx_napi_stats napi_stats;
 154 };
 155
 156 struct ag71xx {
 157         /*
 158          * Critical data related to the per-packet data path are clustered
 159          * early in this structure to help improve the D-cache footprint.
 160          */
 161         struct ag71xx_ring      rx_ring ____cacheline_aligned;
 162         struct ag71xx_ring      tx_ring ____cacheline_aligned;
 163
 164         unsigned int            max_frame_len;
 165         unsigned int            desc_pktlen_mask;
 166         unsigned int            rx_buf_size;
 167
 168         struct net_device       *dev;
 169         struct platform_device  *pdev;
 170         spinlock_t              lock;
 171         struct napi_struct      napi;
 172         u32                     msg_enable;
 173
 174         /*
 175          * From this point onwards we're not looking at per-packet fields.
 176          */
 177         void __iomem            *mac_base;
 178
 179         struct ag71xx_desc      *stop_desc;
 180         dma_addr_t              stop_desc_dma;
 181
 182         struct mii_bus          *mii_bus;
 183         struct phy_device       *phy_dev;
 184         void                    *phy_priv;
 185
 186         unsigned int            link;
 187         unsigned int            speed;
 188         int                     duplex;
 189
 190         struct delayed_work     restart_work;
 191         struct delayed_work     link_work;
 192         struct timer_list       oom_timer;
 193
 194 #ifdef CONFIG_AG71XX_DEBUG_FS
 195         struct ag71xx_debug     debug;
 196 #endif
 197 };
 198
 199 extern struct ethtool_ops ag71xx_ethtool_ops;
 200 void ag71xx_link_adjust(struct ag71xx *ag);
 201
 202 int ag71xx_mdio_driver_init(void) __init;
 203 void ag71xx_mdio_driver_exit(void);
 204
 205 int ag71xx_phy_connect(struct ag71xx *ag);
 206 void ag71xx_phy_disconnect(struct ag71xx *ag);
 207 void ag71xx_phy_start(struct ag71xx *ag);
 208 void ag71xx_phy_stop(struct ag71xx *ag);
 209
 210 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
 211 {
 212         return ag->pdev->dev.platform_data;
 213 }
 214
 215 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
 216 {
 217         return (desc->ctrl & DESC_EMPTY) != 0;
 218 }
 219
 220 static inline struct ag71xx_desc *
 221 ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
 222 {
 223         return (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE];
 224 }
 225
 226 static inline int
 227 ag71xx_ring_size_order(int size)
 228 {
 229         return fls(size - 1);
 230 }
 231
 232 /* Register offsets */
 233 #define AG71XX_REG_MAC_CFG1     0x0000
 234 #define AG71XX_REG_MAC_CFG2     0x0004
 235 #define AG71XX_REG_MAC_IPG      0x0008
 236 #define AG71XX_REG_MAC_HDX      0x000c
 237 #define AG71XX_REG_MAC_MFL      0x0010
 238 #define AG71XX_REG_MII_CFG      0x0020
 239 #define AG71XX_REG_MII_CMD      0x0024
 240 #define AG71XX_REG_MII_ADDR     0x0028
 241 #define AG71XX_REG_MII_CTRL     0x002c
 242 #define AG71XX_REG_MII_STATUS   0x0030
 243 #define AG71XX_REG_MII_IND      0x0034
 244 #define AG71XX_REG_MAC_IFCTL    0x0038
 245 #define AG71XX_REG_MAC_ADDR1    0x0040
 246 #define AG71XX_REG_MAC_ADDR2    0x0044
 247 #define AG71XX_REG_FIFO_CFG0    0x0048
 248 #define AG71XX_REG_FIFO_CFG1    0x004c
 249 #define AG71XX_REG_FIFO_CFG2    0x0050
 250 #define AG71XX_REG_FIFO_CFG3    0x0054
 251 #define AG71XX_REG_FIFO_CFG4    0x0058
 252 #define AG71XX_REG_FIFO_CFG5    0x005c
 253 #define AG71XX_REG_FIFO_RAM0    0x0060
 254 #define AG71XX_REG_FIFO_RAM1    0x0064
 255 #define AG71XX_REG_FIFO_RAM2    0x0068
 256 #define AG71XX_REG_FIFO_RAM3    0x006c
 257 #define AG71XX_REG_FIFO_RAM4    0x0070
 258 #define AG71XX_REG_FIFO_RAM5    0x0074
 259 #define AG71XX_REG_FIFO_RAM6    0x0078
 260 #define AG71XX_REG_FIFO_RAM7    0x007c
 261
 262 #define AG71XX_REG_TX_CTRL      0x0180
 263 #define AG71XX_REG_TX_DESC      0x0184
 264 #define AG71XX_REG_TX_STATUS    0x0188
 265 #define AG71XX_REG_RX_CTRL      0x018c
 266 #define AG71XX_REG_RX_DESC      0x0190
 267 #define AG71XX_REG_RX_STATUS    0x0194
 268 #define AG71XX_REG_INT_ENABLE   0x0198
 269 #define AG71XX_REG_INT_STATUS   0x019c
 270
 271 #define AG71XX_REG_FIFO_DEPTH   0x01a8
 272 #define AG71XX_REG_RX_SM        0x01b0
 273 #define AG71XX_REG_TX_SM        0x01b4
 274
 275 #define MAC_CFG1_TXE            BIT(0)  /* Tx Enable */
 276 #define MAC_CFG1_STX            BIT(1)  /* Synchronize Tx Enable */
 277 #define MAC_CFG1_RXE            BIT(2)  /* Rx Enable */
 278 #define MAC_CFG1_SRX            BIT(3)  /* Synchronize Rx Enable */
 279 #define MAC_CFG1_TFC            BIT(4)  /* Tx Flow Control Enable */
 280 #define MAC_CFG1_RFC            BIT(5)  /* Rx Flow Control Enable */
 281 #define MAC_CFG1_LB             BIT(8)  /* Loopback mode */
 282 #define MAC_CFG1_SR             BIT(31) /* Soft Reset */
 283
 284 #define MAC_CFG2_FDX            BIT(0)
 285 #define MAC_CFG2_CRC_EN         BIT(1)
 286 #define MAC_CFG2_PAD_CRC_EN     BIT(2)
 287 #define MAC_CFG2_LEN_CHECK      BIT(4)
 288 #define MAC_CFG2_HUGE_FRAME_EN  BIT(5)
 289 #define MAC_CFG2_IF_1000        BIT(9)
 290 #define MAC_CFG2_IF_10_100      BIT(8)
 291
 292 #define FIFO_CFG0_WTM           BIT(0)  /* Watermark Module */
 293 #define FIFO_CFG0_RXS           BIT(1)  /* Rx System Module */
 294 #define FIFO_CFG0_RXF           BIT(2)  /* Rx Fabric Module */
 295 #define FIFO_CFG0_TXS           BIT(3)  /* Tx System Module */
 296 #define FIFO_CFG0_TXF           BIT(4)  /* Tx Fabric Module */
 297 #define FIFO_CFG0_ALL   (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
 298                         | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
 299
 300 #define FIFO_CFG0_ENABLE_SHIFT  8
 301
 302 #define FIFO_CFG4_DE            BIT(0)  /* Drop Event */
 303 #define FIFO_CFG4_DV            BIT(1)  /* RX_DV Event */
 304 #define FIFO_CFG4_FC            BIT(2)  /* False Carrier */
 305 #define FIFO_CFG4_CE            BIT(3)  /* Code Error */
 306 #define FIFO_CFG4_CR            BIT(4)  /* CRC error */
 307 #define FIFO_CFG4_LM            BIT(5)  /* Length Mismatch */
 308 #define FIFO_CFG4_LO            BIT(6)  /* Length out of range */
 309 #define FIFO_CFG4_OK            BIT(7)  /* Packet is OK */
 310 #define FIFO_CFG4_MC            BIT(8)  /* Multicast Packet */
 311 #define FIFO_CFG4_BC            BIT(9)  /* Broadcast Packet */
 312 #define FIFO_CFG4_DR            BIT(10) /* Dribble */
 313 #define FIFO_CFG4_LE            BIT(11) /* Long Event */
 314 #define FIFO_CFG4_CF            BIT(12) /* Control Frame */
 315 #define FIFO_CFG4_PF            BIT(13) /* Pause Frame */
 316 #define FIFO_CFG4_UO            BIT(14) /* Unsupported Opcode */
 317 #define FIFO_CFG4_VT            BIT(15) /* VLAN tag detected */
 318 #define FIFO_CFG4_FT            BIT(16) /* Frame Truncated */
 319 #define FIFO_CFG4_UC            BIT(17) /* Unicast Packet */
 320
 321 #define FIFO_CFG5_DE            BIT(0)  /* Drop Event */
 322 #define FIFO_CFG5_DV            BIT(1)  /* RX_DV Event */
 323 #define FIFO_CFG5_FC            BIT(2)  /* False Carrier */
 324 #define FIFO_CFG5_CE            BIT(3)  /* Code Error */
 325 #define FIFO_CFG5_LM            BIT(4)  /* Length Mismatch */
 326 #define FIFO_CFG5_LO            BIT(5)  /* Length Out of Range */
 327 #define FIFO_CFG5_OK            BIT(6)  /* Packet is OK */
 328 #define FIFO_CFG5_MC            BIT(7)  /* Multicast Packet */
 329 #define FIFO_CFG5_BC            BIT(8)  /* Broadcast Packet */
 330 #define FIFO_CFG5_DR            BIT(9)  /* Dribble */
 331 #define FIFO_CFG5_CF            BIT(10) /* Control Frame */
 332 #define FIFO_CFG5_PF            BIT(11) /* Pause Frame */
 333 #define FIFO_CFG5_UO            BIT(12) /* Unsupported Opcode */
 334 #define FIFO_CFG5_VT            BIT(13) /* VLAN tag detected */
 335 #define FIFO_CFG5_LE            BIT(14) /* Long Event */
 336 #define FIFO_CFG5_FT            BIT(15) /* Frame Truncated */
 337 #define FIFO_CFG5_16            BIT(16) /* unknown */
 338 #define FIFO_CFG5_17            BIT(17) /* unknown */
 339 #define FIFO_CFG5_SF            BIT(18) /* Short Frame */
 340 #define FIFO_CFG5_BM            BIT(19) /* Byte Mode */
 341
 342 #define AG71XX_INT_TX_PS        BIT(0)
 343 #define AG71XX_INT_TX_UR        BIT(1)
 344 #define AG71XX_INT_TX_BE        BIT(3)
 345 #define AG71XX_INT_RX_PR        BIT(4)
 346 #define AG71XX_INT_RX_OF        BIT(6)
 347 #define AG71XX_INT_RX_BE        BIT(7)
 348
 349 #define MAC_IFCTL_SPEED         BIT(16)
 350
 351 #define MII_CFG_CLK_DIV_4       0
 352 #define MII_CFG_CLK_DIV_6       2
 353 #define MII_CFG_CLK_DIV_8       3
 354 #define MII_CFG_CLK_DIV_10      4
 355 #define MII_CFG_CLK_DIV_14      5
 356 #define MII_CFG_CLK_DIV_20      6
 357 #define MII_CFG_CLK_DIV_28      7
 358 #define MII_CFG_CLK_DIV_34      8
 359 #define MII_CFG_CLK_DIV_42      9
 360 #define MII_CFG_CLK_DIV_50      10
 361 #define MII_CFG_CLK_DIV_58      11
 362 #define MII_CFG_CLK_DIV_66      12
 363 #define MII_CFG_CLK_DIV_74      13
 364 #define MII_CFG_CLK_DIV_82      14
 365 #define MII_CFG_CLK_DIV_98      15
 366 #define MII_CFG_RESET           BIT(31)
 367
 368 #define MII_CMD_WRITE           0x0
 369 #define MII_CMD_READ            0x1
 370 #define MII_ADDR_SHIFT          8
 371 #define MII_IND_BUSY            BIT(0)
 372 #define MII_IND_INVALID         BIT(2)
 373
 374 #define TX_CTRL_TXE             BIT(0)  /* Tx Enable */
 375
 376 #define TX_STATUS_PS            BIT(0)  /* Packet Sent */
 377 #define TX_STATUS_UR            BIT(1)  /* Tx Underrun */
 378 #define TX_STATUS_BE            BIT(3)  /* Bus Error */
 379
 380 #define RX_CTRL_RXE             BIT(0)  /* Rx Enable */
 381
 382 #define RX_STATUS_PR            BIT(0)  /* Packet Received */
 383 #define RX_STATUS_OF            BIT(2)  /* Rx Overflow */
 384 #define RX_STATUS_BE            BIT(3)  /* Bus Error */
 385
 386 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
 387 {
 388         switch (reg) {
 389         case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 390         case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
 391         case AG71XX_REG_MII_CFG:
 392                 break;
 393
 394         default:
 395                 BUG();
 396         }
 397 }
 398
 399 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 400 {
 401         ag71xx_check_reg_offset(ag, reg);
 402
 403         __raw_writel(value, ag->mac_base + reg);
 404         /* flush write */
 405         (void) __raw_readl(ag->mac_base + reg);
 406 }
 407
 408 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 409 {
 410         ag71xx_check_reg_offset(ag, reg);
 411
 412         return __raw_readl(ag->mac_base + reg);
 413 }
 414
 415 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
 416 {
 417         void __iomem *r;
 418
 419         ag71xx_check_reg_offset(ag, reg);
 420
 421         r = ag->mac_base + reg;
 422         __raw_writel(__raw_readl(r) | mask, r);
 423         /* flush write */
 424         (void)__raw_readl(r);
 425 }
 426
 427 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
 428 {
 429         void __iomem *r;
 430
 431         ag71xx_check_reg_offset(ag, reg);
 432
 433         r = ag->mac_base + reg;
 434         __raw_writel(__raw_readl(r) & ~mask, r);
 435         /* flush write */
 436         (void) __raw_readl(r);
 437 }
 438
 439 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
 440 {
 441         ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
 442 }
 443
 444 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 445 {
 446         ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
 447 }
 448
 449 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
 450 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
 451 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
 452                                 int pktlen);
 453 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
 454 {
 455         return ag71xx_get_pdata(ag)->has_ar8216;
 456 }
 457 #else
 458 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
 459                                            struct sk_buff *skb)
 460 {
 461 }
 462
 463 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
 464                                               struct sk_buff *skb,
 465                                               int pktlen)
 466 {
 467         return 0;
 468 }
 469 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
 470 {
 471         return 0;
 472 }
 473 #endif
 474
 475 #ifdef CONFIG_AG71XX_DEBUG_FS
 476 int ag71xx_debugfs_root_init(void);
 477 void ag71xx_debugfs_root_exit(void);
 478 int ag71xx_debugfs_init(struct ag71xx *ag);
 479 void ag71xx_debugfs_exit(struct ag71xx *ag);
 480 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
 481 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
 482 #else
 483 static inline int ag71xx_debugfs_root_init(void) { return 0; }
 484 static inline void ag71xx_debugfs_root_exit(void) {}
 485 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
 486 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
 487 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
 488                                                    u32 status) {}
 489 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
 490                                                     int rx, int tx) {}
 491 #endif /* CONFIG_AG71XX_DEBUG_FS */
 492
 493 void ag71xx_ar7240_start(struct ag71xx *ag);
 494 void ag71xx_ar7240_stop(struct ag71xx *ag);
 495 int ag71xx_ar7240_init(struct ag71xx *ag);
 496 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
 497
 498 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
 499 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
 500
 501 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
 502                       unsigned reg_addr);
 503 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
 504                        unsigned reg_addr, u16 reg_val);
 505
 506 #endif /* _AG71XX_H */