mac80211: refresh patches
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33
34 #include <linux/bitops.h>
35
36 #include <asm/mach-ath79/ar71xx_regs.h>
37 #include <asm/mach-ath79/ath79.h>
38 #include <asm/mach-ath79/ag71xx_platform.h>
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.35"
42
43 /*
44 * For our NAPI weight bigger does *NOT* mean better - it means more
45 * D-cache misses and lots more wasted cycles than we'll ever
46 * possibly gain from saving instructions.
47 */
48 #define AG71XX_NAPI_WEIGHT 32
49 #define AG71XX_OOM_REFILL (1 + HZ/10)
50
51 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
52 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
53 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
54
55 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
56 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
57
58 #define AG71XX_TX_MTU_LEN 1540
59
60 #define AG71XX_TX_RING_SPLIT 512
61 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
62 AG71XX_TX_RING_SPLIT)
63 #define AG71XX_TX_RING_SIZE_DEFAULT 128
64 #define AG71XX_RX_RING_SIZE_DEFAULT 256
65
66 #define AG71XX_TX_RING_SIZE_MAX 128
67 #define AG71XX_RX_RING_SIZE_MAX 256
68
69 #define QCA955X_SGMII_LINK_WAR_MAX_TRY 10
70
71 #ifdef CONFIG_AG71XX_DEBUG
72 #define DBG(fmt, args...) pr_debug(fmt, ## args)
73 #else
74 #define DBG(fmt, args...) do {} while (0)
75 #endif
76
77 #define ag71xx_assert(_cond) \
78 do { \
79 if (_cond) \
80 break; \
81 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
82 BUG(); \
83 } while (0)
84
85 struct ag71xx_desc {
86 u32 data;
87 u32 ctrl;
88 #define DESC_EMPTY BIT(31)
89 #define DESC_MORE BIT(24)
90 #define DESC_PKTLEN_M 0xfff
91 u32 next;
92 u32 pad;
93 } __attribute__((aligned(4)));
94
95 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \
96 L1_CACHE_BYTES)
97
98 struct ag71xx_buf {
99 union {
100 struct sk_buff *skb;
101 void *rx_buf;
102 };
103 union {
104 dma_addr_t dma_addr;
105 unsigned int len;
106 };
107 };
108
109 struct ag71xx_ring {
110 struct ag71xx_buf *buf;
111 u8 *descs_cpu;
112 dma_addr_t descs_dma;
113 u16 desc_split;
114 u16 order;
115 unsigned int curr;
116 unsigned int dirty;
117 };
118
119 struct ag71xx_mdio {
120 struct mii_bus *mii_bus;
121 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)
122 int mii_irq[PHY_MAX_ADDR];
123 #endif
124 void __iomem *mdio_base;
125 struct ag71xx_mdio_platform_data *pdata;
126 };
127
128 struct ag71xx_int_stats {
129 unsigned long rx_pr;
130 unsigned long rx_be;
131 unsigned long rx_of;
132 unsigned long tx_ps;
133 unsigned long tx_be;
134 unsigned long tx_ur;
135 unsigned long total;
136 };
137
138 struct ag71xx_napi_stats {
139 unsigned long napi_calls;
140 unsigned long rx_count;
141 unsigned long rx_packets;
142 unsigned long rx_packets_max;
143 unsigned long tx_count;
144 unsigned long tx_packets;
145 unsigned long tx_packets_max;
146
147 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
148 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
149 };
150
151 struct ag71xx_debug {
152 struct dentry *debugfs_dir;
153
154 struct ag71xx_int_stats int_stats;
155 struct ag71xx_napi_stats napi_stats;
156 };
157
158 struct ag71xx {
159 /*
160 * Critical data related to the per-packet data path are clustered
161 * early in this structure to help improve the D-cache footprint.
162 */
163 struct ag71xx_ring rx_ring ____cacheline_aligned;
164 struct ag71xx_ring tx_ring ____cacheline_aligned;
165
166 unsigned int max_frame_len;
167 unsigned int desc_pktlen_mask;
168 unsigned int rx_buf_size;
169
170 struct net_device *dev;
171 struct platform_device *pdev;
172 spinlock_t lock;
173 struct napi_struct napi;
174 u32 msg_enable;
175
176 /*
177 * From this point onwards we're not looking at per-packet fields.
178 */
179 void __iomem *mac_base;
180
181 struct ag71xx_desc *stop_desc;
182 dma_addr_t stop_desc_dma;
183
184 struct mii_bus *mii_bus;
185 struct phy_device *phy_dev;
186 void *phy_priv;
187
188 unsigned int link;
189 unsigned int speed;
190 int duplex;
191
192 struct delayed_work restart_work;
193 struct delayed_work link_work;
194 struct timer_list oom_timer;
195
196 #ifdef CONFIG_AG71XX_DEBUG_FS
197 struct ag71xx_debug debug;
198 #endif
199 };
200
201 extern struct ethtool_ops ag71xx_ethtool_ops;
202 void ag71xx_link_adjust(struct ag71xx *ag);
203
204 int ag71xx_mdio_driver_init(void) __init;
205 void ag71xx_mdio_driver_exit(void);
206
207 int ag71xx_phy_connect(struct ag71xx *ag);
208 void ag71xx_phy_disconnect(struct ag71xx *ag);
209 void ag71xx_phy_start(struct ag71xx *ag);
210 void ag71xx_phy_stop(struct ag71xx *ag);
211
212 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
213 {
214 return ag->pdev->dev.platform_data;
215 }
216
217 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
218 {
219 return (desc->ctrl & DESC_EMPTY) != 0;
220 }
221
222 static inline struct ag71xx_desc *
223 ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
224 {
225 return (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE];
226 }
227
228 static inline int
229 ag71xx_ring_size_order(int size)
230 {
231 return fls(size - 1);
232 }
233
234 /* Register offsets */
235 #define AG71XX_REG_MAC_CFG1 0x0000
236 #define AG71XX_REG_MAC_CFG2 0x0004
237 #define AG71XX_REG_MAC_IPG 0x0008
238 #define AG71XX_REG_MAC_HDX 0x000c
239 #define AG71XX_REG_MAC_MFL 0x0010
240 #define AG71XX_REG_MII_CFG 0x0020
241 #define AG71XX_REG_MII_CMD 0x0024
242 #define AG71XX_REG_MII_ADDR 0x0028
243 #define AG71XX_REG_MII_CTRL 0x002c
244 #define AG71XX_REG_MII_STATUS 0x0030
245 #define AG71XX_REG_MII_IND 0x0034
246 #define AG71XX_REG_MAC_IFCTL 0x0038
247 #define AG71XX_REG_MAC_ADDR1 0x0040
248 #define AG71XX_REG_MAC_ADDR2 0x0044
249 #define AG71XX_REG_FIFO_CFG0 0x0048
250 #define AG71XX_REG_FIFO_CFG1 0x004c
251 #define AG71XX_REG_FIFO_CFG2 0x0050
252 #define AG71XX_REG_FIFO_CFG3 0x0054
253 #define AG71XX_REG_FIFO_CFG4 0x0058
254 #define AG71XX_REG_FIFO_CFG5 0x005c
255 #define AG71XX_REG_FIFO_RAM0 0x0060
256 #define AG71XX_REG_FIFO_RAM1 0x0064
257 #define AG71XX_REG_FIFO_RAM2 0x0068
258 #define AG71XX_REG_FIFO_RAM3 0x006c
259 #define AG71XX_REG_FIFO_RAM4 0x0070
260 #define AG71XX_REG_FIFO_RAM5 0x0074
261 #define AG71XX_REG_FIFO_RAM6 0x0078
262 #define AG71XX_REG_FIFO_RAM7 0x007c
263
264 #define AG71XX_REG_TX_CTRL 0x0180
265 #define AG71XX_REG_TX_DESC 0x0184
266 #define AG71XX_REG_TX_STATUS 0x0188
267 #define AG71XX_REG_RX_CTRL 0x018c
268 #define AG71XX_REG_RX_DESC 0x0190
269 #define AG71XX_REG_RX_STATUS 0x0194
270 #define AG71XX_REG_INT_ENABLE 0x0198
271 #define AG71XX_REG_INT_STATUS 0x019c
272
273 #define AG71XX_REG_FIFO_DEPTH 0x01a8
274 #define AG71XX_REG_RX_SM 0x01b0
275 #define AG71XX_REG_TX_SM 0x01b4
276
277 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
278 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
279 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
280 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
281 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
282 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
283 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
284 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
285
286 #define MAC_CFG2_FDX BIT(0)
287 #define MAC_CFG2_CRC_EN BIT(1)
288 #define MAC_CFG2_PAD_CRC_EN BIT(2)
289 #define MAC_CFG2_LEN_CHECK BIT(4)
290 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
291 #define MAC_CFG2_IF_1000 BIT(9)
292 #define MAC_CFG2_IF_10_100 BIT(8)
293
294 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
295 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
296 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
297 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
298 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
299 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
300 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
301
302 #define FIFO_CFG0_ENABLE_SHIFT 8
303
304 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
305 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
306 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
307 #define FIFO_CFG4_CE BIT(3) /* Code Error */
308 #define FIFO_CFG4_CR BIT(4) /* CRC error */
309 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
310 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
311 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
312 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
313 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
314 #define FIFO_CFG4_DR BIT(10) /* Dribble */
315 #define FIFO_CFG4_LE BIT(11) /* Long Event */
316 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
317 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
318 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
319 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
320 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
321 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
322
323 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
324 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
325 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
326 #define FIFO_CFG5_CE BIT(3) /* Code Error */
327 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
328 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
329 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
330 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
331 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
332 #define FIFO_CFG5_DR BIT(9) /* Dribble */
333 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
334 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
335 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
336 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
337 #define FIFO_CFG5_LE BIT(14) /* Long Event */
338 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
339 #define FIFO_CFG5_16 BIT(16) /* unknown */
340 #define FIFO_CFG5_17 BIT(17) /* unknown */
341 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
342 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
343
344 #define AG71XX_INT_TX_PS BIT(0)
345 #define AG71XX_INT_TX_UR BIT(1)
346 #define AG71XX_INT_TX_BE BIT(3)
347 #define AG71XX_INT_RX_PR BIT(4)
348 #define AG71XX_INT_RX_OF BIT(6)
349 #define AG71XX_INT_RX_BE BIT(7)
350
351 #define MAC_IFCTL_SPEED BIT(16)
352
353 #define MII_CFG_CLK_DIV_4 0
354 #define MII_CFG_CLK_DIV_6 2
355 #define MII_CFG_CLK_DIV_8 3
356 #define MII_CFG_CLK_DIV_10 4
357 #define MII_CFG_CLK_DIV_14 5
358 #define MII_CFG_CLK_DIV_20 6
359 #define MII_CFG_CLK_DIV_28 7
360 #define MII_CFG_CLK_DIV_34 8
361 #define MII_CFG_CLK_DIV_42 9
362 #define MII_CFG_CLK_DIV_50 10
363 #define MII_CFG_CLK_DIV_58 11
364 #define MII_CFG_CLK_DIV_66 12
365 #define MII_CFG_CLK_DIV_74 13
366 #define MII_CFG_CLK_DIV_82 14
367 #define MII_CFG_CLK_DIV_98 15
368 #define MII_CFG_RESET BIT(31)
369
370 #define MII_CMD_WRITE 0x0
371 #define MII_CMD_READ 0x1
372 #define MII_ADDR_SHIFT 8
373 #define MII_IND_BUSY BIT(0)
374 #define MII_IND_INVALID BIT(2)
375
376 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
377
378 #define TX_STATUS_PS BIT(0) /* Packet Sent */
379 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
380 #define TX_STATUS_BE BIT(3) /* Bus Error */
381
382 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
383
384 #define RX_STATUS_PR BIT(0) /* Packet Received */
385 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
386 #define RX_STATUS_BE BIT(3) /* Bus Error */
387
388 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
389 {
390 switch (reg) {
391 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
392 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
393 case AG71XX_REG_MII_CFG:
394 break;
395
396 default:
397 BUG();
398 }
399 }
400
401 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
402 {
403 ag71xx_check_reg_offset(ag, reg);
404
405 __raw_writel(value, ag->mac_base + reg);
406 /* flush write */
407 (void) __raw_readl(ag->mac_base + reg);
408 }
409
410 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
411 {
412 ag71xx_check_reg_offset(ag, reg);
413
414 return __raw_readl(ag->mac_base + reg);
415 }
416
417 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
418 {
419 void __iomem *r;
420
421 ag71xx_check_reg_offset(ag, reg);
422
423 r = ag->mac_base + reg;
424 __raw_writel(__raw_readl(r) | mask, r);
425 /* flush write */
426 (void)__raw_readl(r);
427 }
428
429 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
430 {
431 void __iomem *r;
432
433 ag71xx_check_reg_offset(ag, reg);
434
435 r = ag->mac_base + reg;
436 __raw_writel(__raw_readl(r) & ~mask, r);
437 /* flush write */
438 (void) __raw_readl(r);
439 }
440
441 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
442 {
443 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
444 }
445
446 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
447 {
448 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
449 }
450
451 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
452 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
453 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
454 int pktlen);
455 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
456 {
457 return ag71xx_get_pdata(ag)->has_ar8216;
458 }
459 #else
460 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
461 struct sk_buff *skb)
462 {
463 }
464
465 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
466 struct sk_buff *skb,
467 int pktlen)
468 {
469 return 0;
470 }
471 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
472 {
473 return 0;
474 }
475 #endif
476
477 #ifdef CONFIG_AG71XX_DEBUG_FS
478 int ag71xx_debugfs_root_init(void);
479 void ag71xx_debugfs_root_exit(void);
480 int ag71xx_debugfs_init(struct ag71xx *ag);
481 void ag71xx_debugfs_exit(struct ag71xx *ag);
482 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
483 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
484 #else
485 static inline int ag71xx_debugfs_root_init(void) { return 0; }
486 static inline void ag71xx_debugfs_root_exit(void) {}
487 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
488 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
489 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
490 u32 status) {}
491 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
492 int rx, int tx) {}
493 #endif /* CONFIG_AG71XX_DEBUG_FS */
494
495 void ag71xx_ar7240_start(struct ag71xx *ag);
496 void ag71xx_ar7240_stop(struct ag71xx *ag);
497 int ag71xx_ar7240_init(struct ag71xx *ag);
498 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
499
500 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
501 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
502
503 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
504 unsigned reg_addr);
505 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
506 unsigned reg_addr, u16 reg_val);
507
508 #endif /* _AG71XX_H */