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ar71xx: add missing include for checking kernel version
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
40 #define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
41
42 #define AR7240_REG_VTU 0x0040
43 #define AR7240_VTU_OP BITM(3)
44 #define AR7240_VTU_OP_NOOP 0x0
45 #define AR7240_VTU_OP_FLUSH 0x1
46 #define AR7240_VTU_OP_LOAD 0x2
47 #define AR7240_VTU_OP_PURGE 0x3
48 #define AR7240_VTU_OP_REMOVE_PORT 0x4
49 #define AR7240_VTU_ACTIVE BIT(3)
50 #define AR7240_VTU_FULL BIT(4)
51 #define AR7240_VTU_PORT BITS(8, 4)
52 #define AR7240_VTU_PORT_S 8
53 #define AR7240_VTU_VID BITS(16, 12)
54 #define AR7240_VTU_VID_S 16
55 #define AR7240_VTU_PRIO BITS(28, 3)
56 #define AR7240_VTU_PRIO_S 28
57 #define AR7240_VTU_PRIO_EN BIT(31)
58
59 #define AR7240_REG_VTU_DATA 0x0044
60 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
61 #define AR7240_VTUDATA_VALID BIT(11)
62
63 #define AR7240_REG_ATU 0x50
64 #define AR7240_ATU_FLUSH_ALL 0x1
65
66 #define AR7240_REG_AT_CTRL 0x5c
67 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
68 #define AR7240_AT_CTRL_AGE_EN BIT(17)
69 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
70 #define AR7240_AT_CTRL_RESERVED BIT(19)
71 #define AR7240_AT_CTRL_ARP_EN BIT(20)
72
73 #define AR7240_REG_TAG_PRIORITY 0x70
74
75 #define AR7240_REG_SERVICE_TAG 0x74
76 #define AR7240_SERVICE_TAG_M BITM(16)
77
78 #define AR7240_REG_CPU_PORT 0x78
79 #define AR7240_MIRROR_PORT_S 4
80 #define AR7240_MIRROR_PORT_M BITM(4)
81 #define AR7240_CPU_PORT_EN BIT(8)
82
83 #define AR7240_REG_MIB_FUNCTION0 0x80
84 #define AR7240_MIB_TIMER_M BITM(16)
85 #define AR7240_MIB_AT_HALF_EN BIT(16)
86 #define AR7240_MIB_BUSY BIT(17)
87 #define AR7240_MIB_FUNC_S 24
88 #define AR7240_MIB_FUNC_M BITM(3)
89 #define AR7240_MIB_FUNC_NO_OP 0x0
90 #define AR7240_MIB_FUNC_FLUSH 0x1
91 #define AR7240_MIB_FUNC_CAPTURE 0x3
92
93 #define AR7240_REG_MDIO_CTRL 0x98
94 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
95 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
96 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
97 #define AR7240_MDIO_CTRL_CMD_WRITE 0
98 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
99 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
100 #define AR7240_MDIO_CTRL_BUSY BIT(31)
101
102 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
103
104 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
105 #define AR7240_PORT_STATUS_SPEED_S 0
106 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
107 #define AR7240_PORT_STATUS_SPEED_10 0
108 #define AR7240_PORT_STATUS_SPEED_100 1
109 #define AR7240_PORT_STATUS_SPEED_1000 2
110 #define AR7240_PORT_STATUS_TXMAC BIT(2)
111 #define AR7240_PORT_STATUS_RXMAC BIT(3)
112 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
113 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
114 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
115 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
116 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
117 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
118
119 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
120 #define AR7240_PORT_CTRL_STATE_M BITM(3)
121 #define AR7240_PORT_CTRL_STATE_DISABLED 0
122 #define AR7240_PORT_CTRL_STATE_BLOCK 1
123 #define AR7240_PORT_CTRL_STATE_LISTEN 2
124 #define AR7240_PORT_CTRL_STATE_LEARN 3
125 #define AR7240_PORT_CTRL_STATE_FORWARD 4
126 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
127 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
128 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
129 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
130 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
131 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
132 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
133 #define AR7240_PORT_CTRL_HEADER BIT(11)
134 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
135 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
136 #define AR7240_PORT_CTRL_LEARN BIT(14)
137 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
138 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
139 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
140
141 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
142
143 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
144 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
145 #define AR7240_PORT_VLAN_MODE_S 30
146 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
147 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
148 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
149 #define AR7240_PORT_VLAN_MODE_SECURE 3
150
151
152 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
153
154 #define AR7240_STATS_RXBROAD 0x00
155 #define AR7240_STATS_RXPAUSE 0x04
156 #define AR7240_STATS_RXMULTI 0x08
157 #define AR7240_STATS_RXFCSERR 0x0c
158 #define AR7240_STATS_RXALIGNERR 0x10
159 #define AR7240_STATS_RXRUNT 0x14
160 #define AR7240_STATS_RXFRAGMENT 0x18
161 #define AR7240_STATS_RX64BYTE 0x1c
162 #define AR7240_STATS_RX128BYTE 0x20
163 #define AR7240_STATS_RX256BYTE 0x24
164 #define AR7240_STATS_RX512BYTE 0x28
165 #define AR7240_STATS_RX1024BYTE 0x2c
166 #define AR7240_STATS_RX1518BYTE 0x30
167 #define AR7240_STATS_RXMAXBYTE 0x34
168 #define AR7240_STATS_RXTOOLONG 0x38
169 #define AR7240_STATS_RXGOODBYTE 0x3c
170 #define AR7240_STATS_RXBADBYTE 0x44
171 #define AR7240_STATS_RXOVERFLOW 0x4c
172 #define AR7240_STATS_FILTERED 0x50
173 #define AR7240_STATS_TXBROAD 0x54
174 #define AR7240_STATS_TXPAUSE 0x58
175 #define AR7240_STATS_TXMULTI 0x5c
176 #define AR7240_STATS_TXUNDERRUN 0x60
177 #define AR7240_STATS_TX64BYTE 0x64
178 #define AR7240_STATS_TX128BYTE 0x68
179 #define AR7240_STATS_TX256BYTE 0x6c
180 #define AR7240_STATS_TX512BYTE 0x70
181 #define AR7240_STATS_TX1024BYTE 0x74
182 #define AR7240_STATS_TX1518BYTE 0x78
183 #define AR7240_STATS_TXMAXBYTE 0x7c
184 #define AR7240_STATS_TXOVERSIZE 0x80
185 #define AR7240_STATS_TXBYTE 0x84
186 #define AR7240_STATS_TXCOLLISION 0x8c
187 #define AR7240_STATS_TXABORTCOL 0x90
188 #define AR7240_STATS_TXMULTICOL 0x94
189 #define AR7240_STATS_TXSINGLECOL 0x98
190 #define AR7240_STATS_TXEXCDEFER 0x9c
191 #define AR7240_STATS_TXDEFER 0xa0
192 #define AR7240_STATS_TXLATECOL 0xa4
193
194 #define AR7240_PORT_CPU 0
195 #define AR7240_NUM_PORTS 6
196 #define AR7240_NUM_PHYS 5
197
198 #define AR7240_PHY_ID1 0x004d
199 #define AR7240_PHY_ID2 0xd041
200
201 #define AR934X_PHY_ID1 0x004d
202 #define AR934X_PHY_ID2 0xd042
203
204 #define AR7240_MAX_VLANS 16
205
206 #define AR934X_REG_OPER_MODE0 0x04
207 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
208 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
209
210 #define AR934X_REG_OPER_MODE1 0x08
211 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
212
213 #define AR934X_REG_FLOOD_MASK 0x2c
214 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
215 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
216
217 #define AR934X_REG_QM_CTRL 0x3c
218 #define AR934X_QM_CTRL_ARP_EN BIT(15)
219
220 #define AR934X_REG_AT_CTRL 0x5c
221 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
222 #define AR934X_AT_CTRL_AGE_EN BIT(17)
223 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
224
225 #define AR934X_MIB_ENABLE BIT(30)
226
227 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
228
229 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
230 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
231 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
232 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
233 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
234 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
235 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
236 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
237 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
238
239 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
240 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
241 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
242 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
243 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
244 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
245 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
246
247 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
248
249 struct ar7240sw_port_stat {
250 unsigned long rx_broadcast;
251 unsigned long rx_pause;
252 unsigned long rx_multicast;
253 unsigned long rx_fcs_error;
254 unsigned long rx_align_error;
255 unsigned long rx_runt;
256 unsigned long rx_fragments;
257 unsigned long rx_64byte;
258 unsigned long rx_128byte;
259 unsigned long rx_256byte;
260 unsigned long rx_512byte;
261 unsigned long rx_1024byte;
262 unsigned long rx_1518byte;
263 unsigned long rx_maxbyte;
264 unsigned long rx_toolong;
265 unsigned long rx_good_byte;
266 unsigned long rx_bad_byte;
267 unsigned long rx_overflow;
268 unsigned long filtered;
269
270 unsigned long tx_broadcast;
271 unsigned long tx_pause;
272 unsigned long tx_multicast;
273 unsigned long tx_underrun;
274 unsigned long tx_64byte;
275 unsigned long tx_128byte;
276 unsigned long tx_256byte;
277 unsigned long tx_512byte;
278 unsigned long tx_1024byte;
279 unsigned long tx_1518byte;
280 unsigned long tx_maxbyte;
281 unsigned long tx_oversize;
282 unsigned long tx_byte;
283 unsigned long tx_collision;
284 unsigned long tx_abortcol;
285 unsigned long tx_multicol;
286 unsigned long tx_singlecol;
287 unsigned long tx_excdefer;
288 unsigned long tx_defer;
289 unsigned long tx_xlatecol;
290 };
291
292 struct ar7240sw {
293 struct mii_bus *mii_bus;
294 struct ag71xx_switch_platform_data *swdata;
295 struct switch_dev swdev;
296 int num_ports;
297 u8 ver;
298 bool vlan;
299 u16 vlan_id[AR7240_MAX_VLANS];
300 u8 vlan_table[AR7240_MAX_VLANS];
301 u8 vlan_tagged;
302 u16 pvid[AR7240_NUM_PORTS];
303 char buf[80];
304
305 rwlock_t stats_lock;
306 struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
307 };
308
309 struct ar7240sw_hw_stat {
310 char string[ETH_GSTRING_LEN];
311 int sizeof_stat;
312 int reg;
313 };
314
315 static DEFINE_MUTEX(reg_mutex);
316
317 static inline int sw_is_ar7240(struct ar7240sw *as)
318 {
319 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
320 }
321
322 static inline int sw_is_ar934x(struct ar7240sw *as)
323 {
324 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
325 }
326
327 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
328 {
329 return BIT(port);
330 }
331
332 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
333 {
334 return BIT(as->swdev.ports) - 1;
335 }
336
337 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
338 {
339 return ar7240sw_port_mask_all(as) & ~BIT(port);
340 }
341
342 static inline u16 mk_phy_addr(u32 reg)
343 {
344 return 0x17 & ((reg >> 4) | 0x10);
345 }
346
347 static inline u16 mk_phy_reg(u32 reg)
348 {
349 return (reg << 1) & 0x1e;
350 }
351
352 static inline u16 mk_high_addr(u32 reg)
353 {
354 return (reg >> 7) & 0x1ff;
355 }
356
357 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
358 {
359 unsigned long flags;
360 u16 phy_addr;
361 u16 phy_reg;
362 u32 hi, lo;
363
364 reg = (reg & 0xfffffffc) >> 2;
365 phy_addr = mk_phy_addr(reg);
366 phy_reg = mk_phy_reg(reg);
367
368 local_irq_save(flags);
369 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
370 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
371 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
372 local_irq_restore(flags);
373
374 return (hi << 16) | lo;
375 }
376
377 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
378 {
379 unsigned long flags;
380 u16 phy_addr;
381 u16 phy_reg;
382
383 reg = (reg & 0xfffffffc) >> 2;
384 phy_addr = mk_phy_addr(reg);
385 phy_reg = mk_phy_reg(reg);
386
387 local_irq_save(flags);
388 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
389 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
390 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
391 local_irq_restore(flags);
392 }
393
394 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
395 {
396 u32 ret;
397
398 mutex_lock(&reg_mutex);
399 ret = __ar7240sw_reg_read(mii, reg_addr);
400 mutex_unlock(&reg_mutex);
401
402 return ret;
403 }
404
405 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
406 {
407 mutex_lock(&reg_mutex);
408 __ar7240sw_reg_write(mii, reg_addr, reg_val);
409 mutex_unlock(&reg_mutex);
410 }
411
412 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
413 {
414 u32 t;
415
416 mutex_lock(&reg_mutex);
417 t = __ar7240sw_reg_read(mii, reg);
418 t &= ~mask;
419 t |= val;
420 __ar7240sw_reg_write(mii, reg, t);
421 mutex_unlock(&reg_mutex);
422
423 return t;
424 }
425
426 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
427 {
428 u32 t;
429
430 mutex_lock(&reg_mutex);
431 t = __ar7240sw_reg_read(mii, reg);
432 t |= val;
433 __ar7240sw_reg_write(mii, reg, t);
434 mutex_unlock(&reg_mutex);
435 }
436
437 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
438 unsigned timeout)
439 {
440 int i;
441
442 for (i = 0; i < timeout; i++) {
443 u32 t;
444
445 t = __ar7240sw_reg_read(mii, reg);
446 if ((t & mask) == val)
447 return 0;
448
449 usleep_range(1000, 2000);
450 }
451
452 return -ETIMEDOUT;
453 }
454
455 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
456 unsigned timeout)
457 {
458 int ret;
459
460 mutex_lock(&reg_mutex);
461 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
462 mutex_unlock(&reg_mutex);
463 return ret;
464 }
465
466 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
467 unsigned reg_addr)
468 {
469 u32 t, val = 0xffff;
470 int err;
471
472 if (phy_addr >= AR7240_NUM_PHYS)
473 return 0xffff;
474
475 mutex_lock(&reg_mutex);
476 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
477 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
478 AR7240_MDIO_CTRL_MASTER_EN |
479 AR7240_MDIO_CTRL_BUSY |
480 AR7240_MDIO_CTRL_CMD_READ;
481
482 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
483 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
484 AR7240_MDIO_CTRL_BUSY, 0, 5);
485 if (!err)
486 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
487 mutex_unlock(&reg_mutex);
488
489 return val & AR7240_MDIO_CTRL_DATA_M;
490 }
491
492 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
493 unsigned reg_addr, u16 reg_val)
494 {
495 u32 t;
496 int ret;
497
498 if (phy_addr >= AR7240_NUM_PHYS)
499 return -EINVAL;
500
501 mutex_lock(&reg_mutex);
502 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
503 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
504 AR7240_MDIO_CTRL_MASTER_EN |
505 AR7240_MDIO_CTRL_BUSY |
506 AR7240_MDIO_CTRL_CMD_WRITE |
507 reg_val;
508
509 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
510 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
511 AR7240_MDIO_CTRL_BUSY, 0, 5);
512 mutex_unlock(&reg_mutex);
513
514 return ret;
515 }
516
517 static int ar7240sw_capture_stats(struct ar7240sw *as)
518 {
519 struct mii_bus *mii = as->mii_bus;
520 int port;
521 int ret;
522
523 write_lock(&as->stats_lock);
524
525 /* Capture the hardware statistics for all ports */
526 ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
527 (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
528 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
529
530 /* Wait for the capturing to complete. */
531 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
532 AR7240_MIB_BUSY, 0, 10);
533
534 if (ret)
535 goto unlock;
536
537 for (port = 0; port < AR7240_NUM_PORTS; port++) {
538 unsigned int base;
539 struct ar7240sw_port_stat *stats;
540
541 base = AR7240_REG_STATS_BASE(port);
542 stats = &as->port_stats[port];
543
544 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
545
546 stats->rx_good_byte += READ_STAT(RXGOODBYTE);
547 stats->tx_byte += READ_STAT(TXBYTE);
548
549 #undef READ_STAT
550 }
551
552 ret = 0;
553
554 unlock:
555 write_unlock(&as->stats_lock);
556 return ret;
557 }
558
559 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
560 {
561 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
562 AR7240_PORT_CTRL_STATE_DISABLED);
563 }
564
565 static void ar7240sw_setup(struct ar7240sw *as)
566 {
567 struct mii_bus *mii = as->mii_bus;
568
569 /* Enable CPU port, and disable mirror port */
570 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
571 AR7240_CPU_PORT_EN |
572 (15 << AR7240_MIRROR_PORT_S));
573
574 /* Setup TAG priority mapping */
575 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
576
577 if (sw_is_ar934x(as)) {
578 /* Enable aging, MAC replacing */
579 ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
580 0x2b /* 5 min age time */ |
581 AR934X_AT_CTRL_AGE_EN |
582 AR934X_AT_CTRL_LEARN_CHANGE);
583 /* Enable ARP frame acknowledge */
584 ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
585 AR934X_QM_CTRL_ARP_EN);
586 /* Enable Broadcast/Multicast frames transmitted to the CPU */
587 ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
588 AR934X_FLOOD_MASK_BC_DP(0) |
589 AR934X_FLOOD_MASK_MC_DP(0));
590
591 /* setup MTU */
592 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
593 AR9340_GLOBAL_CTRL_MTU_M,
594 AR9340_GLOBAL_CTRL_MTU_M);
595
596 /* Enable MIB counters */
597 ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
598 AR934X_MIB_ENABLE);
599
600 } else {
601 /* Enable ARP frame acknowledge, aging, MAC replacing */
602 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
603 AR7240_AT_CTRL_RESERVED |
604 0x2b /* 5 min age time */ |
605 AR7240_AT_CTRL_AGE_EN |
606 AR7240_AT_CTRL_ARP_EN |
607 AR7240_AT_CTRL_LEARN_CHANGE);
608 /* Enable Broadcast frames transmitted to the CPU */
609 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
610 AR7240_FLOOD_MASK_BROAD_TO_CPU);
611
612 /* setup MTU */
613 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
614 AR7240_GLOBAL_CTRL_MTU_M,
615 AR7240_GLOBAL_CTRL_MTU_M);
616 }
617
618 /* setup Service TAG */
619 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
620 }
621
622 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
623 static int
624 ar7240sw_phy_poll_reset(struct mii_bus *bus)
625 {
626 const unsigned int sleep_msecs = 20;
627 int ret, elapsed, i;
628
629 for (elapsed = sleep_msecs; elapsed <= 600;
630 elapsed += sleep_msecs) {
631 msleep(sleep_msecs);
632 for (i = 0; i < AR7240_NUM_PHYS; i++) {
633 ret = ar7240sw_phy_read(bus, i, MII_BMCR);
634 if (ret < 0)
635 return ret;
636 if (ret & BMCR_RESET)
637 break;
638 if (i == AR7240_NUM_PHYS - 1) {
639 usleep_range(1000, 2000);
640 return 0;
641 }
642 }
643 }
644 return -ETIMEDOUT;
645 }
646
647 static int ar7240sw_reset(struct ar7240sw *as)
648 {
649 struct mii_bus *mii = as->mii_bus;
650 int ret;
651 int i;
652
653 /* Set all ports to disabled state. */
654 for (i = 0; i < AR7240_NUM_PORTS; i++)
655 ar7240sw_disable_port(as, i);
656
657 /* Wait for transmit queues to drain. */
658 usleep_range(2000, 3000);
659
660 /* Reset the switch. */
661 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
662 AR7240_MASK_CTRL_SOFT_RESET);
663
664 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
665 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
666
667 /* setup PHYs */
668 for (i = 0; i < AR7240_NUM_PHYS; i++) {
669 ar7240sw_phy_write(mii, i, MII_ADVERTISE,
670 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
671 ADVERTISE_PAUSE_ASYM);
672 ar7240sw_phy_write(mii, i, MII_BMCR,
673 BMCR_RESET | BMCR_ANENABLE);
674 }
675 ret = ar7240sw_phy_poll_reset(mii);
676 if (ret)
677 return ret;
678
679 ar7240sw_setup(as);
680 return ret;
681 }
682
683 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
684 {
685 struct mii_bus *mii = as->mii_bus;
686 u32 ctrl;
687 u32 vid, mode;
688
689 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
690 AR7240_PORT_CTRL_SINGLE_VLAN;
691
692 if (port == AR7240_PORT_CPU) {
693 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
694 AR7240_PORT_STATUS_SPEED_1000 |
695 AR7240_PORT_STATUS_TXFLOW |
696 AR7240_PORT_STATUS_RXFLOW |
697 AR7240_PORT_STATUS_TXMAC |
698 AR7240_PORT_STATUS_RXMAC |
699 AR7240_PORT_STATUS_DUPLEX);
700 } else {
701 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
702 AR7240_PORT_STATUS_LINK_AUTO);
703 }
704
705 /* Set the default VID for this port */
706 if (as->vlan) {
707 vid = as->vlan_id[as->pvid[port]];
708 mode = AR7240_PORT_VLAN_MODE_SECURE;
709 } else {
710 vid = port;
711 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
712 }
713
714 if (as->vlan) {
715 if (as->vlan_tagged & BIT(port))
716 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
717 AR7240_PORT_CTRL_VLAN_MODE_S;
718 else
719 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
720 AR7240_PORT_CTRL_VLAN_MODE_S;
721 } else {
722 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
723 AR7240_PORT_CTRL_VLAN_MODE_S;
724 }
725
726 if (!portmask) {
727 if (port == AR7240_PORT_CPU)
728 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
729 else
730 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
731 }
732
733 /* allow the port to talk to all other ports, but exclude its
734 * own ID to prevent frames from being reflected back to the
735 * port that they came from */
736 portmask &= ar7240sw_port_mask_but(as, port);
737
738 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
739 if (sw_is_ar934x(as)) {
740 u32 vlan1, vlan2;
741
742 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
743 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
744 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
745 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
746 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
747 } else {
748 u32 vlan;
749
750 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
751 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
752
753 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
754 }
755 }
756
757 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
758 {
759 struct mii_bus *mii = as->mii_bus;
760 u32 t;
761
762 t = (addr[4] << 8) | addr[5];
763 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
764
765 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
766 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
767
768 return 0;
769 }
770
771 static int
772 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
773 struct switch_val *val)
774 {
775 struct ar7240sw *as = sw_to_ar7240(dev);
776 as->vlan_id[val->port_vlan] = val->value.i;
777 return 0;
778 }
779
780 static int
781 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
782 struct switch_val *val)
783 {
784 struct ar7240sw *as = sw_to_ar7240(dev);
785 val->value.i = as->vlan_id[val->port_vlan];
786 return 0;
787 }
788
789 static int
790 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
791 {
792 struct ar7240sw *as = sw_to_ar7240(dev);
793
794 /* make sure no invalid PVIDs get set */
795
796 if (vlan >= dev->vlans)
797 return -EINVAL;
798
799 as->pvid[port] = vlan;
800 return 0;
801 }
802
803 static int
804 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
805 {
806 struct ar7240sw *as = sw_to_ar7240(dev);
807 *vlan = as->pvid[port];
808 return 0;
809 }
810
811 static int
812 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
813 {
814 struct ar7240sw *as = sw_to_ar7240(dev);
815 u8 ports = as->vlan_table[val->port_vlan];
816 int i;
817
818 val->len = 0;
819 for (i = 0; i < as->swdev.ports; i++) {
820 struct switch_port *p;
821
822 if (!(ports & (1 << i)))
823 continue;
824
825 p = &val->value.ports[val->len++];
826 p->id = i;
827 if (as->vlan_tagged & (1 << i))
828 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
829 else
830 p->flags = 0;
831 }
832 return 0;
833 }
834
835 static int
836 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
837 {
838 struct ar7240sw *as = sw_to_ar7240(dev);
839 u8 *vt = &as->vlan_table[val->port_vlan];
840 int i, j;
841
842 *vt = 0;
843 for (i = 0; i < val->len; i++) {
844 struct switch_port *p = &val->value.ports[i];
845
846 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
847 as->vlan_tagged |= (1 << p->id);
848 else {
849 as->vlan_tagged &= ~(1 << p->id);
850 as->pvid[p->id] = val->port_vlan;
851
852 /* make sure that an untagged port does not
853 * appear in other vlans */
854 for (j = 0; j < AR7240_MAX_VLANS; j++) {
855 if (j == val->port_vlan)
856 continue;
857 as->vlan_table[j] &= ~(1 << p->id);
858 }
859 }
860
861 *vt |= 1 << p->id;
862 }
863 return 0;
864 }
865
866 static int
867 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
868 struct switch_val *val)
869 {
870 struct ar7240sw *as = sw_to_ar7240(dev);
871 as->vlan = !!val->value.i;
872 return 0;
873 }
874
875 static int
876 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
877 struct switch_val *val)
878 {
879 struct ar7240sw *as = sw_to_ar7240(dev);
880 val->value.i = as->vlan;
881 return 0;
882 }
883
884 static void
885 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
886 {
887 struct mii_bus *mii = as->mii_bus;
888
889 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
890 return;
891
892 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
893 val &= AR7240_VTUDATA_MEMBER;
894 val |= AR7240_VTUDATA_VALID;
895 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
896 }
897 op |= AR7240_VTU_ACTIVE;
898 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
899 }
900
901 static int
902 ar7240_hw_apply(struct switch_dev *dev)
903 {
904 struct ar7240sw *as = sw_to_ar7240(dev);
905 u8 portmask[AR7240_NUM_PORTS];
906 int i, j;
907
908 /* flush all vlan translation unit entries */
909 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
910
911 memset(portmask, 0, sizeof(portmask));
912 if (as->vlan) {
913 /* calculate the port destination masks and load vlans
914 * into the vlan translation unit */
915 for (j = 0; j < AR7240_MAX_VLANS; j++) {
916 u8 vp = as->vlan_table[j];
917
918 if (!vp)
919 continue;
920
921 for (i = 0; i < as->swdev.ports; i++) {
922 u8 mask = (1 << i);
923 if (vp & mask)
924 portmask[i] |= vp & ~mask;
925 }
926
927 ar7240_vtu_op(as,
928 AR7240_VTU_OP_LOAD |
929 (as->vlan_id[j] << AR7240_VTU_VID_S),
930 as->vlan_table[j]);
931 }
932 } else {
933 /* vlan disabled:
934 * isolate all ports, but connect them to the cpu port */
935 for (i = 0; i < as->swdev.ports; i++) {
936 if (i == AR7240_PORT_CPU)
937 continue;
938
939 portmask[i] = 1 << AR7240_PORT_CPU;
940 portmask[AR7240_PORT_CPU] |= (1 << i);
941 }
942 }
943
944 /* update the port destination mask registers and tag settings */
945 for (i = 0; i < as->swdev.ports; i++)
946 ar7240sw_setup_port(as, i, portmask[i]);
947
948 return 0;
949 }
950
951 static int
952 ar7240_reset_switch(struct switch_dev *dev)
953 {
954 struct ar7240sw *as = sw_to_ar7240(dev);
955 ar7240sw_reset(as);
956 return 0;
957 }
958
959 static int
960 ar7240_get_port_link(struct switch_dev *dev, int port,
961 struct switch_port_link *link)
962 {
963 struct ar7240sw *as = sw_to_ar7240(dev);
964 struct mii_bus *mii = as->mii_bus;
965 u32 status;
966
967 if (port >= AR7240_NUM_PORTS)
968 return -EINVAL;
969
970 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
971 link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
972 if (link->aneg) {
973 link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
974 if (!link->link)
975 return 0;
976 } else {
977 link->link = true;
978 }
979
980 link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
981 link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
982 link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
983 switch (status & AR7240_PORT_STATUS_SPEED_M) {
984 case AR7240_PORT_STATUS_SPEED_10:
985 link->speed = SWITCH_PORT_SPEED_10;
986 break;
987 case AR7240_PORT_STATUS_SPEED_100:
988 link->speed = SWITCH_PORT_SPEED_100;
989 break;
990 case AR7240_PORT_STATUS_SPEED_1000:
991 link->speed = SWITCH_PORT_SPEED_1000;
992 break;
993 }
994
995 return 0;
996 }
997
998 static int
999 ar7240_get_port_stats(struct switch_dev *dev, int port,
1000 struct switch_port_stats *stats)
1001 {
1002 struct ar7240sw *as = sw_to_ar7240(dev);
1003
1004 if (port >= AR7240_NUM_PORTS)
1005 return -EINVAL;
1006
1007 ar7240sw_capture_stats(as);
1008
1009 read_lock(&as->stats_lock);
1010 stats->rx_bytes = as->port_stats[port].rx_good_byte;
1011 stats->tx_bytes = as->port_stats[port].tx_byte;
1012 read_unlock(&as->stats_lock);
1013
1014 return 0;
1015 }
1016
1017 static int
1018 ar7240_set_mirror_monitor_port(struct switch_dev *dev,
1019 const struct switch_attr *attr,
1020 struct switch_val *val)
1021 {
1022 struct ar7240sw *as = sw_to_ar7240(dev);
1023 struct mii_bus *mii = as->mii_bus;
1024
1025 int port = val->value.i;
1026
1027 if (port > 15)
1028 return -EINVAL;
1029
1030 ar7240sw_reg_rmw(mii, AR7240_REG_CPU_PORT,
1031 AR7240_MIRROR_PORT_M << AR7240_MIRROR_PORT_S,
1032 port << AR7240_MIRROR_PORT_S);
1033
1034 return 0;
1035 }
1036
1037 static int
1038 ar7240_get_mirror_monitor_port(struct switch_dev *dev,
1039 const struct switch_attr *attr,
1040 struct switch_val *val)
1041 {
1042 struct ar7240sw *as = sw_to_ar7240(dev);
1043 struct mii_bus *mii = as->mii_bus;
1044
1045 u32 ret;
1046
1047 ret = ar7240sw_reg_read(mii, AR7240_REG_CPU_PORT);
1048 val->value.i = (ret >> AR7240_MIRROR_PORT_S) & AR7240_MIRROR_PORT_M;
1049
1050 return 0;
1051 }
1052
1053 static int
1054 ar7240_set_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1055 struct switch_val *val)
1056 {
1057 struct ar7240sw *as = sw_to_ar7240(dev);
1058 struct mii_bus *mii = as->mii_bus;
1059
1060 int port = val->port_vlan;
1061
1062 if (port >= dev->ports)
1063 return -EINVAL;
1064
1065 if (val && val->value.i == 1)
1066 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1067 AR7240_PORT_CTRL_MIRROR_RX);
1068 else
1069 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1070 AR7240_PORT_CTRL_MIRROR_RX, 0);
1071
1072 return 0;
1073 }
1074
1075 static int
1076 ar7240_get_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1077 struct switch_val *val)
1078 {
1079 struct ar7240sw *as = sw_to_ar7240(dev);
1080 struct mii_bus *mii = as->mii_bus;
1081
1082 u32 ctrl;
1083
1084 int port = val->port_vlan;
1085
1086 if (port >= dev->ports)
1087 return -EINVAL;
1088
1089 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1090
1091 if ((ctrl & AR7240_PORT_CTRL_MIRROR_RX) == AR7240_PORT_CTRL_MIRROR_RX)
1092 val->value.i = 1;
1093 else
1094 val->value.i = 0;
1095
1096 return 0;
1097 }
1098
1099 static int
1100 ar7240_set_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1101 struct switch_val *val)
1102 {
1103 struct ar7240sw *as = sw_to_ar7240(dev);
1104 struct mii_bus *mii = as->mii_bus;
1105
1106 int port = val->port_vlan;
1107
1108 if (port >= dev->ports)
1109 return -EINVAL;
1110
1111 if (val && val->value.i == 1)
1112 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1113 AR7240_PORT_CTRL_MIRROR_TX);
1114 else
1115 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1116 AR7240_PORT_CTRL_MIRROR_TX, 0);
1117
1118 return 0;
1119 }
1120
1121 static int
1122 ar7240_get_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1123 struct switch_val *val)
1124 {
1125 struct ar7240sw *as = sw_to_ar7240(dev);
1126 struct mii_bus *mii = as->mii_bus;
1127
1128 u32 ctrl;
1129
1130 int port = val->port_vlan;
1131
1132 if (port >= dev->ports)
1133 return -EINVAL;
1134
1135 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1136
1137 if ((ctrl & AR7240_PORT_CTRL_MIRROR_TX) == AR7240_PORT_CTRL_MIRROR_TX)
1138 val->value.i = 1;
1139 else
1140 val->value.i = 0;
1141
1142 return 0;
1143 }
1144
1145 static struct switch_attr ar7240_globals[] = {
1146 {
1147 .type = SWITCH_TYPE_INT,
1148 .name = "enable_vlan",
1149 .description = "Enable VLAN mode",
1150 .set = ar7240_set_vlan,
1151 .get = ar7240_get_vlan,
1152 .max = 1
1153 },
1154 {
1155 .type = SWITCH_TYPE_INT,
1156 .name = "mirror_monitor_port",
1157 .description = "Mirror monitor port",
1158 .set = ar7240_set_mirror_monitor_port,
1159 .get = ar7240_get_mirror_monitor_port,
1160 .max = 15
1161 },
1162 };
1163
1164 static struct switch_attr ar7240_port[] = {
1165 {
1166 .type = SWITCH_TYPE_INT,
1167 .name = "enable_mirror_rx",
1168 .description = "Enable mirroring of RX packets",
1169 .set = ar7240_set_mirror_rx,
1170 .get = ar7240_get_mirror_rx,
1171 .max = 1
1172 },
1173 {
1174 .type = SWITCH_TYPE_INT,
1175 .name = "enable_mirror_tx",
1176 .description = "Enable mirroring of TX packets",
1177 .set = ar7240_set_mirror_tx,
1178 .get = ar7240_get_mirror_tx,
1179 .max = 1
1180 },
1181 };
1182
1183 static struct switch_attr ar7240_vlan[] = {
1184 {
1185 .type = SWITCH_TYPE_INT,
1186 .name = "vid",
1187 .description = "VLAN ID",
1188 .set = ar7240_set_vid,
1189 .get = ar7240_get_vid,
1190 .max = 4094,
1191 },
1192 };
1193
1194 static const struct switch_dev_ops ar7240_ops = {
1195 .attr_global = {
1196 .attr = ar7240_globals,
1197 .n_attr = ARRAY_SIZE(ar7240_globals),
1198 },
1199 .attr_port = {
1200 .attr = ar7240_port,
1201 .n_attr = ARRAY_SIZE(ar7240_port),
1202 },
1203 .attr_vlan = {
1204 .attr = ar7240_vlan,
1205 .n_attr = ARRAY_SIZE(ar7240_vlan),
1206 },
1207 .get_port_pvid = ar7240_get_pvid,
1208 .set_port_pvid = ar7240_set_pvid,
1209 .get_vlan_ports = ar7240_get_ports,
1210 .set_vlan_ports = ar7240_set_ports,
1211 .apply_config = ar7240_hw_apply,
1212 .reset_switch = ar7240_reset_switch,
1213 .get_port_link = ar7240_get_port_link,
1214 .get_port_stats = ar7240_get_port_stats,
1215 };
1216
1217 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
1218 {
1219 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1220 struct mii_bus *mii = ag->mii_bus;
1221 struct ar7240sw *as;
1222 struct switch_dev *swdev;
1223 u32 ctrl;
1224 u16 phy_id1;
1225 u16 phy_id2;
1226 int i;
1227
1228 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
1229 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
1230 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
1231 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
1232 pr_err("%s: unknown phy id '%04x:%04x'\n",
1233 dev_name(&mii->dev), phy_id1, phy_id2);
1234 return NULL;
1235 }
1236
1237 as = kzalloc(sizeof(*as), GFP_KERNEL);
1238 if (!as)
1239 return NULL;
1240
1241 as->mii_bus = mii;
1242 as->swdata = pdata->switch_data;
1243
1244 swdev = &as->swdev;
1245
1246 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1247 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1248 AR7240_MASK_CTRL_VERSION_M;
1249
1250 if (sw_is_ar7240(as)) {
1251 swdev->name = "AR7240/AR9330 built-in switch";
1252 swdev->ports = AR7240_NUM_PORTS - 1;
1253 } else if (sw_is_ar934x(as)) {
1254 swdev->name = "AR934X built-in switch";
1255
1256 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1257 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1258 AR934X_OPER_MODE0_MAC_GMII_EN);
1259 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
1260 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1261 AR934X_OPER_MODE0_PHY_MII_EN);
1262 } else {
1263 pr_err("%s: invalid PHY interface mode\n",
1264 dev_name(&mii->dev));
1265 goto err_free;
1266 }
1267
1268 if (as->swdata->phy4_mii_en) {
1269 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1270 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1271 swdev->ports = AR7240_NUM_PORTS - 1;
1272 } else {
1273 swdev->ports = AR7240_NUM_PORTS;
1274 }
1275 } else {
1276 pr_err("%s: unsupported chip, ctrl=%08x\n",
1277 dev_name(&mii->dev), ctrl);
1278 goto err_free;
1279 }
1280
1281 swdev->cpu_port = AR7240_PORT_CPU;
1282 swdev->vlans = AR7240_MAX_VLANS;
1283 swdev->ops = &ar7240_ops;
1284
1285 if (register_switch(&as->swdev, ag->dev) < 0)
1286 goto err_free;
1287
1288 pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name);
1289
1290 /* initialize defaults */
1291 for (i = 0; i < AR7240_MAX_VLANS; i++)
1292 as->vlan_id[i] = i;
1293
1294 as->vlan_table[0] = ar7240sw_port_mask_all(as);
1295
1296 return as;
1297
1298 err_free:
1299 kfree(as);
1300 return NULL;
1301 }
1302
1303 static void link_function(struct work_struct *work) {
1304 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
1305 struct ar7240sw *as = ag->phy_priv;
1306 unsigned long flags;
1307 u8 mask;
1308 int i;
1309 int status = 0;
1310
1311 mask = ~as->swdata->phy_poll_mask;
1312 for (i = 0; i < AR7240_NUM_PHYS; i++) {
1313 int link;
1314
1315 if (!(mask & BIT(i)))
1316 continue;
1317
1318 link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
1319 if (link & BMSR_LSTATUS) {
1320 status = 1;
1321 break;
1322 }
1323 }
1324
1325 spin_lock_irqsave(&ag->lock, flags);
1326 if (status != ag->link) {
1327 ag->link = status;
1328 ag71xx_link_adjust(ag);
1329 }
1330 spin_unlock_irqrestore(&ag->lock, flags);
1331
1332 schedule_delayed_work(&ag->link_work, HZ / 2);
1333 }
1334
1335 void ag71xx_ar7240_start(struct ag71xx *ag)
1336 {
1337 struct ar7240sw *as = ag->phy_priv;
1338
1339 ar7240sw_reset(as);
1340
1341 ag->speed = SPEED_1000;
1342 ag->duplex = 1;
1343
1344 ar7240_set_addr(as, ag->dev->dev_addr);
1345 ar7240_hw_apply(&as->swdev);
1346
1347 schedule_delayed_work(&ag->link_work, HZ / 10);
1348 }
1349
1350 void ag71xx_ar7240_stop(struct ag71xx *ag)
1351 {
1352 cancel_delayed_work_sync(&ag->link_work);
1353 }
1354
1355 int ag71xx_ar7240_init(struct ag71xx *ag)
1356 {
1357 struct ar7240sw *as;
1358
1359 as = ar7240_probe(ag);
1360 if (!as)
1361 return -ENODEV;
1362
1363 ag->phy_priv = as;
1364 ar7240sw_reset(as);
1365
1366 rwlock_init(&as->stats_lock);
1367 INIT_DELAYED_WORK(&ag->link_work, link_function);
1368
1369 return 0;
1370 }
1371
1372 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1373 {
1374 struct ar7240sw *as = ag->phy_priv;
1375
1376 if (!as)
1377 return;
1378
1379 unregister_switch(&as->swdev);
1380 kfree(as);
1381 ag->phy_priv = NULL;
1382 }
OpenWrt Source Repository