ar71xx: rename ethernet pdata->builtin_switch to use_flow_control
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
40 #define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
41
42 #define AR7240_REG_VTU 0x0040
43 #define AR7240_VTU_OP BITM(3)
44 #define AR7240_VTU_OP_NOOP 0x0
45 #define AR7240_VTU_OP_FLUSH 0x1
46 #define AR7240_VTU_OP_LOAD 0x2
47 #define AR7240_VTU_OP_PURGE 0x3
48 #define AR7240_VTU_OP_REMOVE_PORT 0x4
49 #define AR7240_VTU_ACTIVE BIT(3)
50 #define AR7240_VTU_FULL BIT(4)
51 #define AR7240_VTU_PORT BITS(8, 4)
52 #define AR7240_VTU_PORT_S 8
53 #define AR7240_VTU_VID BITS(16, 12)
54 #define AR7240_VTU_VID_S 16
55 #define AR7240_VTU_PRIO BITS(28, 3)
56 #define AR7240_VTU_PRIO_S 28
57 #define AR7240_VTU_PRIO_EN BIT(31)
58
59 #define AR7240_REG_VTU_DATA 0x0044
60 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
61 #define AR7240_VTUDATA_VALID BIT(11)
62
63 #define AR7240_REG_ATU 0x50
64 #define AR7240_ATU_FLUSH_ALL 0x1
65
66 #define AR7240_REG_AT_CTRL 0x5c
67 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
68 #define AR7240_AT_CTRL_AGE_EN BIT(17)
69 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
70 #define AR7240_AT_CTRL_RESERVED BIT(19)
71 #define AR7240_AT_CTRL_ARP_EN BIT(20)
72
73 #define AR7240_REG_TAG_PRIORITY 0x70
74
75 #define AR7240_REG_SERVICE_TAG 0x74
76 #define AR7240_SERVICE_TAG_M BITM(16)
77
78 #define AR7240_REG_CPU_PORT 0x78
79 #define AR7240_MIRROR_PORT_S 4
80 #define AR7240_CPU_PORT_EN BIT(8)
81
82 #define AR7240_REG_MIB_FUNCTION0 0x80
83 #define AR7240_MIB_TIMER_M BITM(16)
84 #define AR7240_MIB_AT_HALF_EN BIT(16)
85 #define AR7240_MIB_BUSY BIT(17)
86 #define AR7240_MIB_FUNC_S 24
87 #define AR7240_MIB_FUNC_M BITM(3)
88 #define AR7240_MIB_FUNC_NO_OP 0x0
89 #define AR7240_MIB_FUNC_FLUSH 0x1
90 #define AR7240_MIB_FUNC_CAPTURE 0x3
91
92 #define AR7240_REG_MDIO_CTRL 0x98
93 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
94 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
95 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
96 #define AR7240_MDIO_CTRL_CMD_WRITE 0
97 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
98 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
99 #define AR7240_MDIO_CTRL_BUSY BIT(31)
100
101 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
102
103 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
104 #define AR7240_PORT_STATUS_SPEED_S 0
105 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
106 #define AR7240_PORT_STATUS_SPEED_10 0
107 #define AR7240_PORT_STATUS_SPEED_100 1
108 #define AR7240_PORT_STATUS_SPEED_1000 2
109 #define AR7240_PORT_STATUS_TXMAC BIT(2)
110 #define AR7240_PORT_STATUS_RXMAC BIT(3)
111 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
112 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
113 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
114 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
115 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
116 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
117
118 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
119 #define AR7240_PORT_CTRL_STATE_M BITM(3)
120 #define AR7240_PORT_CTRL_STATE_DISABLED 0
121 #define AR7240_PORT_CTRL_STATE_BLOCK 1
122 #define AR7240_PORT_CTRL_STATE_LISTEN 2
123 #define AR7240_PORT_CTRL_STATE_LEARN 3
124 #define AR7240_PORT_CTRL_STATE_FORWARD 4
125 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
126 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
127 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
128 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
129 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
130 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
131 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
132 #define AR7240_PORT_CTRL_HEADER BIT(11)
133 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
134 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
135 #define AR7240_PORT_CTRL_LEARN BIT(14)
136 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
137 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
138 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
139
140 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
141
142 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
143 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
144 #define AR7240_PORT_VLAN_MODE_S 30
145 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
146 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
147 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
148 #define AR7240_PORT_VLAN_MODE_SECURE 3
149
150
151 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
152
153 #define AR7240_STATS_RXBROAD 0x00
154 #define AR7240_STATS_RXPAUSE 0x04
155 #define AR7240_STATS_RXMULTI 0x08
156 #define AR7240_STATS_RXFCSERR 0x0c
157 #define AR7240_STATS_RXALIGNERR 0x10
158 #define AR7240_STATS_RXRUNT 0x14
159 #define AR7240_STATS_RXFRAGMENT 0x18
160 #define AR7240_STATS_RX64BYTE 0x1c
161 #define AR7240_STATS_RX128BYTE 0x20
162 #define AR7240_STATS_RX256BYTE 0x24
163 #define AR7240_STATS_RX512BYTE 0x28
164 #define AR7240_STATS_RX1024BYTE 0x2c
165 #define AR7240_STATS_RX1518BYTE 0x30
166 #define AR7240_STATS_RXMAXBYTE 0x34
167 #define AR7240_STATS_RXTOOLONG 0x38
168 #define AR7240_STATS_RXGOODBYTE 0x3c
169 #define AR7240_STATS_RXBADBYTE 0x44
170 #define AR7240_STATS_RXOVERFLOW 0x4c
171 #define AR7240_STATS_FILTERED 0x50
172 #define AR7240_STATS_TXBROAD 0x54
173 #define AR7240_STATS_TXPAUSE 0x58
174 #define AR7240_STATS_TXMULTI 0x5c
175 #define AR7240_STATS_TXUNDERRUN 0x60
176 #define AR7240_STATS_TX64BYTE 0x64
177 #define AR7240_STATS_TX128BYTE 0x68
178 #define AR7240_STATS_TX256BYTE 0x6c
179 #define AR7240_STATS_TX512BYTE 0x70
180 #define AR7240_STATS_TX1024BYTE 0x74
181 #define AR7240_STATS_TX1518BYTE 0x78
182 #define AR7240_STATS_TXMAXBYTE 0x7c
183 #define AR7240_STATS_TXOVERSIZE 0x80
184 #define AR7240_STATS_TXBYTE 0x84
185 #define AR7240_STATS_TXCOLLISION 0x8c
186 #define AR7240_STATS_TXABORTCOL 0x90
187 #define AR7240_STATS_TXMULTICOL 0x94
188 #define AR7240_STATS_TXSINGLECOL 0x98
189 #define AR7240_STATS_TXEXCDEFER 0x9c
190 #define AR7240_STATS_TXDEFER 0xa0
191 #define AR7240_STATS_TXLATECOL 0xa4
192
193 #define AR7240_PORT_CPU 0
194 #define AR7240_NUM_PORTS 6
195 #define AR7240_NUM_PHYS 5
196
197 #define AR7240_PHY_ID1 0x004d
198 #define AR7240_PHY_ID2 0xd041
199
200 #define AR934X_PHY_ID1 0x004d
201 #define AR934X_PHY_ID2 0xd042
202
203 #define AR7240_MAX_VLANS 16
204
205 #define AR934X_REG_OPER_MODE0 0x04
206 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
207 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
208
209 #define AR934X_REG_OPER_MODE1 0x08
210 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
211
212 #define AR934X_REG_FLOOD_MASK 0x2c
213 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
214 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
215
216 #define AR934X_REG_QM_CTRL 0x3c
217 #define AR934X_QM_CTRL_ARP_EN BIT(15)
218
219 #define AR934X_REG_AT_CTRL 0x5c
220 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
221 #define AR934X_AT_CTRL_AGE_EN BIT(17)
222 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
223
224 #define AR934X_MIB_ENABLE BIT(30)
225
226 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
227
228 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
229 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
230 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
231 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
232 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
233 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
234 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
235 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
236 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
237
238 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
239 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
240 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
241 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
242 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
243 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
244 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
245
246 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
247
248 struct ar7240sw_port_stat {
249 unsigned long rx_broadcast;
250 unsigned long rx_pause;
251 unsigned long rx_multicast;
252 unsigned long rx_fcs_error;
253 unsigned long rx_align_error;
254 unsigned long rx_runt;
255 unsigned long rx_fragments;
256 unsigned long rx_64byte;
257 unsigned long rx_128byte;
258 unsigned long rx_256byte;
259 unsigned long rx_512byte;
260 unsigned long rx_1024byte;
261 unsigned long rx_1518byte;
262 unsigned long rx_maxbyte;
263 unsigned long rx_toolong;
264 unsigned long rx_good_byte;
265 unsigned long rx_bad_byte;
266 unsigned long rx_overflow;
267 unsigned long filtered;
268
269 unsigned long tx_broadcast;
270 unsigned long tx_pause;
271 unsigned long tx_multicast;
272 unsigned long tx_underrun;
273 unsigned long tx_64byte;
274 unsigned long tx_128byte;
275 unsigned long tx_256byte;
276 unsigned long tx_512byte;
277 unsigned long tx_1024byte;
278 unsigned long tx_1518byte;
279 unsigned long tx_maxbyte;
280 unsigned long tx_oversize;
281 unsigned long tx_byte;
282 unsigned long tx_collision;
283 unsigned long tx_abortcol;
284 unsigned long tx_multicol;
285 unsigned long tx_singlecol;
286 unsigned long tx_excdefer;
287 unsigned long tx_defer;
288 unsigned long tx_xlatecol;
289 };
290
291 struct ar7240sw {
292 struct mii_bus *mii_bus;
293 struct ag71xx_switch_platform_data *swdata;
294 struct switch_dev swdev;
295 int num_ports;
296 u8 ver;
297 bool vlan;
298 u16 vlan_id[AR7240_MAX_VLANS];
299 u8 vlan_table[AR7240_MAX_VLANS];
300 u8 vlan_tagged;
301 u16 pvid[AR7240_NUM_PORTS];
302 char buf[80];
303
304 rwlock_t stats_lock;
305 struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
306 };
307
308 struct ar7240sw_hw_stat {
309 char string[ETH_GSTRING_LEN];
310 int sizeof_stat;
311 int reg;
312 };
313
314 static DEFINE_MUTEX(reg_mutex);
315
316 static inline int sw_is_ar7240(struct ar7240sw *as)
317 {
318 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
319 }
320
321 static inline int sw_is_ar934x(struct ar7240sw *as)
322 {
323 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
324 }
325
326 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
327 {
328 return BIT(port);
329 }
330
331 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
332 {
333 return BIT(as->swdev.ports) - 1;
334 }
335
336 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
337 {
338 return ar7240sw_port_mask_all(as) & ~BIT(port);
339 }
340
341 static inline u16 mk_phy_addr(u32 reg)
342 {
343 return 0x17 & ((reg >> 4) | 0x10);
344 }
345
346 static inline u16 mk_phy_reg(u32 reg)
347 {
348 return (reg << 1) & 0x1e;
349 }
350
351 static inline u16 mk_high_addr(u32 reg)
352 {
353 return (reg >> 7) & 0x1ff;
354 }
355
356 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
357 {
358 unsigned long flags;
359 u16 phy_addr;
360 u16 phy_reg;
361 u32 hi, lo;
362
363 reg = (reg & 0xfffffffc) >> 2;
364 phy_addr = mk_phy_addr(reg);
365 phy_reg = mk_phy_reg(reg);
366
367 local_irq_save(flags);
368 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
369 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
370 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
371 local_irq_restore(flags);
372
373 return (hi << 16) | lo;
374 }
375
376 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
377 {
378 unsigned long flags;
379 u16 phy_addr;
380 u16 phy_reg;
381
382 reg = (reg & 0xfffffffc) >> 2;
383 phy_addr = mk_phy_addr(reg);
384 phy_reg = mk_phy_reg(reg);
385
386 local_irq_save(flags);
387 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
388 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
389 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
390 local_irq_restore(flags);
391 }
392
393 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
394 {
395 u32 ret;
396
397 mutex_lock(&reg_mutex);
398 ret = __ar7240sw_reg_read(mii, reg_addr);
399 mutex_unlock(&reg_mutex);
400
401 return ret;
402 }
403
404 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
405 {
406 mutex_lock(&reg_mutex);
407 __ar7240sw_reg_write(mii, reg_addr, reg_val);
408 mutex_unlock(&reg_mutex);
409 }
410
411 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
412 {
413 u32 t;
414
415 mutex_lock(&reg_mutex);
416 t = __ar7240sw_reg_read(mii, reg);
417 t &= ~mask;
418 t |= val;
419 __ar7240sw_reg_write(mii, reg, t);
420 mutex_unlock(&reg_mutex);
421
422 return t;
423 }
424
425 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
426 {
427 u32 t;
428
429 mutex_lock(&reg_mutex);
430 t = __ar7240sw_reg_read(mii, reg);
431 t |= val;
432 __ar7240sw_reg_write(mii, reg, t);
433 mutex_unlock(&reg_mutex);
434 }
435
436 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
437 unsigned timeout)
438 {
439 int i;
440
441 for (i = 0; i < timeout; i++) {
442 u32 t;
443
444 t = __ar7240sw_reg_read(mii, reg);
445 if ((t & mask) == val)
446 return 0;
447
448 usleep_range(1000, 2000);
449 }
450
451 return -ETIMEDOUT;
452 }
453
454 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
455 unsigned timeout)
456 {
457 int ret;
458
459 mutex_lock(&reg_mutex);
460 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
461 mutex_unlock(&reg_mutex);
462 return ret;
463 }
464
465 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
466 unsigned reg_addr)
467 {
468 u32 t, val = 0xffff;
469 int err;
470
471 if (phy_addr >= AR7240_NUM_PHYS)
472 return 0xffff;
473
474 mutex_lock(&reg_mutex);
475 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
476 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
477 AR7240_MDIO_CTRL_MASTER_EN |
478 AR7240_MDIO_CTRL_BUSY |
479 AR7240_MDIO_CTRL_CMD_READ;
480
481 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
482 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
483 AR7240_MDIO_CTRL_BUSY, 0, 5);
484 if (!err)
485 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
486 mutex_unlock(&reg_mutex);
487
488 return val & AR7240_MDIO_CTRL_DATA_M;
489 }
490
491 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
492 unsigned reg_addr, u16 reg_val)
493 {
494 u32 t;
495 int ret;
496
497 if (phy_addr >= AR7240_NUM_PHYS)
498 return -EINVAL;
499
500 mutex_lock(&reg_mutex);
501 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
502 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
503 AR7240_MDIO_CTRL_MASTER_EN |
504 AR7240_MDIO_CTRL_BUSY |
505 AR7240_MDIO_CTRL_CMD_WRITE |
506 reg_val;
507
508 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
509 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
510 AR7240_MDIO_CTRL_BUSY, 0, 5);
511 mutex_unlock(&reg_mutex);
512
513 return ret;
514 }
515
516 static int ar7240sw_capture_stats(struct ar7240sw *as)
517 {
518 struct mii_bus *mii = as->mii_bus;
519 int port;
520 int ret;
521
522 write_lock(&as->stats_lock);
523
524 /* Capture the hardware statistics for all ports */
525 ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
526 (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
527 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
528
529 /* Wait for the capturing to complete. */
530 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
531 AR7240_MIB_BUSY, 0, 10);
532
533 if (ret)
534 goto unlock;
535
536 for (port = 0; port < AR7240_NUM_PORTS; port++) {
537 unsigned int base;
538 struct ar7240sw_port_stat *stats;
539
540 base = AR7240_REG_STATS_BASE(port);
541 stats = &as->port_stats[port];
542
543 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
544
545 stats->rx_good_byte += READ_STAT(RXGOODBYTE);
546 stats->tx_byte += READ_STAT(TXBYTE);
547
548 #undef READ_STAT
549 }
550
551 ret = 0;
552
553 unlock:
554 write_unlock(&as->stats_lock);
555 return ret;
556 }
557
558 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
559 {
560 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
561 AR7240_PORT_CTRL_STATE_DISABLED);
562 }
563
564 static void ar7240sw_setup(struct ar7240sw *as)
565 {
566 struct mii_bus *mii = as->mii_bus;
567
568 /* Enable CPU port, and disable mirror port */
569 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
570 AR7240_CPU_PORT_EN |
571 (15 << AR7240_MIRROR_PORT_S));
572
573 /* Setup TAG priority mapping */
574 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
575
576 if (sw_is_ar934x(as)) {
577 /* Enable aging, MAC replacing */
578 ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
579 0x2b /* 5 min age time */ |
580 AR934X_AT_CTRL_AGE_EN |
581 AR934X_AT_CTRL_LEARN_CHANGE);
582 /* Enable ARP frame acknowledge */
583 ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
584 AR934X_QM_CTRL_ARP_EN);
585 /* Enable Broadcast/Multicast frames transmitted to the CPU */
586 ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
587 AR934X_FLOOD_MASK_BC_DP(0) |
588 AR934X_FLOOD_MASK_MC_DP(0));
589
590 /* setup MTU */
591 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
592 AR9340_GLOBAL_CTRL_MTU_M,
593 AR9340_GLOBAL_CTRL_MTU_M);
594
595 /* Enable MIB counters */
596 ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
597 AR934X_MIB_ENABLE);
598
599 } else {
600 /* Enable ARP frame acknowledge, aging, MAC replacing */
601 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
602 AR7240_AT_CTRL_RESERVED |
603 0x2b /* 5 min age time */ |
604 AR7240_AT_CTRL_AGE_EN |
605 AR7240_AT_CTRL_ARP_EN |
606 AR7240_AT_CTRL_LEARN_CHANGE);
607 /* Enable Broadcast frames transmitted to the CPU */
608 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
609 AR7240_FLOOD_MASK_BROAD_TO_CPU);
610
611 /* setup MTU */
612 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
613 AR7240_GLOBAL_CTRL_MTU_M,
614 AR7240_GLOBAL_CTRL_MTU_M);
615 }
616
617 /* setup Service TAG */
618 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
619 }
620
621 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
622 static int
623 ar7240sw_phy_poll_reset(struct mii_bus *bus)
624 {
625 const unsigned int sleep_msecs = 20;
626 int ret, elapsed, i;
627
628 for (elapsed = sleep_msecs; elapsed <= 600;
629 elapsed += sleep_msecs) {
630 msleep(sleep_msecs);
631 for (i = 0; i < AR7240_NUM_PHYS; i++) {
632 ret = ar7240sw_phy_read(bus, i, MII_BMCR);
633 if (ret < 0)
634 return ret;
635 if (ret & BMCR_RESET)
636 break;
637 if (i == AR7240_NUM_PHYS - 1) {
638 usleep_range(1000, 2000);
639 return 0;
640 }
641 }
642 }
643 return -ETIMEDOUT;
644 }
645
646 static int ar7240sw_reset(struct ar7240sw *as)
647 {
648 struct mii_bus *mii = as->mii_bus;
649 int ret;
650 int i;
651
652 /* Set all ports to disabled state. */
653 for (i = 0; i < AR7240_NUM_PORTS; i++)
654 ar7240sw_disable_port(as, i);
655
656 /* Wait for transmit queues to drain. */
657 usleep_range(2000, 3000);
658
659 /* Reset the switch. */
660 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
661 AR7240_MASK_CTRL_SOFT_RESET);
662
663 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
664 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
665
666 /* setup PHYs */
667 for (i = 0; i < AR7240_NUM_PHYS; i++) {
668 ar7240sw_phy_write(mii, i, MII_ADVERTISE,
669 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
670 ADVERTISE_PAUSE_ASYM);
671 ar7240sw_phy_write(mii, i, MII_BMCR,
672 BMCR_RESET | BMCR_ANENABLE);
673 }
674 ret = ar7240sw_phy_poll_reset(mii);
675 if (ret)
676 return ret;
677
678 ar7240sw_setup(as);
679 return ret;
680 }
681
682 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
683 {
684 struct mii_bus *mii = as->mii_bus;
685 u32 ctrl;
686 u32 vid, mode;
687
688 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
689 AR7240_PORT_CTRL_SINGLE_VLAN;
690
691 if (port == AR7240_PORT_CPU) {
692 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
693 AR7240_PORT_STATUS_SPEED_1000 |
694 AR7240_PORT_STATUS_TXFLOW |
695 AR7240_PORT_STATUS_RXFLOW |
696 AR7240_PORT_STATUS_TXMAC |
697 AR7240_PORT_STATUS_RXMAC |
698 AR7240_PORT_STATUS_DUPLEX);
699 } else {
700 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
701 AR7240_PORT_STATUS_LINK_AUTO);
702 }
703
704 /* Set the default VID for this port */
705 if (as->vlan) {
706 vid = as->vlan_id[as->pvid[port]];
707 mode = AR7240_PORT_VLAN_MODE_SECURE;
708 } else {
709 vid = port;
710 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
711 }
712
713 if (as->vlan) {
714 if (as->vlan_tagged & BIT(port))
715 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
716 AR7240_PORT_CTRL_VLAN_MODE_S;
717 else
718 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
719 AR7240_PORT_CTRL_VLAN_MODE_S;
720 } else {
721 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
722 AR7240_PORT_CTRL_VLAN_MODE_S;
723 }
724
725 if (!portmask) {
726 if (port == AR7240_PORT_CPU)
727 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
728 else
729 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
730 }
731
732 /* allow the port to talk to all other ports, but exclude its
733 * own ID to prevent frames from being reflected back to the
734 * port that they came from */
735 portmask &= ar7240sw_port_mask_but(as, port);
736
737 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
738 if (sw_is_ar934x(as)) {
739 u32 vlan1, vlan2;
740
741 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
742 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
743 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
744 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
745 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
746 } else {
747 u32 vlan;
748
749 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
750 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
751
752 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
753 }
754 }
755
756 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
757 {
758 struct mii_bus *mii = as->mii_bus;
759 u32 t;
760
761 t = (addr[4] << 8) | addr[5];
762 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
763
764 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
765 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
766
767 return 0;
768 }
769
770 static int
771 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
772 struct switch_val *val)
773 {
774 struct ar7240sw *as = sw_to_ar7240(dev);
775 as->vlan_id[val->port_vlan] = val->value.i;
776 return 0;
777 }
778
779 static int
780 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
781 struct switch_val *val)
782 {
783 struct ar7240sw *as = sw_to_ar7240(dev);
784 val->value.i = as->vlan_id[val->port_vlan];
785 return 0;
786 }
787
788 static int
789 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
790 {
791 struct ar7240sw *as = sw_to_ar7240(dev);
792
793 /* make sure no invalid PVIDs get set */
794
795 if (vlan >= dev->vlans)
796 return -EINVAL;
797
798 as->pvid[port] = vlan;
799 return 0;
800 }
801
802 static int
803 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
804 {
805 struct ar7240sw *as = sw_to_ar7240(dev);
806 *vlan = as->pvid[port];
807 return 0;
808 }
809
810 static int
811 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
812 {
813 struct ar7240sw *as = sw_to_ar7240(dev);
814 u8 ports = as->vlan_table[val->port_vlan];
815 int i;
816
817 val->len = 0;
818 for (i = 0; i < as->swdev.ports; i++) {
819 struct switch_port *p;
820
821 if (!(ports & (1 << i)))
822 continue;
823
824 p = &val->value.ports[val->len++];
825 p->id = i;
826 if (as->vlan_tagged & (1 << i))
827 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
828 else
829 p->flags = 0;
830 }
831 return 0;
832 }
833
834 static int
835 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
836 {
837 struct ar7240sw *as = sw_to_ar7240(dev);
838 u8 *vt = &as->vlan_table[val->port_vlan];
839 int i, j;
840
841 *vt = 0;
842 for (i = 0; i < val->len; i++) {
843 struct switch_port *p = &val->value.ports[i];
844
845 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
846 as->vlan_tagged |= (1 << p->id);
847 else {
848 as->vlan_tagged &= ~(1 << p->id);
849 as->pvid[p->id] = val->port_vlan;
850
851 /* make sure that an untagged port does not
852 * appear in other vlans */
853 for (j = 0; j < AR7240_MAX_VLANS; j++) {
854 if (j == val->port_vlan)
855 continue;
856 as->vlan_table[j] &= ~(1 << p->id);
857 }
858 }
859
860 *vt |= 1 << p->id;
861 }
862 return 0;
863 }
864
865 static int
866 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
867 struct switch_val *val)
868 {
869 struct ar7240sw *as = sw_to_ar7240(dev);
870 as->vlan = !!val->value.i;
871 return 0;
872 }
873
874 static int
875 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
876 struct switch_val *val)
877 {
878 struct ar7240sw *as = sw_to_ar7240(dev);
879 val->value.i = as->vlan;
880 return 0;
881 }
882
883 static void
884 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
885 {
886 struct mii_bus *mii = as->mii_bus;
887
888 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
889 return;
890
891 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
892 val &= AR7240_VTUDATA_MEMBER;
893 val |= AR7240_VTUDATA_VALID;
894 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
895 }
896 op |= AR7240_VTU_ACTIVE;
897 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
898 }
899
900 static int
901 ar7240_hw_apply(struct switch_dev *dev)
902 {
903 struct ar7240sw *as = sw_to_ar7240(dev);
904 u8 portmask[AR7240_NUM_PORTS];
905 int i, j;
906
907 /* flush all vlan translation unit entries */
908 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
909
910 memset(portmask, 0, sizeof(portmask));
911 if (as->vlan) {
912 /* calculate the port destination masks and load vlans
913 * into the vlan translation unit */
914 for (j = 0; j < AR7240_MAX_VLANS; j++) {
915 u8 vp = as->vlan_table[j];
916
917 if (!vp)
918 continue;
919
920 for (i = 0; i < as->swdev.ports; i++) {
921 u8 mask = (1 << i);
922 if (vp & mask)
923 portmask[i] |= vp & ~mask;
924 }
925
926 ar7240_vtu_op(as,
927 AR7240_VTU_OP_LOAD |
928 (as->vlan_id[j] << AR7240_VTU_VID_S),
929 as->vlan_table[j]);
930 }
931 } else {
932 /* vlan disabled:
933 * isolate all ports, but connect them to the cpu port */
934 for (i = 0; i < as->swdev.ports; i++) {
935 if (i == AR7240_PORT_CPU)
936 continue;
937
938 portmask[i] = 1 << AR7240_PORT_CPU;
939 portmask[AR7240_PORT_CPU] |= (1 << i);
940 }
941 }
942
943 /* update the port destination mask registers and tag settings */
944 for (i = 0; i < as->swdev.ports; i++)
945 ar7240sw_setup_port(as, i, portmask[i]);
946
947 return 0;
948 }
949
950 static int
951 ar7240_reset_switch(struct switch_dev *dev)
952 {
953 struct ar7240sw *as = sw_to_ar7240(dev);
954 ar7240sw_reset(as);
955 return 0;
956 }
957
958 static int
959 ar7240_get_port_link(struct switch_dev *dev, int port,
960 struct switch_port_link *link)
961 {
962 struct ar7240sw *as = sw_to_ar7240(dev);
963 struct mii_bus *mii = as->mii_bus;
964 u32 status;
965
966 if (port > AR7240_NUM_PORTS)
967 return -EINVAL;
968
969 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
970 link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
971 if (link->aneg) {
972 link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
973 if (!link->link)
974 return 0;
975 } else {
976 link->link = true;
977 }
978
979 link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
980 link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
981 link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
982 switch (status & AR7240_PORT_STATUS_SPEED_M) {
983 case AR7240_PORT_STATUS_SPEED_10:
984 link->speed = SWITCH_PORT_SPEED_10;
985 break;
986 case AR7240_PORT_STATUS_SPEED_100:
987 link->speed = SWITCH_PORT_SPEED_100;
988 break;
989 case AR7240_PORT_STATUS_SPEED_1000:
990 link->speed = SWITCH_PORT_SPEED_1000;
991 break;
992 }
993
994 return 0;
995 }
996
997 static int
998 ar7240_get_port_stats(struct switch_dev *dev, int port,
999 struct switch_port_stats *stats)
1000 {
1001 struct ar7240sw *as = sw_to_ar7240(dev);
1002
1003 if (port > AR7240_NUM_PORTS)
1004 return -EINVAL;
1005
1006 ar7240sw_capture_stats(as);
1007
1008 read_lock(&as->stats_lock);
1009 stats->rx_bytes = as->port_stats[port].rx_good_byte;
1010 stats->tx_bytes = as->port_stats[port].tx_byte;
1011 read_unlock(&as->stats_lock);
1012
1013 return 0;
1014 }
1015
1016 static struct switch_attr ar7240_globals[] = {
1017 {
1018 .type = SWITCH_TYPE_INT,
1019 .name = "enable_vlan",
1020 .description = "Enable VLAN mode",
1021 .set = ar7240_set_vlan,
1022 .get = ar7240_get_vlan,
1023 .max = 1
1024 },
1025 };
1026
1027 static struct switch_attr ar7240_port[] = {
1028 };
1029
1030 static struct switch_attr ar7240_vlan[] = {
1031 {
1032 .type = SWITCH_TYPE_INT,
1033 .name = "vid",
1034 .description = "VLAN ID",
1035 .set = ar7240_set_vid,
1036 .get = ar7240_get_vid,
1037 .max = 4094,
1038 },
1039 };
1040
1041 static const struct switch_dev_ops ar7240_ops = {
1042 .attr_global = {
1043 .attr = ar7240_globals,
1044 .n_attr = ARRAY_SIZE(ar7240_globals),
1045 },
1046 .attr_port = {
1047 .attr = ar7240_port,
1048 .n_attr = ARRAY_SIZE(ar7240_port),
1049 },
1050 .attr_vlan = {
1051 .attr = ar7240_vlan,
1052 .n_attr = ARRAY_SIZE(ar7240_vlan),
1053 },
1054 .get_port_pvid = ar7240_get_pvid,
1055 .set_port_pvid = ar7240_set_pvid,
1056 .get_vlan_ports = ar7240_get_ports,
1057 .set_vlan_ports = ar7240_set_ports,
1058 .apply_config = ar7240_hw_apply,
1059 .reset_switch = ar7240_reset_switch,
1060 .get_port_link = ar7240_get_port_link,
1061 .get_port_stats = ar7240_get_port_stats,
1062 };
1063
1064 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
1065 {
1066 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1067 struct mii_bus *mii = ag->mii_bus;
1068 struct ar7240sw *as;
1069 struct switch_dev *swdev;
1070 u32 ctrl;
1071 u16 phy_id1;
1072 u16 phy_id2;
1073 int i;
1074
1075 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
1076 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
1077 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
1078 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
1079 pr_err("%s: unknown phy id '%04x:%04x'\n",
1080 dev_name(&mii->dev), phy_id1, phy_id2);
1081 return NULL;
1082 }
1083
1084 as = kzalloc(sizeof(*as), GFP_KERNEL);
1085 if (!as)
1086 return NULL;
1087
1088 as->mii_bus = mii;
1089 as->swdata = pdata->switch_data;
1090
1091 swdev = &as->swdev;
1092
1093 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1094 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1095 AR7240_MASK_CTRL_VERSION_M;
1096
1097 if (sw_is_ar7240(as)) {
1098 swdev->name = "AR7240/AR9330 built-in switch";
1099 swdev->ports = AR7240_NUM_PORTS - 1;
1100 } else if (sw_is_ar934x(as)) {
1101 swdev->name = "AR934X built-in switch";
1102
1103 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1104 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1105 AR934X_OPER_MODE0_MAC_GMII_EN);
1106 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
1107 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1108 AR934X_OPER_MODE0_PHY_MII_EN);
1109 } else {
1110 pr_err("%s: invalid PHY interface mode\n",
1111 dev_name(&mii->dev));
1112 goto err_free;
1113 }
1114
1115 if (as->swdata->phy4_mii_en) {
1116 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1117 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1118 swdev->ports = AR7240_NUM_PORTS - 1;
1119 } else {
1120 swdev->ports = AR7240_NUM_PORTS;
1121 }
1122 } else {
1123 pr_err("%s: unsupported chip, ctrl=%08x\n",
1124 dev_name(&mii->dev), ctrl);
1125 goto err_free;
1126 }
1127
1128 swdev->cpu_port = AR7240_PORT_CPU;
1129 swdev->vlans = AR7240_MAX_VLANS;
1130 swdev->ops = &ar7240_ops;
1131
1132 if (register_switch(&as->swdev, ag->dev) < 0)
1133 goto err_free;
1134
1135 pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name);
1136
1137 /* initialize defaults */
1138 for (i = 0; i < AR7240_MAX_VLANS; i++)
1139 as->vlan_id[i] = i;
1140
1141 as->vlan_table[0] = ar7240sw_port_mask_all(as);
1142
1143 return as;
1144
1145 err_free:
1146 kfree(as);
1147 return NULL;
1148 }
1149
1150 static void link_function(struct work_struct *work) {
1151 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
1152 struct ar7240sw *as = ag->phy_priv;
1153 unsigned long flags;
1154 u8 mask;
1155 int i;
1156 int status = 0;
1157
1158 mask = ~as->swdata->phy_poll_mask;
1159 for (i = 0; i < AR7240_NUM_PHYS; i++) {
1160 int link;
1161
1162 if (!(mask & BIT(i)))
1163 continue;
1164
1165 link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
1166 if (link & BMSR_LSTATUS) {
1167 status = 1;
1168 break;
1169 }
1170 }
1171
1172 spin_lock_irqsave(&ag->lock, flags);
1173 if (status != ag->link) {
1174 ag->link = status;
1175 ag71xx_link_adjust(ag);
1176 }
1177 spin_unlock_irqrestore(&ag->lock, flags);
1178
1179 schedule_delayed_work(&ag->link_work, HZ / 2);
1180 }
1181
1182 void ag71xx_ar7240_start(struct ag71xx *ag)
1183 {
1184 struct ar7240sw *as = ag->phy_priv;
1185
1186 ar7240sw_reset(as);
1187
1188 ag->speed = SPEED_1000;
1189 ag->duplex = 1;
1190
1191 ar7240_set_addr(as, ag->dev->dev_addr);
1192 ar7240_hw_apply(&as->swdev);
1193
1194 schedule_delayed_work(&ag->link_work, HZ / 10);
1195 }
1196
1197 void ag71xx_ar7240_stop(struct ag71xx *ag)
1198 {
1199 cancel_delayed_work_sync(&ag->link_work);
1200 }
1201
1202 int ag71xx_ar7240_init(struct ag71xx *ag)
1203 {
1204 struct ar7240sw *as;
1205
1206 as = ar7240_probe(ag);
1207 if (!as)
1208 return -ENODEV;
1209
1210 ag->phy_priv = as;
1211 ar7240sw_reset(as);
1212
1213 rwlock_init(&as->stats_lock);
1214 INIT_DELAYED_WORK(&ag->link_work, link_function);
1215
1216 return 0;
1217 }
1218
1219 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1220 {
1221 struct ar7240sw *as = ag->phy_priv;
1222
1223 if (!as)
1224 return;
1225
1226 unregister_switch(&as->swdev);
1227 kfree(as);
1228 ag->phy_priv = NULL;
1229 }