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linux-firmware: fix md5sum
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
17 static inline void skb_free_frag(void *data)
18 {
19 put_page(virt_to_head_page(data));
20 }
21 #endif
22
23 #define AG71XX_DEFAULT_MSG_ENABLE \
24 (NETIF_MSG_DRV \
25 | NETIF_MSG_PROBE \
26 | NETIF_MSG_LINK \
27 | NETIF_MSG_TIMER \
28 | NETIF_MSG_IFDOWN \
29 | NETIF_MSG_IFUP \
30 | NETIF_MSG_RX_ERR \
31 | NETIF_MSG_TX_ERR)
32
33 static int ag71xx_msg_level = -1;
34
35 module_param_named(msg_level, ag71xx_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define ETH_SWITCH_HEADER_LEN 2
39
40 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
41
42 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
43 {
44 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
45 }
46
47 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
48 {
49 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
52 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
53 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
54
55 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
58 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
59 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
60 }
61
62 static void ag71xx_dump_regs(struct ag71xx *ag)
63 {
64 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
65 ag->dev->name,
66 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
67 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
68 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
69 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
70 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
71 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
72 ag->dev->name,
73 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
74 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
75 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
76 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
77 ag->dev->name,
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
79 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
81 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
82 ag->dev->name,
83 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
84 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
85 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
86 }
87
88 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
89 {
90 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
91 ag->dev->name, label, intr,
92 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
93 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
94 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
95 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
96 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
97 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
98 }
99
100 static void ag71xx_ring_free(struct ag71xx_ring *ring)
101 {
102 int ring_size = BIT(ring->order);
103 kfree(ring->buf);
104
105 if (ring->descs_cpu)
106 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
107 ring->descs_cpu, ring->descs_dma);
108 }
109
110 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
111 {
112 int ring_size = BIT(ring->order);
113 int err;
114
115 ring->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
116 &ring->descs_dma, GFP_ATOMIC);
117 if (!ring->descs_cpu) {
118 err = -ENOMEM;
119 goto err;
120 }
121
122
123 ring->buf = kzalloc(ring_size * sizeof(*ring->buf), GFP_KERNEL);
124 if (!ring->buf) {
125 err = -ENOMEM;
126 goto err;
127 }
128
129 return 0;
130
131 err:
132 return err;
133 }
134
135 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
136 {
137 struct ag71xx_ring *ring = &ag->tx_ring;
138 struct net_device *dev = ag->dev;
139 int ring_mask = BIT(ring->order) - 1;
140 u32 bytes_compl = 0, pkts_compl = 0;
141
142 while (ring->curr != ring->dirty) {
143 struct ag71xx_desc *desc;
144 u32 i = ring->dirty & ring_mask;
145
146 desc = ag71xx_ring_desc(ring, i);
147 if (!ag71xx_desc_empty(desc)) {
148 desc->ctrl = 0;
149 dev->stats.tx_errors++;
150 }
151
152 if (ring->buf[i].skb) {
153 bytes_compl += ring->buf[i].len;
154 pkts_compl++;
155 dev_kfree_skb_any(ring->buf[i].skb);
156 }
157 ring->buf[i].skb = NULL;
158 ring->dirty++;
159 }
160
161 /* flush descriptors */
162 wmb();
163
164 netdev_completed_queue(dev, pkts_compl, bytes_compl);
165 }
166
167 static void ag71xx_ring_tx_init(struct ag71xx *ag)
168 {
169 struct ag71xx_ring *ring = &ag->tx_ring;
170 int ring_size = BIT(ring->order);
171 int ring_mask = ring_size - 1;
172 int i;
173
174 for (i = 0; i < ring_size; i++) {
175 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
176
177 desc->next = (u32) (ring->descs_dma +
178 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
179
180 desc->ctrl = DESC_EMPTY;
181 ring->buf[i].skb = NULL;
182 }
183
184 /* flush descriptors */
185 wmb();
186
187 ring->curr = 0;
188 ring->dirty = 0;
189 netdev_reset_queue(ag->dev);
190 }
191
192 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
193 {
194 struct ag71xx_ring *ring = &ag->rx_ring;
195 int ring_size = BIT(ring->order);
196 int i;
197
198 if (!ring->buf)
199 return;
200
201 for (i = 0; i < ring_size; i++)
202 if (ring->buf[i].rx_buf) {
203 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
204 ag->rx_buf_size, DMA_FROM_DEVICE);
205 skb_free_frag(ring->buf[i].rx_buf);
206 }
207 }
208
209 static int ag71xx_buffer_offset(struct ag71xx *ag)
210 {
211 int offset = NET_SKB_PAD;
212
213 /*
214 * On AR71xx/AR91xx packets must be 4-byte aligned.
215 *
216 * When using builtin AR8216 support, hardware adds a 2-byte header,
217 * so we don't need any extra alignment in that case.
218 */
219 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
220 return offset;
221
222 return offset + NET_IP_ALIGN;
223 }
224
225 static int ag71xx_buffer_size(struct ag71xx *ag)
226 {
227 return ag->rx_buf_size +
228 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
229 }
230
231 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
232 int offset,
233 void *(*alloc)(unsigned int size))
234 {
235 struct ag71xx_ring *ring = &ag->rx_ring;
236 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
237 void *data;
238
239 data = alloc(ag71xx_buffer_size(ag));
240 if (!data)
241 return false;
242
243 buf->rx_buf = data;
244 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
245 DMA_FROM_DEVICE);
246 desc->data = (u32) buf->dma_addr + offset;
247 return true;
248 }
249
250 static int ag71xx_ring_rx_init(struct ag71xx *ag)
251 {
252 struct ag71xx_ring *ring = &ag->rx_ring;
253 int ring_size = BIT(ring->order);
254 int ring_mask = BIT(ring->order) - 1;
255 unsigned int i;
256 int ret;
257 int offset = ag71xx_buffer_offset(ag);
258
259 ret = 0;
260 for (i = 0; i < ring_size; i++) {
261 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
262
263 desc->next = (u32) (ring->descs_dma +
264 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
265
266 DBG("ag71xx: RX desc at %p, next is %08x\n",
267 desc, desc->next);
268 }
269
270 for (i = 0; i < ring_size; i++) {
271 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
272
273 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
274 netdev_alloc_frag)) {
275 ret = -ENOMEM;
276 break;
277 }
278
279 desc->ctrl = DESC_EMPTY;
280 }
281
282 /* flush descriptors */
283 wmb();
284
285 ring->curr = 0;
286 ring->dirty = 0;
287
288 return ret;
289 }
290
291 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
292 {
293 struct ag71xx_ring *ring = &ag->rx_ring;
294 int ring_mask = BIT(ring->order) - 1;
295 unsigned int count;
296 int offset = ag71xx_buffer_offset(ag);
297
298 count = 0;
299 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
300 struct ag71xx_desc *desc;
301 unsigned int i;
302
303 i = ring->dirty & ring_mask;
304 desc = ag71xx_ring_desc(ring, i);
305
306 if (!ring->buf[i].rx_buf &&
307 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
308 napi_alloc_frag))
309 break;
310
311 desc->ctrl = DESC_EMPTY;
312 count++;
313 }
314
315 /* flush descriptors */
316 wmb();
317
318 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
319
320 return count;
321 }
322
323 static int ag71xx_rings_init(struct ag71xx *ag)
324 {
325 int ret;
326
327 ret = ag71xx_ring_alloc(&ag->tx_ring);
328 if (ret)
329 return ret;
330
331 ag71xx_ring_tx_init(ag);
332
333 ret = ag71xx_ring_alloc(&ag->rx_ring);
334 if (ret)
335 return ret;
336
337 ret = ag71xx_ring_rx_init(ag);
338 return ret;
339 }
340
341 static void ag71xx_rings_cleanup(struct ag71xx *ag)
342 {
343 ag71xx_ring_rx_clean(ag);
344 ag71xx_ring_free(&ag->rx_ring);
345
346 ag71xx_ring_tx_clean(ag);
347 netdev_reset_queue(ag->dev);
348 ag71xx_ring_free(&ag->tx_ring);
349 }
350
351 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
352 {
353 switch (ag->speed) {
354 case SPEED_1000:
355 return "1000";
356 case SPEED_100:
357 return "100";
358 case SPEED_10:
359 return "10";
360 }
361
362 return "?";
363 }
364
365 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
366 {
367 u32 t;
368
369 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
370 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
371
372 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
373
374 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
375 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
376 }
377
378 static void ag71xx_dma_reset(struct ag71xx *ag)
379 {
380 u32 val;
381 int i;
382
383 ag71xx_dump_dma_regs(ag);
384
385 /* stop RX and TX */
386 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
387 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
388
389 /*
390 * give the hardware some time to really stop all rx/tx activity
391 * clearing the descriptors too early causes random memory corruption
392 */
393 mdelay(1);
394
395 /* clear descriptor addresses */
396 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
397 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
398
399 /* clear pending RX/TX interrupts */
400 for (i = 0; i < 256; i++) {
401 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
402 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
403 }
404
405 /* clear pending errors */
406 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
407 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
408
409 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
410 if (val)
411 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
412 ag->dev->name, val);
413
414 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
415
416 /* mask out reserved bits */
417 val &= ~0xff000000;
418
419 if (val)
420 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
421 ag->dev->name, val);
422
423 ag71xx_dump_dma_regs(ag);
424 }
425
426 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
427 MAC_CFG1_SRX | MAC_CFG1_STX)
428
429 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
430
431 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
432 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
433 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
434 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
435 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
436 FIFO_CFG4_VT)
437
438 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
439 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
440 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
441 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
442 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
443 FIFO_CFG5_17 | FIFO_CFG5_SF)
444
445 static void ag71xx_hw_stop(struct ag71xx *ag)
446 {
447 /* disable all interrupts and stop the rx/tx engine */
448 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
449 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
450 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
451 }
452
453 static void ag71xx_hw_setup(struct ag71xx *ag)
454 {
455 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
456
457 /* setup MAC configuration registers */
458 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
459
460 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
461 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
462
463 /* setup max frame length to zero */
464 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
465
466 /* setup FIFO configuration registers */
467 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
468 if (pdata->is_ar724x) {
469 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
470 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
471 } else {
472 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
473 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
474 }
475 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
476 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
477 }
478
479 static void ag71xx_hw_init(struct ag71xx *ag)
480 {
481 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
482 u32 reset_mask = pdata->reset_bit;
483
484 ag71xx_hw_stop(ag);
485
486 if (pdata->is_ar724x) {
487 u32 reset_phy = reset_mask;
488
489 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
490 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
491
492 ath79_device_reset_set(reset_phy);
493 msleep(50);
494 ath79_device_reset_clear(reset_phy);
495 msleep(200);
496 }
497
498 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
499 udelay(20);
500
501 ath79_device_reset_set(reset_mask);
502 msleep(100);
503 ath79_device_reset_clear(reset_mask);
504 msleep(200);
505
506 ag71xx_hw_setup(ag);
507
508 ag71xx_dma_reset(ag);
509 }
510
511 static void ag71xx_fast_reset(struct ag71xx *ag)
512 {
513 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
514 struct net_device *dev = ag->dev;
515 u32 reset_mask = pdata->reset_bit;
516 u32 rx_ds;
517 u32 mii_reg;
518
519 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
520
521 ag71xx_hw_stop(ag);
522 wmb();
523
524 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
525 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
526
527 ath79_device_reset_set(reset_mask);
528 udelay(10);
529 ath79_device_reset_clear(reset_mask);
530 udelay(10);
531
532 ag71xx_dma_reset(ag);
533 ag71xx_hw_setup(ag);
534 ag71xx_tx_packets(ag, true);
535 ag->tx_ring.curr = 0;
536 ag->tx_ring.dirty = 0;
537 netdev_reset_queue(ag->dev);
538
539 /* setup max frame length */
540 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
541 ag71xx_max_frame_len(ag->dev->mtu));
542
543 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
544 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
545 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
546
547 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
548 }
549
550 static void ag71xx_hw_start(struct ag71xx *ag)
551 {
552 /* start RX engine */
553 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
554
555 /* enable interrupts */
556 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
557
558 netif_wake_queue(ag->dev);
559 }
560
561 static void
562 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
563 {
564 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
565 u32 cfg2;
566 u32 ifctl;
567 u32 fifo5;
568 u32 fifo3;
569
570 if (!ag->link && update) {
571 ag71xx_hw_stop(ag);
572 netif_carrier_off(ag->dev);
573 if (netif_msg_link(ag))
574 pr_info("%s: link down\n", ag->dev->name);
575 return;
576 }
577
578 if (pdata->is_ar724x)
579 ag71xx_fast_reset(ag);
580
581 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
582 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
583 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
584
585 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
586 ifctl &= ~(MAC_IFCTL_SPEED);
587
588 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
589 fifo5 &= ~FIFO_CFG5_BM;
590
591 switch (ag->speed) {
592 case SPEED_1000:
593 cfg2 |= MAC_CFG2_IF_1000;
594 fifo5 |= FIFO_CFG5_BM;
595 break;
596 case SPEED_100:
597 cfg2 |= MAC_CFG2_IF_10_100;
598 ifctl |= MAC_IFCTL_SPEED;
599 break;
600 case SPEED_10:
601 cfg2 |= MAC_CFG2_IF_10_100;
602 break;
603 default:
604 BUG();
605 return;
606 }
607
608 if (pdata->is_ar91xx)
609 fifo3 = 0x00780fff;
610 else if (pdata->is_ar724x)
611 fifo3 = pdata->fifo_cfg3;
612 else
613 fifo3 = 0x008001ff;
614
615 if (ag->tx_ring.desc_split) {
616 fifo3 &= 0xffff;
617 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
618 }
619
620 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
621
622 if (update && pdata->set_speed)
623 pdata->set_speed(ag->speed);
624
625 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
626 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
627 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
628 ag71xx_hw_start(ag);
629
630 netif_carrier_on(ag->dev);
631 if (update && netif_msg_link(ag))
632 pr_info("%s: link up (%sMbps/%s duplex)\n",
633 ag->dev->name,
634 ag71xx_speed_str(ag),
635 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
636
637 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
638 ag->dev->name,
639 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
640 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
641 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
642
643 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
644 ag->dev->name,
645 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
646 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
647 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
648
649 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
650 ag->dev->name,
651 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
652 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
653 }
654
655 void ag71xx_link_adjust(struct ag71xx *ag)
656 {
657 __ag71xx_link_adjust(ag, true);
658 }
659
660 static int ag71xx_hw_enable(struct ag71xx *ag)
661 {
662 int ret;
663
664 ret = ag71xx_rings_init(ag);
665 if (ret)
666 return ret;
667
668 napi_enable(&ag->napi);
669 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
670 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
671 netif_start_queue(ag->dev);
672
673 return 0;
674 }
675
676 static void ag71xx_hw_disable(struct ag71xx *ag)
677 {
678 unsigned long flags;
679
680 spin_lock_irqsave(&ag->lock, flags);
681
682 netif_stop_queue(ag->dev);
683
684 ag71xx_hw_stop(ag);
685 ag71xx_dma_reset(ag);
686
687 napi_disable(&ag->napi);
688 del_timer_sync(&ag->oom_timer);
689
690 spin_unlock_irqrestore(&ag->lock, flags);
691
692 ag71xx_rings_cleanup(ag);
693 }
694
695 static int ag71xx_open(struct net_device *dev)
696 {
697 struct ag71xx *ag = netdev_priv(dev);
698 unsigned int max_frame_len;
699 int ret;
700
701 netif_carrier_off(dev);
702 max_frame_len = ag71xx_max_frame_len(dev->mtu);
703 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
704
705 /* setup max frame length */
706 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
707 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
708
709 ret = ag71xx_hw_enable(ag);
710 if (ret)
711 goto err;
712
713 ag71xx_phy_start(ag);
714
715 return 0;
716
717 err:
718 ag71xx_rings_cleanup(ag);
719 return ret;
720 }
721
722 static int ag71xx_stop(struct net_device *dev)
723 {
724 struct ag71xx *ag = netdev_priv(dev);
725
726 netif_carrier_off(dev);
727 ag71xx_phy_stop(ag);
728 ag71xx_hw_disable(ag);
729
730 return 0;
731 }
732
733 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
734 {
735 int i;
736 struct ag71xx_desc *desc;
737 int ring_mask = BIT(ring->order) - 1;
738 int ndesc = 0;
739 int split = ring->desc_split;
740
741 if (!split)
742 split = len;
743
744 while (len > 0) {
745 unsigned int cur_len = len;
746
747 i = (ring->curr + ndesc) & ring_mask;
748 desc = ag71xx_ring_desc(ring, i);
749
750 if (!ag71xx_desc_empty(desc))
751 return -1;
752
753 if (cur_len > split) {
754 cur_len = split;
755
756 /*
757 * TX will hang if DMA transfers <= 4 bytes,
758 * make sure next segment is more than 4 bytes long.
759 */
760 if (len <= split + 4)
761 cur_len -= 4;
762 }
763
764 desc->data = addr;
765 addr += cur_len;
766 len -= cur_len;
767
768 if (len > 0)
769 cur_len |= DESC_MORE;
770
771 /* prevent early tx attempt of this descriptor */
772 if (!ndesc)
773 cur_len |= DESC_EMPTY;
774
775 desc->ctrl = cur_len;
776 ndesc++;
777 }
778
779 return ndesc;
780 }
781
782 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
783 struct net_device *dev)
784 {
785 struct ag71xx *ag = netdev_priv(dev);
786 struct ag71xx_ring *ring = &ag->tx_ring;
787 int ring_mask = BIT(ring->order) - 1;
788 int ring_size = BIT(ring->order);
789 struct ag71xx_desc *desc;
790 dma_addr_t dma_addr;
791 int i, n, ring_min;
792
793 if (ag71xx_has_ar8216(ag))
794 ag71xx_add_ar8216_header(ag, skb);
795
796 if (skb->len <= 4) {
797 DBG("%s: packet len is too small\n", ag->dev->name);
798 goto err_drop;
799 }
800
801 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
802 DMA_TO_DEVICE);
803
804 i = ring->curr & ring_mask;
805 desc = ag71xx_ring_desc(ring, i);
806
807 /* setup descriptor fields */
808 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
809 if (n < 0)
810 goto err_drop_unmap;
811
812 i = (ring->curr + n - 1) & ring_mask;
813 ring->buf[i].len = skb->len;
814 ring->buf[i].skb = skb;
815 ring->buf[i].timestamp = jiffies;
816
817 netdev_sent_queue(dev, skb->len);
818
819 desc->ctrl &= ~DESC_EMPTY;
820 ring->curr += n;
821
822 /* flush descriptor */
823 wmb();
824
825 ring_min = 2;
826 if (ring->desc_split)
827 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
828
829 if (ring->curr - ring->dirty >= ring_size - ring_min) {
830 DBG("%s: tx queue full\n", dev->name);
831 netif_stop_queue(dev);
832 }
833
834 DBG("%s: packet injected into TX queue\n", ag->dev->name);
835
836 /* enable TX engine */
837 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
838
839 return NETDEV_TX_OK;
840
841 err_drop_unmap:
842 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
843
844 err_drop:
845 dev->stats.tx_dropped++;
846
847 dev_kfree_skb(skb);
848 return NETDEV_TX_OK;
849 }
850
851 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
852 {
853 struct ag71xx *ag = netdev_priv(dev);
854 int ret;
855
856 switch (cmd) {
857 case SIOCETHTOOL:
858 if (ag->phy_dev == NULL)
859 break;
860
861 spin_lock_irq(&ag->lock);
862 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
863 spin_unlock_irq(&ag->lock);
864 return ret;
865
866 case SIOCSIFHWADDR:
867 if (copy_from_user
868 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
869 return -EFAULT;
870 return 0;
871
872 case SIOCGIFHWADDR:
873 if (copy_to_user
874 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
875 return -EFAULT;
876 return 0;
877
878 case SIOCGMIIPHY:
879 case SIOCGMIIREG:
880 case SIOCSMIIREG:
881 if (ag->phy_dev == NULL)
882 break;
883
884 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
885
886 default:
887 break;
888 }
889
890 return -EOPNOTSUPP;
891 }
892
893 static void ag71xx_oom_timer_handler(unsigned long data)
894 {
895 struct net_device *dev = (struct net_device *) data;
896 struct ag71xx *ag = netdev_priv(dev);
897
898 napi_schedule(&ag->napi);
899 }
900
901 static void ag71xx_tx_timeout(struct net_device *dev)
902 {
903 struct ag71xx *ag = netdev_priv(dev);
904
905 if (netif_msg_tx_err(ag))
906 pr_info("%s: tx timeout\n", ag->dev->name);
907
908 schedule_work(&ag->restart_work);
909 }
910
911 static void ag71xx_restart_work_func(struct work_struct *work)
912 {
913 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
914
915 rtnl_lock();
916 ag71xx_hw_disable(ag);
917 ag71xx_hw_enable(ag);
918 if (ag->link)
919 __ag71xx_link_adjust(ag, false);
920 rtnl_unlock();
921 }
922
923 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
924 {
925 u32 rx_sm, tx_sm, rx_fd;
926
927 if (likely(time_before(jiffies, timestamp + HZ/10)))
928 return false;
929
930 if (!netif_carrier_ok(ag->dev))
931 return false;
932
933 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
934 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
935 return true;
936
937 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
938 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
939 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
940 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
941 return true;
942
943 return false;
944 }
945
946 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
947 {
948 struct ag71xx_ring *ring = &ag->tx_ring;
949 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
950 int ring_mask = BIT(ring->order) - 1;
951 int ring_size = BIT(ring->order);
952 int sent = 0;
953 int bytes_compl = 0;
954 int n = 0;
955
956 DBG("%s: processing TX ring\n", ag->dev->name);
957
958 while (ring->dirty + n != ring->curr) {
959 unsigned int i = (ring->dirty + n) & ring_mask;
960 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
961 struct sk_buff *skb = ring->buf[i].skb;
962
963 if (!flush && !ag71xx_desc_empty(desc)) {
964 if (pdata->is_ar724x &&
965 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
966 schedule_work(&ag->restart_work);
967 break;
968 }
969
970 if (flush)
971 desc->ctrl |= DESC_EMPTY;
972
973 n++;
974 if (!skb)
975 continue;
976
977 dev_kfree_skb_any(skb);
978 ring->buf[i].skb = NULL;
979
980 bytes_compl += ring->buf[i].len;
981
982 sent++;
983 ring->dirty += n;
984
985 while (n > 0) {
986 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
987 n--;
988 }
989 }
990
991 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
992
993 ag->dev->stats.tx_bytes += bytes_compl;
994 ag->dev->stats.tx_packets += sent;
995
996 if (!sent)
997 return 0;
998
999 netdev_completed_queue(ag->dev, sent, bytes_compl);
1000 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1001 netif_wake_queue(ag->dev);
1002
1003 return sent;
1004 }
1005
1006 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1007 {
1008 struct net_device *dev = ag->dev;
1009 struct ag71xx_ring *ring = &ag->rx_ring;
1010 int offset = ag71xx_buffer_offset(ag);
1011 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1012 int ring_mask = BIT(ring->order) - 1;
1013 int ring_size = BIT(ring->order);
1014 struct sk_buff_head queue;
1015 struct sk_buff *skb;
1016 int done = 0;
1017
1018 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1019 dev->name, limit, ring->curr, ring->dirty);
1020
1021 skb_queue_head_init(&queue);
1022
1023 while (done < limit) {
1024 unsigned int i = ring->curr & ring_mask;
1025 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1026 int pktlen;
1027 int err = 0;
1028
1029 if (ag71xx_desc_empty(desc))
1030 break;
1031
1032 if ((ring->dirty + ring_size) == ring->curr) {
1033 ag71xx_assert(0);
1034 break;
1035 }
1036
1037 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1038
1039 pktlen = desc->ctrl & pktlen_mask;
1040 pktlen -= ETH_FCS_LEN;
1041
1042 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1043 ag->rx_buf_size, DMA_FROM_DEVICE);
1044
1045 dev->stats.rx_packets++;
1046 dev->stats.rx_bytes += pktlen;
1047
1048 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1049 if (!skb) {
1050 skb_free_frag(ring->buf[i].rx_buf);
1051 goto next;
1052 }
1053
1054 skb_reserve(skb, offset);
1055 skb_put(skb, pktlen);
1056
1057 if (ag71xx_has_ar8216(ag))
1058 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1059
1060 if (err) {
1061 dev->stats.rx_dropped++;
1062 kfree_skb(skb);
1063 } else {
1064 skb->dev = dev;
1065 skb->ip_summed = CHECKSUM_NONE;
1066 __skb_queue_tail(&queue, skb);
1067 }
1068
1069 next:
1070 ring->buf[i].rx_buf = NULL;
1071 done++;
1072
1073 ring->curr++;
1074 }
1075
1076 ag71xx_ring_rx_refill(ag);
1077
1078 while ((skb = __skb_dequeue(&queue)) != NULL) {
1079 skb->protocol = eth_type_trans(skb, dev);
1080 netif_receive_skb(skb);
1081 }
1082
1083 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1084 dev->name, ring->curr, ring->dirty, done);
1085
1086 return done;
1087 }
1088
1089 static int ag71xx_poll(struct napi_struct *napi, int limit)
1090 {
1091 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1092 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1093 struct net_device *dev = ag->dev;
1094 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1095 int rx_ring_size = BIT(rx_ring->order);
1096 unsigned long flags;
1097 u32 status;
1098 int tx_done;
1099 int rx_done;
1100
1101 pdata->ddr_flush();
1102 tx_done = ag71xx_tx_packets(ag, false);
1103
1104 DBG("%s: processing RX ring\n", dev->name);
1105 rx_done = ag71xx_rx_packets(ag, limit);
1106
1107 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1108
1109 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1110 goto oom;
1111
1112 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1113 if (unlikely(status & RX_STATUS_OF)) {
1114 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1115 dev->stats.rx_fifo_errors++;
1116
1117 /* restart RX */
1118 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1119 }
1120
1121 if (rx_done < limit) {
1122 if (status & RX_STATUS_PR)
1123 goto more;
1124
1125 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1126 if (status & TX_STATUS_PS)
1127 goto more;
1128
1129 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1130 dev->name, rx_done, tx_done, limit);
1131
1132 napi_complete(napi);
1133
1134 /* enable interrupts */
1135 spin_lock_irqsave(&ag->lock, flags);
1136 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1137 spin_unlock_irqrestore(&ag->lock, flags);
1138 return rx_done;
1139 }
1140
1141 more:
1142 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1143 dev->name, rx_done, tx_done, limit);
1144 return limit;
1145
1146 oom:
1147 if (netif_msg_rx_err(ag))
1148 pr_info("%s: out of memory\n", dev->name);
1149
1150 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1151 napi_complete(napi);
1152 return 0;
1153 }
1154
1155 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1156 {
1157 struct net_device *dev = dev_id;
1158 struct ag71xx *ag = netdev_priv(dev);
1159 u32 status;
1160
1161 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1162 ag71xx_dump_intr(ag, "raw", status);
1163
1164 if (unlikely(!status))
1165 return IRQ_NONE;
1166
1167 if (unlikely(status & AG71XX_INT_ERR)) {
1168 if (status & AG71XX_INT_TX_BE) {
1169 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1170 dev_err(&dev->dev, "TX BUS error\n");
1171 }
1172 if (status & AG71XX_INT_RX_BE) {
1173 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1174 dev_err(&dev->dev, "RX BUS error\n");
1175 }
1176 }
1177
1178 if (likely(status & AG71XX_INT_POLL)) {
1179 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1180 DBG("%s: enable polling mode\n", dev->name);
1181 napi_schedule(&ag->napi);
1182 }
1183
1184 ag71xx_debugfs_update_int_stats(ag, status);
1185
1186 return IRQ_HANDLED;
1187 }
1188
1189 #ifdef CONFIG_NET_POLL_CONTROLLER
1190 /*
1191 * Polling 'interrupt' - used by things like netconsole to send skbs
1192 * without having to re-enable interrupts. It's not called while
1193 * the interrupt routine is executing.
1194 */
1195 static void ag71xx_netpoll(struct net_device *dev)
1196 {
1197 disable_irq(dev->irq);
1198 ag71xx_interrupt(dev->irq, dev);
1199 enable_irq(dev->irq);
1200 }
1201 #endif
1202
1203 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1204 {
1205 struct ag71xx *ag = netdev_priv(dev);
1206 unsigned int max_frame_len;
1207
1208 max_frame_len = ag71xx_max_frame_len(new_mtu);
1209 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1210 return -EINVAL;
1211
1212 if (netif_running(dev))
1213 return -EBUSY;
1214
1215 dev->mtu = new_mtu;
1216 return 0;
1217 }
1218
1219 static const struct net_device_ops ag71xx_netdev_ops = {
1220 .ndo_open = ag71xx_open,
1221 .ndo_stop = ag71xx_stop,
1222 .ndo_start_xmit = ag71xx_hard_start_xmit,
1223 .ndo_do_ioctl = ag71xx_do_ioctl,
1224 .ndo_tx_timeout = ag71xx_tx_timeout,
1225 .ndo_change_mtu = ag71xx_change_mtu,
1226 .ndo_set_mac_address = eth_mac_addr,
1227 .ndo_validate_addr = eth_validate_addr,
1228 #ifdef CONFIG_NET_POLL_CONTROLLER
1229 .ndo_poll_controller = ag71xx_netpoll,
1230 #endif
1231 };
1232
1233 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1234 {
1235 switch (mode) {
1236 case PHY_INTERFACE_MODE_MII:
1237 return "MII";
1238 case PHY_INTERFACE_MODE_GMII:
1239 return "GMII";
1240 case PHY_INTERFACE_MODE_RMII:
1241 return "RMII";
1242 case PHY_INTERFACE_MODE_RGMII:
1243 return "RGMII";
1244 case PHY_INTERFACE_MODE_SGMII:
1245 return "SGMII";
1246 default:
1247 break;
1248 }
1249
1250 return "unknown";
1251 }
1252
1253
1254 static int ag71xx_probe(struct platform_device *pdev)
1255 {
1256 struct net_device *dev;
1257 struct resource *res;
1258 struct ag71xx *ag;
1259 struct ag71xx_platform_data *pdata;
1260 int tx_size, err;
1261
1262 pdata = pdev->dev.platform_data;
1263 if (!pdata) {
1264 dev_err(&pdev->dev, "no platform data specified\n");
1265 err = -ENXIO;
1266 goto err_out;
1267 }
1268
1269 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1270 dev_err(&pdev->dev, "no MII bus device specified\n");
1271 err = -EINVAL;
1272 goto err_out;
1273 }
1274
1275 dev = alloc_etherdev(sizeof(*ag));
1276 if (!dev) {
1277 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1278 err = -ENOMEM;
1279 goto err_out;
1280 }
1281
1282 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1283 return -EINVAL;
1284
1285 SET_NETDEV_DEV(dev, &pdev->dev);
1286
1287 ag = netdev_priv(dev);
1288 ag->pdev = pdev;
1289 ag->dev = dev;
1290 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1291 AG71XX_DEFAULT_MSG_ENABLE);
1292 spin_lock_init(&ag->lock);
1293
1294 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1295 if (!res) {
1296 dev_err(&pdev->dev, "no mac_base resource found\n");
1297 err = -ENXIO;
1298 goto err_out;
1299 }
1300
1301 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1302 if (!ag->mac_base) {
1303 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1304 err = -ENOMEM;
1305 goto err_free_dev;
1306 }
1307
1308 dev->irq = platform_get_irq(pdev, 0);
1309 err = request_irq(dev->irq, ag71xx_interrupt,
1310 0x0,
1311 dev->name, dev);
1312 if (err) {
1313 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1314 goto err_unmap_base;
1315 }
1316
1317 dev->base_addr = (unsigned long)ag->mac_base;
1318 dev->netdev_ops = &ag71xx_netdev_ops;
1319 dev->ethtool_ops = &ag71xx_ethtool_ops;
1320
1321 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1322
1323 init_timer(&ag->oom_timer);
1324 ag->oom_timer.data = (unsigned long) dev;
1325 ag->oom_timer.function = ag71xx_oom_timer_handler;
1326
1327 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1328 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1329
1330 ag->max_frame_len = pdata->max_frame_len;
1331 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1332
1333 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1334 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1335 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1336 }
1337 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1338
1339 ag->stop_desc = dma_alloc_coherent(NULL,
1340 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1341
1342 if (!ag->stop_desc)
1343 goto err_free_irq;
1344
1345 ag->stop_desc->data = 0;
1346 ag->stop_desc->ctrl = 0;
1347 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1348
1349 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1350
1351 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1352
1353 ag71xx_dump_regs(ag);
1354
1355 ag71xx_hw_init(ag);
1356
1357 ag71xx_dump_regs(ag);
1358
1359 err = ag71xx_phy_connect(ag);
1360 if (err)
1361 goto err_free_desc;
1362
1363 err = ag71xx_debugfs_init(ag);
1364 if (err)
1365 goto err_phy_disconnect;
1366
1367 platform_set_drvdata(pdev, dev);
1368
1369 err = register_netdev(dev);
1370 if (err) {
1371 dev_err(&pdev->dev, "unable to register net device\n");
1372 goto err_debugfs_exit;
1373 }
1374
1375 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1376 dev->name, dev->base_addr, dev->irq,
1377 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1378
1379 return 0;
1380
1381 err_debugfs_exit:
1382 ag71xx_debugfs_exit(ag);
1383 err_phy_disconnect:
1384 ag71xx_phy_disconnect(ag);
1385 err_free_desc:
1386 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1387 ag->stop_desc_dma);
1388 err_free_irq:
1389 free_irq(dev->irq, dev);
1390 err_unmap_base:
1391 iounmap(ag->mac_base);
1392 err_free_dev:
1393 kfree(dev);
1394 err_out:
1395 platform_set_drvdata(pdev, NULL);
1396 return err;
1397 }
1398
1399 static int ag71xx_remove(struct platform_device *pdev)
1400 {
1401 struct net_device *dev = platform_get_drvdata(pdev);
1402
1403 if (dev) {
1404 struct ag71xx *ag = netdev_priv(dev);
1405
1406 ag71xx_debugfs_exit(ag);
1407 ag71xx_phy_disconnect(ag);
1408 unregister_netdev(dev);
1409 free_irq(dev->irq, dev);
1410 iounmap(ag->mac_base);
1411 kfree(dev);
1412 platform_set_drvdata(pdev, NULL);
1413 }
1414
1415 return 0;
1416 }
1417
1418 static struct platform_driver ag71xx_driver = {
1419 .probe = ag71xx_probe,
1420 .remove = ag71xx_remove,
1421 .driver = {
1422 .name = AG71XX_DRV_NAME,
1423 }
1424 };
1425
1426 static int __init ag71xx_module_init(void)
1427 {
1428 int ret;
1429
1430 ret = ag71xx_debugfs_root_init();
1431 if (ret)
1432 goto err_out;
1433
1434 ret = ag71xx_mdio_driver_init();
1435 if (ret)
1436 goto err_debugfs_exit;
1437
1438 ret = platform_driver_register(&ag71xx_driver);
1439 if (ret)
1440 goto err_mdio_exit;
1441
1442 return 0;
1443
1444 err_mdio_exit:
1445 ag71xx_mdio_driver_exit();
1446 err_debugfs_exit:
1447 ag71xx_debugfs_root_exit();
1448 err_out:
1449 return ret;
1450 }
1451
1452 static void __exit ag71xx_module_exit(void)
1453 {
1454 platform_driver_unregister(&ag71xx_driver);
1455 ag71xx_mdio_driver_exit();
1456 ag71xx_debugfs_root_exit();
1457 }
1458
1459 module_init(ag71xx_module_init);
1460 module_exit(ag71xx_module_exit);
1461
1462 MODULE_VERSION(AG71XX_DRV_VERSION);
1463 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1464 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1465 MODULE_LICENSE("GPL v2");
1466 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository