ar71xx: remove obsolete '< KERNEL_VERSION(4, 2, 0)' check
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define ETH_SWITCH_HEADER_LEN 2
32
33 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
34
35 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
36 {
37 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
38 }
39
40 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
41 {
42 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
43 ag->dev->name,
44 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
45 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
46 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
47
48 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
51 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
52 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
53 }
54
55 static void ag71xx_dump_regs(struct ag71xx *ag)
56 {
57 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
58 ag->dev->name,
59 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
60 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
61 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
62 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
63 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
64 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
65 ag->dev->name,
66 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
67 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
68 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
69 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
70 ag->dev->name,
71 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
72 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
73 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
74 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
75 ag->dev->name,
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
79 }
80
81 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
82 {
83 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
84 ag->dev->name, label, intr,
85 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
86 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
87 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
88 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
89 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
90 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
91 }
92
93 static void ag71xx_ring_free(struct ag71xx_ring *ring)
94 {
95 int ring_size = BIT(ring->order);
96 kfree(ring->buf);
97
98 if (ring->descs_cpu)
99 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
100 ring->descs_cpu, ring->descs_dma);
101 }
102
103 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
104 {
105 int ring_size = BIT(ring->order);
106 int err;
107
108 ring->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
109 &ring->descs_dma, GFP_ATOMIC);
110 if (!ring->descs_cpu) {
111 err = -ENOMEM;
112 goto err;
113 }
114
115
116 ring->buf = kzalloc(ring_size * sizeof(*ring->buf), GFP_KERNEL);
117 if (!ring->buf) {
118 err = -ENOMEM;
119 goto err;
120 }
121
122 return 0;
123
124 err:
125 return err;
126 }
127
128 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
129 {
130 struct ag71xx_ring *ring = &ag->tx_ring;
131 struct net_device *dev = ag->dev;
132 int ring_mask = BIT(ring->order) - 1;
133 u32 bytes_compl = 0, pkts_compl = 0;
134
135 while (ring->curr != ring->dirty) {
136 struct ag71xx_desc *desc;
137 u32 i = ring->dirty & ring_mask;
138
139 desc = ag71xx_ring_desc(ring, i);
140 if (!ag71xx_desc_empty(desc)) {
141 desc->ctrl = 0;
142 dev->stats.tx_errors++;
143 }
144
145 if (ring->buf[i].skb) {
146 bytes_compl += ring->buf[i].len;
147 pkts_compl++;
148 dev_kfree_skb_any(ring->buf[i].skb);
149 }
150 ring->buf[i].skb = NULL;
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 netdev_completed_queue(dev, pkts_compl, bytes_compl);
158 }
159
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
161 {
162 struct ag71xx_ring *ring = &ag->tx_ring;
163 int ring_size = BIT(ring->order);
164 int ring_mask = ring_size - 1;
165 int i;
166
167 for (i = 0; i < ring_size; i++) {
168 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
169
170 desc->next = (u32) (ring->descs_dma +
171 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
172
173 desc->ctrl = DESC_EMPTY;
174 ring->buf[i].skb = NULL;
175 }
176
177 /* flush descriptors */
178 wmb();
179
180 ring->curr = 0;
181 ring->dirty = 0;
182 netdev_reset_queue(ag->dev);
183 }
184
185 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
186 {
187 struct ag71xx_ring *ring = &ag->rx_ring;
188 int ring_size = BIT(ring->order);
189 int i;
190
191 if (!ring->buf)
192 return;
193
194 for (i = 0; i < ring_size; i++)
195 if (ring->buf[i].rx_buf) {
196 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
197 ag->rx_buf_size, DMA_FROM_DEVICE);
198 skb_free_frag(ring->buf[i].rx_buf);
199 }
200 }
201
202 static int ag71xx_buffer_offset(struct ag71xx *ag)
203 {
204 int offset = NET_SKB_PAD;
205
206 /*
207 * On AR71xx/AR91xx packets must be 4-byte aligned.
208 *
209 * When using builtin AR8216 support, hardware adds a 2-byte header,
210 * so we don't need any extra alignment in that case.
211 */
212 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
213 return offset;
214
215 return offset + NET_IP_ALIGN;
216 }
217
218 static int ag71xx_buffer_size(struct ag71xx *ag)
219 {
220 return ag->rx_buf_size +
221 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
222 }
223
224 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
225 int offset,
226 void *(*alloc)(unsigned int size))
227 {
228 struct ag71xx_ring *ring = &ag->rx_ring;
229 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
230 void *data;
231
232 data = alloc(ag71xx_buffer_size(ag));
233 if (!data)
234 return false;
235
236 buf->rx_buf = data;
237 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
238 DMA_FROM_DEVICE);
239 desc->data = (u32) buf->dma_addr + offset;
240 return true;
241 }
242
243 static int ag71xx_ring_rx_init(struct ag71xx *ag)
244 {
245 struct ag71xx_ring *ring = &ag->rx_ring;
246 int ring_size = BIT(ring->order);
247 int ring_mask = BIT(ring->order) - 1;
248 unsigned int i;
249 int ret;
250 int offset = ag71xx_buffer_offset(ag);
251
252 ret = 0;
253 for (i = 0; i < ring_size; i++) {
254 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
255
256 desc->next = (u32) (ring->descs_dma +
257 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
258
259 DBG("ag71xx: RX desc at %p, next is %08x\n",
260 desc, desc->next);
261 }
262
263 for (i = 0; i < ring_size; i++) {
264 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
265
266 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
267 netdev_alloc_frag)) {
268 ret = -ENOMEM;
269 break;
270 }
271
272 desc->ctrl = DESC_EMPTY;
273 }
274
275 /* flush descriptors */
276 wmb();
277
278 ring->curr = 0;
279 ring->dirty = 0;
280
281 return ret;
282 }
283
284 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
285 {
286 struct ag71xx_ring *ring = &ag->rx_ring;
287 int ring_mask = BIT(ring->order) - 1;
288 unsigned int count;
289 int offset = ag71xx_buffer_offset(ag);
290
291 count = 0;
292 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
293 struct ag71xx_desc *desc;
294 unsigned int i;
295
296 i = ring->dirty & ring_mask;
297 desc = ag71xx_ring_desc(ring, i);
298
299 if (!ring->buf[i].rx_buf &&
300 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
301 napi_alloc_frag))
302 break;
303
304 desc->ctrl = DESC_EMPTY;
305 count++;
306 }
307
308 /* flush descriptors */
309 wmb();
310
311 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
312
313 return count;
314 }
315
316 static int ag71xx_rings_init(struct ag71xx *ag)
317 {
318 int ret;
319
320 ret = ag71xx_ring_alloc(&ag->tx_ring);
321 if (ret)
322 return ret;
323
324 ag71xx_ring_tx_init(ag);
325
326 ret = ag71xx_ring_alloc(&ag->rx_ring);
327 if (ret)
328 return ret;
329
330 ret = ag71xx_ring_rx_init(ag);
331 return ret;
332 }
333
334 static void ag71xx_rings_cleanup(struct ag71xx *ag)
335 {
336 ag71xx_ring_rx_clean(ag);
337 ag71xx_ring_free(&ag->rx_ring);
338
339 ag71xx_ring_tx_clean(ag);
340 netdev_reset_queue(ag->dev);
341 ag71xx_ring_free(&ag->tx_ring);
342 }
343
344 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
345 {
346 switch (ag->speed) {
347 case SPEED_1000:
348 return "1000";
349 case SPEED_100:
350 return "100";
351 case SPEED_10:
352 return "10";
353 }
354
355 return "?";
356 }
357
358 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
359 {
360 u32 t;
361
362 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
363 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
364
365 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
366
367 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
368 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
369 }
370
371 static void ag71xx_dma_reset(struct ag71xx *ag)
372 {
373 u32 val;
374 int i;
375
376 ag71xx_dump_dma_regs(ag);
377
378 /* stop RX and TX */
379 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
380 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
381
382 /*
383 * give the hardware some time to really stop all rx/tx activity
384 * clearing the descriptors too early causes random memory corruption
385 */
386 mdelay(1);
387
388 /* clear descriptor addresses */
389 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
390 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
391
392 /* clear pending RX/TX interrupts */
393 for (i = 0; i < 256; i++) {
394 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
395 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
396 }
397
398 /* clear pending errors */
399 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
400 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
401
402 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
403 if (val)
404 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
405 ag->dev->name, val);
406
407 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
408
409 /* mask out reserved bits */
410 val &= ~0xff000000;
411
412 if (val)
413 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
414 ag->dev->name, val);
415
416 ag71xx_dump_dma_regs(ag);
417 }
418
419 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
420 MAC_CFG1_SRX | MAC_CFG1_STX)
421
422 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
423
424 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
425 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
426 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
427 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
428 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
429 FIFO_CFG4_VT)
430
431 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
432 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
433 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
434 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
435 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
436 FIFO_CFG5_17 | FIFO_CFG5_SF)
437
438 static void ag71xx_hw_stop(struct ag71xx *ag)
439 {
440 /* disable all interrupts and stop the rx/tx engine */
441 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
442 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
443 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
444 }
445
446 static void ag71xx_hw_setup(struct ag71xx *ag)
447 {
448 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
449 u32 init = MAC_CFG1_INIT;
450
451 /* setup MAC configuration registers */
452 if (pdata->use_flow_control)
453 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
454 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
455
456 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
457 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
458
459 /* setup max frame length to zero */
460 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
461
462 /* setup FIFO configuration registers */
463 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
464 if (pdata->is_ar724x) {
465 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
466 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
467 } else {
468 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
469 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
470 }
471 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
472 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
473 }
474
475 static void ag71xx_hw_init(struct ag71xx *ag)
476 {
477 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
478 u32 reset_mask = pdata->reset_bit;
479
480 ag71xx_hw_stop(ag);
481
482 if (pdata->is_ar724x) {
483 u32 reset_phy = reset_mask;
484
485 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
486 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
487
488 ath79_device_reset_set(reset_phy);
489 msleep(50);
490 ath79_device_reset_clear(reset_phy);
491 msleep(200);
492 }
493
494 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
495 udelay(20);
496
497 ath79_device_reset_set(reset_mask);
498 msleep(100);
499 ath79_device_reset_clear(reset_mask);
500 msleep(200);
501
502 ag71xx_hw_setup(ag);
503
504 ag71xx_dma_reset(ag);
505 }
506
507 static void ag71xx_fast_reset(struct ag71xx *ag)
508 {
509 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
510 struct net_device *dev = ag->dev;
511 u32 reset_mask = pdata->reset_bit;
512 u32 rx_ds;
513 u32 mii_reg;
514
515 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
516
517 ag71xx_hw_stop(ag);
518 wmb();
519
520 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
521 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
522
523 ag71xx_tx_packets(ag, true);
524
525 ath79_device_reset_set(reset_mask);
526 udelay(10);
527 ath79_device_reset_clear(reset_mask);
528 udelay(10);
529
530 ag71xx_dma_reset(ag);
531 ag71xx_hw_setup(ag);
532 ag->tx_ring.curr = 0;
533 ag->tx_ring.dirty = 0;
534 netdev_reset_queue(ag->dev);
535
536 /* setup max frame length */
537 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
538 ag71xx_max_frame_len(ag->dev->mtu));
539
540 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
541 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
542 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
543
544 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
545 }
546
547 static void ag71xx_hw_start(struct ag71xx *ag)
548 {
549 /* start RX engine */
550 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
551
552 /* enable interrupts */
553 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
554
555 netif_wake_queue(ag->dev);
556 }
557
558 static void
559 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
560 {
561 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
562 u32 cfg2;
563 u32 ifctl;
564 u32 fifo5;
565 u32 fifo3;
566
567 if (!ag->link && update) {
568 ag71xx_hw_stop(ag);
569 netif_carrier_off(ag->dev);
570 if (netif_msg_link(ag))
571 pr_info("%s: link down\n", ag->dev->name);
572 return;
573 }
574
575 if (pdata->is_ar724x)
576 ag71xx_fast_reset(ag);
577
578 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
579 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
580 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
581
582 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
583 ifctl &= ~(MAC_IFCTL_SPEED);
584
585 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
586 fifo5 &= ~FIFO_CFG5_BM;
587
588 switch (ag->speed) {
589 case SPEED_1000:
590 cfg2 |= MAC_CFG2_IF_1000;
591 fifo5 |= FIFO_CFG5_BM;
592 break;
593 case SPEED_100:
594 cfg2 |= MAC_CFG2_IF_10_100;
595 ifctl |= MAC_IFCTL_SPEED;
596 break;
597 case SPEED_10:
598 cfg2 |= MAC_CFG2_IF_10_100;
599 break;
600 default:
601 BUG();
602 return;
603 }
604
605 if (pdata->is_ar91xx)
606 fifo3 = 0x00780fff;
607 else if (pdata->is_ar724x)
608 fifo3 = pdata->fifo_cfg3;
609 else
610 fifo3 = 0x008001ff;
611
612 if (ag->tx_ring.desc_split) {
613 fifo3 &= 0xffff;
614 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
615 }
616
617 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
618
619 if (update && pdata->set_speed)
620 pdata->set_speed(ag->speed);
621
622 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
623 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
624 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
625
626 if (pdata->disable_inline_checksum_engine) {
627 /*
628 * The rx ring buffer can stall on small packets on QCA953x and
629 * QCA956x. Disabling the inline checksum engine fixes the stall.
630 * The wr, rr functions cannot be used since this hidden register
631 * is outside of the normal ag71xx register block.
632 */
633 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
634 if (dam) {
635 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
636 (void)__raw_readl(dam);
637 iounmap(dam);
638 }
639 }
640
641 ag71xx_hw_start(ag);
642
643 netif_carrier_on(ag->dev);
644 if (update && netif_msg_link(ag))
645 pr_info("%s: link up (%sMbps/%s duplex)\n",
646 ag->dev->name,
647 ag71xx_speed_str(ag),
648 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
649
650 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
651 ag->dev->name,
652 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
653 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
654 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
655
656 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
657 ag->dev->name,
658 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
659 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
660 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
661
662 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
663 ag->dev->name,
664 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
665 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
666 }
667
668 void ag71xx_link_adjust(struct ag71xx *ag)
669 {
670 __ag71xx_link_adjust(ag, true);
671 }
672
673 static int ag71xx_hw_enable(struct ag71xx *ag)
674 {
675 int ret;
676
677 ret = ag71xx_rings_init(ag);
678 if (ret)
679 return ret;
680
681 napi_enable(&ag->napi);
682 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
683 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
684 netif_start_queue(ag->dev);
685
686 return 0;
687 }
688
689 static void ag71xx_hw_disable(struct ag71xx *ag)
690 {
691 unsigned long flags;
692
693 spin_lock_irqsave(&ag->lock, flags);
694
695 netif_stop_queue(ag->dev);
696
697 ag71xx_hw_stop(ag);
698 ag71xx_dma_reset(ag);
699
700 napi_disable(&ag->napi);
701 del_timer_sync(&ag->oom_timer);
702
703 spin_unlock_irqrestore(&ag->lock, flags);
704
705 ag71xx_rings_cleanup(ag);
706 }
707
708 static int ag71xx_open(struct net_device *dev)
709 {
710 struct ag71xx *ag = netdev_priv(dev);
711 unsigned int max_frame_len;
712 int ret;
713
714 netif_carrier_off(dev);
715 max_frame_len = ag71xx_max_frame_len(dev->mtu);
716 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
717
718 /* setup max frame length */
719 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
720 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
721
722 ret = ag71xx_hw_enable(ag);
723 if (ret)
724 goto err;
725
726 ag71xx_phy_start(ag);
727
728 return 0;
729
730 err:
731 ag71xx_rings_cleanup(ag);
732 return ret;
733 }
734
735 static int ag71xx_stop(struct net_device *dev)
736 {
737 struct ag71xx *ag = netdev_priv(dev);
738
739 netif_carrier_off(dev);
740 ag71xx_phy_stop(ag);
741 ag71xx_hw_disable(ag);
742
743 return 0;
744 }
745
746 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
747 {
748 int i;
749 struct ag71xx_desc *desc;
750 int ring_mask = BIT(ring->order) - 1;
751 int ndesc = 0;
752 int split = ring->desc_split;
753
754 if (!split)
755 split = len;
756
757 while (len > 0) {
758 unsigned int cur_len = len;
759
760 i = (ring->curr + ndesc) & ring_mask;
761 desc = ag71xx_ring_desc(ring, i);
762
763 if (!ag71xx_desc_empty(desc))
764 return -1;
765
766 if (cur_len > split) {
767 cur_len = split;
768
769 /*
770 * TX will hang if DMA transfers <= 4 bytes,
771 * make sure next segment is more than 4 bytes long.
772 */
773 if (len <= split + 4)
774 cur_len -= 4;
775 }
776
777 desc->data = addr;
778 addr += cur_len;
779 len -= cur_len;
780
781 if (len > 0)
782 cur_len |= DESC_MORE;
783
784 /* prevent early tx attempt of this descriptor */
785 if (!ndesc)
786 cur_len |= DESC_EMPTY;
787
788 desc->ctrl = cur_len;
789 ndesc++;
790 }
791
792 return ndesc;
793 }
794
795 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
796 struct net_device *dev)
797 {
798 struct ag71xx *ag = netdev_priv(dev);
799 struct ag71xx_ring *ring = &ag->tx_ring;
800 int ring_mask = BIT(ring->order) - 1;
801 int ring_size = BIT(ring->order);
802 struct ag71xx_desc *desc;
803 dma_addr_t dma_addr;
804 int i, n, ring_min;
805
806 if (ag71xx_has_ar8216(ag))
807 ag71xx_add_ar8216_header(ag, skb);
808
809 if (skb->len <= 4) {
810 DBG("%s: packet len is too small\n", ag->dev->name);
811 goto err_drop;
812 }
813
814 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
815 DMA_TO_DEVICE);
816
817 i = ring->curr & ring_mask;
818 desc = ag71xx_ring_desc(ring, i);
819
820 /* setup descriptor fields */
821 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
822 if (n < 0)
823 goto err_drop_unmap;
824
825 i = (ring->curr + n - 1) & ring_mask;
826 ring->buf[i].len = skb->len;
827 ring->buf[i].skb = skb;
828 ring->buf[i].timestamp = jiffies;
829
830 netdev_sent_queue(dev, skb->len);
831
832 skb_tx_timestamp(skb);
833
834 desc->ctrl &= ~DESC_EMPTY;
835 ring->curr += n;
836
837 /* flush descriptor */
838 wmb();
839
840 ring_min = 2;
841 if (ring->desc_split)
842 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
843
844 if (ring->curr - ring->dirty >= ring_size - ring_min) {
845 DBG("%s: tx queue full\n", dev->name);
846 netif_stop_queue(dev);
847 }
848
849 DBG("%s: packet injected into TX queue\n", ag->dev->name);
850
851 /* enable TX engine */
852 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
853
854 return NETDEV_TX_OK;
855
856 err_drop_unmap:
857 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
858
859 err_drop:
860 dev->stats.tx_dropped++;
861
862 dev_kfree_skb(skb);
863 return NETDEV_TX_OK;
864 }
865
866 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
867 {
868 struct ag71xx *ag = netdev_priv(dev);
869 int ret;
870
871 switch (cmd) {
872 case SIOCETHTOOL:
873 if (ag->phy_dev == NULL)
874 break;
875
876 spin_lock_irq(&ag->lock);
877 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
878 spin_unlock_irq(&ag->lock);
879 return ret;
880
881 case SIOCSIFHWADDR:
882 if (copy_from_user
883 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
884 return -EFAULT;
885 return 0;
886
887 case SIOCGIFHWADDR:
888 if (copy_to_user
889 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
890 return -EFAULT;
891 return 0;
892
893 case SIOCGMIIPHY:
894 case SIOCGMIIREG:
895 case SIOCSMIIREG:
896 if (ag->phy_dev == NULL)
897 break;
898
899 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
900
901 default:
902 break;
903 }
904
905 return -EOPNOTSUPP;
906 }
907
908 static void ag71xx_oom_timer_handler(unsigned long data)
909 {
910 struct net_device *dev = (struct net_device *) data;
911 struct ag71xx *ag = netdev_priv(dev);
912
913 napi_schedule(&ag->napi);
914 }
915
916 static void ag71xx_tx_timeout(struct net_device *dev)
917 {
918 struct ag71xx *ag = netdev_priv(dev);
919
920 if (netif_msg_tx_err(ag))
921 pr_info("%s: tx timeout\n", ag->dev->name);
922
923 schedule_delayed_work(&ag->restart_work, 1);
924 }
925
926 static void ag71xx_restart_work_func(struct work_struct *work)
927 {
928 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
929
930 rtnl_lock();
931 ag71xx_hw_disable(ag);
932 ag71xx_hw_enable(ag);
933 if (ag->link)
934 __ag71xx_link_adjust(ag, false);
935 rtnl_unlock();
936 }
937
938 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
939 {
940 u32 rx_sm, tx_sm, rx_fd;
941
942 if (likely(time_before(jiffies, timestamp + HZ/10)))
943 return false;
944
945 if (!netif_carrier_ok(ag->dev))
946 return false;
947
948 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
949 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
950 return true;
951
952 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
953 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
954 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
955 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
956 return true;
957
958 return false;
959 }
960
961 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
962 {
963 struct ag71xx_ring *ring = &ag->tx_ring;
964 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
965 bool dma_stuck = false;
966 int ring_mask = BIT(ring->order) - 1;
967 int ring_size = BIT(ring->order);
968 int sent = 0;
969 int bytes_compl = 0;
970 int n = 0;
971
972 DBG("%s: processing TX ring\n", ag->dev->name);
973
974 while (ring->dirty + n != ring->curr) {
975 unsigned int i = (ring->dirty + n) & ring_mask;
976 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
977 struct sk_buff *skb = ring->buf[i].skb;
978
979 if (!flush && !ag71xx_desc_empty(desc)) {
980 if (pdata->is_ar724x &&
981 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) {
982 schedule_delayed_work(&ag->restart_work, HZ / 2);
983 dma_stuck = true;
984 }
985 break;
986 }
987
988 if (flush)
989 desc->ctrl |= DESC_EMPTY;
990
991 n++;
992 if (!skb)
993 continue;
994
995 dev_kfree_skb_any(skb);
996 ring->buf[i].skb = NULL;
997
998 bytes_compl += ring->buf[i].len;
999
1000 sent++;
1001 ring->dirty += n;
1002
1003 while (n > 0) {
1004 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1005 n--;
1006 }
1007 }
1008
1009 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1010
1011 ag->dev->stats.tx_bytes += bytes_compl;
1012 ag->dev->stats.tx_packets += sent;
1013
1014 if (!sent)
1015 return 0;
1016
1017 netdev_completed_queue(ag->dev, sent, bytes_compl);
1018 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1019 netif_wake_queue(ag->dev);
1020
1021 if (!dma_stuck)
1022 cancel_delayed_work(&ag->restart_work);
1023
1024 return sent;
1025 }
1026
1027 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1028 {
1029 struct net_device *dev = ag->dev;
1030 struct ag71xx_ring *ring = &ag->rx_ring;
1031 int offset = ag71xx_buffer_offset(ag);
1032 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1033 int ring_mask = BIT(ring->order) - 1;
1034 int ring_size = BIT(ring->order);
1035 struct sk_buff_head queue;
1036 struct sk_buff *skb;
1037 int done = 0;
1038
1039 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1040 dev->name, limit, ring->curr, ring->dirty);
1041
1042 skb_queue_head_init(&queue);
1043
1044 while (done < limit) {
1045 unsigned int i = ring->curr & ring_mask;
1046 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1047 int pktlen;
1048 int err = 0;
1049
1050 if (ag71xx_desc_empty(desc))
1051 break;
1052
1053 if ((ring->dirty + ring_size) == ring->curr) {
1054 ag71xx_assert(0);
1055 break;
1056 }
1057
1058 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1059
1060 pktlen = desc->ctrl & pktlen_mask;
1061 pktlen -= ETH_FCS_LEN;
1062
1063 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1064 ag->rx_buf_size, DMA_FROM_DEVICE);
1065
1066 dev->stats.rx_packets++;
1067 dev->stats.rx_bytes += pktlen;
1068
1069 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1070 if (!skb) {
1071 skb_free_frag(ring->buf[i].rx_buf);
1072 goto next;
1073 }
1074
1075 skb_reserve(skb, offset);
1076 skb_put(skb, pktlen);
1077
1078 if (ag71xx_has_ar8216(ag))
1079 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1080
1081 if (err) {
1082 dev->stats.rx_dropped++;
1083 kfree_skb(skb);
1084 } else {
1085 skb->dev = dev;
1086 skb->ip_summed = CHECKSUM_NONE;
1087 __skb_queue_tail(&queue, skb);
1088 }
1089
1090 next:
1091 ring->buf[i].rx_buf = NULL;
1092 done++;
1093
1094 ring->curr++;
1095 }
1096
1097 ag71xx_ring_rx_refill(ag);
1098
1099 while ((skb = __skb_dequeue(&queue)) != NULL) {
1100 skb->protocol = eth_type_trans(skb, dev);
1101 netif_receive_skb(skb);
1102 }
1103
1104 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1105 dev->name, ring->curr, ring->dirty, done);
1106
1107 return done;
1108 }
1109
1110 static int ag71xx_poll(struct napi_struct *napi, int limit)
1111 {
1112 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1113 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1114 struct net_device *dev = ag->dev;
1115 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1116 int rx_ring_size = BIT(rx_ring->order);
1117 unsigned long flags;
1118 u32 status;
1119 int tx_done;
1120 int rx_done;
1121
1122 pdata->ddr_flush();
1123 tx_done = ag71xx_tx_packets(ag, false);
1124
1125 DBG("%s: processing RX ring\n", dev->name);
1126 rx_done = ag71xx_rx_packets(ag, limit);
1127
1128 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1129
1130 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1131 goto oom;
1132
1133 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1134 if (unlikely(status & RX_STATUS_OF)) {
1135 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1136 dev->stats.rx_fifo_errors++;
1137
1138 /* restart RX */
1139 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1140 }
1141
1142 if (rx_done < limit) {
1143 if (status & RX_STATUS_PR)
1144 goto more;
1145
1146 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1147 if (status & TX_STATUS_PS)
1148 goto more;
1149
1150 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1151 dev->name, rx_done, tx_done, limit);
1152
1153 napi_complete(napi);
1154
1155 /* enable interrupts */
1156 spin_lock_irqsave(&ag->lock, flags);
1157 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1158 spin_unlock_irqrestore(&ag->lock, flags);
1159 return rx_done;
1160 }
1161
1162 more:
1163 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1164 dev->name, rx_done, tx_done, limit);
1165 return limit;
1166
1167 oom:
1168 if (netif_msg_rx_err(ag))
1169 pr_info("%s: out of memory\n", dev->name);
1170
1171 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1172 napi_complete(napi);
1173 return 0;
1174 }
1175
1176 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1177 {
1178 struct net_device *dev = dev_id;
1179 struct ag71xx *ag = netdev_priv(dev);
1180 u32 status;
1181
1182 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1183 ag71xx_dump_intr(ag, "raw", status);
1184
1185 if (unlikely(!status))
1186 return IRQ_NONE;
1187
1188 if (unlikely(status & AG71XX_INT_ERR)) {
1189 if (status & AG71XX_INT_TX_BE) {
1190 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1191 dev_err(&dev->dev, "TX BUS error\n");
1192 }
1193 if (status & AG71XX_INT_RX_BE) {
1194 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1195 dev_err(&dev->dev, "RX BUS error\n");
1196 }
1197 }
1198
1199 if (likely(status & AG71XX_INT_POLL)) {
1200 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1201 DBG("%s: enable polling mode\n", dev->name);
1202 napi_schedule(&ag->napi);
1203 }
1204
1205 ag71xx_debugfs_update_int_stats(ag, status);
1206
1207 return IRQ_HANDLED;
1208 }
1209
1210 #ifdef CONFIG_NET_POLL_CONTROLLER
1211 /*
1212 * Polling 'interrupt' - used by things like netconsole to send skbs
1213 * without having to re-enable interrupts. It's not called while
1214 * the interrupt routine is executing.
1215 */
1216 static void ag71xx_netpoll(struct net_device *dev)
1217 {
1218 disable_irq(dev->irq);
1219 ag71xx_interrupt(dev->irq, dev);
1220 enable_irq(dev->irq);
1221 }
1222 #endif
1223
1224 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1225 {
1226 struct ag71xx *ag = netdev_priv(dev);
1227 unsigned int max_frame_len;
1228
1229 max_frame_len = ag71xx_max_frame_len(new_mtu);
1230 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1231 return -EINVAL;
1232
1233 if (netif_running(dev))
1234 return -EBUSY;
1235
1236 dev->mtu = new_mtu;
1237 return 0;
1238 }
1239
1240 static const struct net_device_ops ag71xx_netdev_ops = {
1241 .ndo_open = ag71xx_open,
1242 .ndo_stop = ag71xx_stop,
1243 .ndo_start_xmit = ag71xx_hard_start_xmit,
1244 .ndo_do_ioctl = ag71xx_do_ioctl,
1245 .ndo_tx_timeout = ag71xx_tx_timeout,
1246 .ndo_change_mtu = ag71xx_change_mtu,
1247 .ndo_set_mac_address = eth_mac_addr,
1248 .ndo_validate_addr = eth_validate_addr,
1249 #ifdef CONFIG_NET_POLL_CONTROLLER
1250 .ndo_poll_controller = ag71xx_netpoll,
1251 #endif
1252 };
1253
1254 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1255 {
1256 switch (mode) {
1257 case PHY_INTERFACE_MODE_MII:
1258 return "MII";
1259 case PHY_INTERFACE_MODE_GMII:
1260 return "GMII";
1261 case PHY_INTERFACE_MODE_RMII:
1262 return "RMII";
1263 case PHY_INTERFACE_MODE_RGMII:
1264 return "RGMII";
1265 case PHY_INTERFACE_MODE_SGMII:
1266 return "SGMII";
1267 default:
1268 break;
1269 }
1270
1271 return "unknown";
1272 }
1273
1274
1275 static int ag71xx_probe(struct platform_device *pdev)
1276 {
1277 struct net_device *dev;
1278 struct resource *res;
1279 struct ag71xx *ag;
1280 struct ag71xx_platform_data *pdata;
1281 int tx_size, err;
1282
1283 pdata = pdev->dev.platform_data;
1284 if (!pdata) {
1285 dev_err(&pdev->dev, "no platform data specified\n");
1286 err = -ENXIO;
1287 goto err_out;
1288 }
1289
1290 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1291 dev_err(&pdev->dev, "no MII bus device specified\n");
1292 err = -EINVAL;
1293 goto err_out;
1294 }
1295
1296 dev = alloc_etherdev(sizeof(*ag));
1297 if (!dev) {
1298 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1299 err = -ENOMEM;
1300 goto err_out;
1301 }
1302
1303 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1304 return -EINVAL;
1305
1306 SET_NETDEV_DEV(dev, &pdev->dev);
1307
1308 ag = netdev_priv(dev);
1309 ag->pdev = pdev;
1310 ag->dev = dev;
1311 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1312 AG71XX_DEFAULT_MSG_ENABLE);
1313 spin_lock_init(&ag->lock);
1314
1315 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1316 if (!res) {
1317 dev_err(&pdev->dev, "no mac_base resource found\n");
1318 err = -ENXIO;
1319 goto err_out;
1320 }
1321
1322 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1323 if (!ag->mac_base) {
1324 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1325 err = -ENOMEM;
1326 goto err_free_dev;
1327 }
1328
1329 dev->irq = platform_get_irq(pdev, 0);
1330 err = request_irq(dev->irq, ag71xx_interrupt,
1331 0x0,
1332 dev->name, dev);
1333 if (err) {
1334 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1335 goto err_unmap_base;
1336 }
1337
1338 dev->base_addr = (unsigned long)ag->mac_base;
1339 dev->netdev_ops = &ag71xx_netdev_ops;
1340 dev->ethtool_ops = &ag71xx_ethtool_ops;
1341
1342 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1343
1344 init_timer(&ag->oom_timer);
1345 ag->oom_timer.data = (unsigned long) dev;
1346 ag->oom_timer.function = ag71xx_oom_timer_handler;
1347
1348 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1349 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1350
1351 ag->max_frame_len = pdata->max_frame_len;
1352 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1353
1354 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1355 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1356 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1357 }
1358 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1359
1360 ag->stop_desc = dma_alloc_coherent(NULL,
1361 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1362
1363 if (!ag->stop_desc)
1364 goto err_free_irq;
1365
1366 ag->stop_desc->data = 0;
1367 ag->stop_desc->ctrl = 0;
1368 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1369
1370 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1371
1372 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1373
1374 ag71xx_dump_regs(ag);
1375
1376 ag71xx_hw_init(ag);
1377
1378 ag71xx_dump_regs(ag);
1379
1380 err = ag71xx_phy_connect(ag);
1381 if (err)
1382 goto err_free_desc;
1383
1384 err = ag71xx_debugfs_init(ag);
1385 if (err)
1386 goto err_phy_disconnect;
1387
1388 platform_set_drvdata(pdev, dev);
1389
1390 err = register_netdev(dev);
1391 if (err) {
1392 dev_err(&pdev->dev, "unable to register net device\n");
1393 goto err_debugfs_exit;
1394 }
1395
1396 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1397 dev->name, dev->base_addr, dev->irq,
1398 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1399
1400 return 0;
1401
1402 err_debugfs_exit:
1403 ag71xx_debugfs_exit(ag);
1404 err_phy_disconnect:
1405 ag71xx_phy_disconnect(ag);
1406 err_free_desc:
1407 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1408 ag->stop_desc_dma);
1409 err_free_irq:
1410 free_irq(dev->irq, dev);
1411 err_unmap_base:
1412 iounmap(ag->mac_base);
1413 err_free_dev:
1414 kfree(dev);
1415 err_out:
1416 platform_set_drvdata(pdev, NULL);
1417 return err;
1418 }
1419
1420 static int ag71xx_remove(struct platform_device *pdev)
1421 {
1422 struct net_device *dev = platform_get_drvdata(pdev);
1423
1424 if (dev) {
1425 struct ag71xx *ag = netdev_priv(dev);
1426
1427 ag71xx_debugfs_exit(ag);
1428 ag71xx_phy_disconnect(ag);
1429 unregister_netdev(dev);
1430 free_irq(dev->irq, dev);
1431 iounmap(ag->mac_base);
1432 kfree(dev);
1433 platform_set_drvdata(pdev, NULL);
1434 }
1435
1436 return 0;
1437 }
1438
1439 static struct platform_driver ag71xx_driver = {
1440 .probe = ag71xx_probe,
1441 .remove = ag71xx_remove,
1442 .driver = {
1443 .name = AG71XX_DRV_NAME,
1444 }
1445 };
1446
1447 static int __init ag71xx_module_init(void)
1448 {
1449 int ret;
1450
1451 ret = ag71xx_debugfs_root_init();
1452 if (ret)
1453 goto err_out;
1454
1455 ret = ag71xx_mdio_driver_init();
1456 if (ret)
1457 goto err_debugfs_exit;
1458
1459 ret = platform_driver_register(&ag71xx_driver);
1460 if (ret)
1461 goto err_mdio_exit;
1462
1463 return 0;
1464
1465 err_mdio_exit:
1466 ag71xx_mdio_driver_exit();
1467 err_debugfs_exit:
1468 ag71xx_debugfs_root_exit();
1469 err_out:
1470 return ret;
1471 }
1472
1473 static void __exit ag71xx_module_exit(void)
1474 {
1475 platform_driver_unregister(&ag71xx_driver);
1476 ag71xx_mdio_driver_exit();
1477 ag71xx_debugfs_root_exit();
1478 }
1479
1480 module_init(ag71xx_module_init);
1481 module_exit(ag71xx_module_exit);
1482
1483 MODULE_VERSION(AG71XX_DRV_VERSION);
1484 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1485 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1486 MODULE_LICENSE("GPL v2");
1487 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);