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wireguard-tools: add tunlink option for hostroute
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define ETH_SWITCH_HEADER_LEN 2
32
33 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
34 static void ag71xx_qca955x_sgmii_init(void);
35
36 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
37 {
38 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
39 }
40
41 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
42 {
43 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
44 ag->dev->name,
45 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
46 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
47 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
48
49 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
52 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
53 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
54 }
55
56 static void ag71xx_dump_regs(struct ag71xx *ag)
57 {
58 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
59 ag->dev->name,
60 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
61 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
62 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
63 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
64 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
65 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
68 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
69 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
70 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
71 ag->dev->name,
72 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
73 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
75 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
76 ag->dev->name,
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
79 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
80 }
81
82 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
83 {
84 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
85 ag->dev->name, label, intr,
86 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
87 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
88 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
89 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
90 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
91 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
92 }
93
94 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
95 {
96 struct ag71xx_ring *ring = &ag->tx_ring;
97 struct net_device *dev = ag->dev;
98 int ring_mask = BIT(ring->order) - 1;
99 u32 bytes_compl = 0, pkts_compl = 0;
100
101 while (ring->curr != ring->dirty) {
102 struct ag71xx_desc *desc;
103 u32 i = ring->dirty & ring_mask;
104
105 desc = ag71xx_ring_desc(ring, i);
106 if (!ag71xx_desc_empty(desc)) {
107 desc->ctrl = 0;
108 dev->stats.tx_errors++;
109 }
110
111 if (ring->buf[i].skb) {
112 bytes_compl += ring->buf[i].len;
113 pkts_compl++;
114 dev_kfree_skb_any(ring->buf[i].skb);
115 }
116 ring->buf[i].skb = NULL;
117 ring->dirty++;
118 }
119
120 /* flush descriptors */
121 wmb();
122
123 netdev_completed_queue(dev, pkts_compl, bytes_compl);
124 }
125
126 static void ag71xx_ring_tx_init(struct ag71xx *ag)
127 {
128 struct ag71xx_ring *ring = &ag->tx_ring;
129 int ring_size = BIT(ring->order);
130 int ring_mask = BIT(ring->order) - 1;
131 int i;
132
133 for (i = 0; i < ring_size; i++) {
134 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
135
136 desc->next = (u32) (ring->descs_dma +
137 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
138
139 desc->ctrl = DESC_EMPTY;
140 ring->buf[i].skb = NULL;
141 }
142
143 /* flush descriptors */
144 wmb();
145
146 ring->curr = 0;
147 ring->dirty = 0;
148 netdev_reset_queue(ag->dev);
149 }
150
151 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
152 {
153 struct ag71xx_ring *ring = &ag->rx_ring;
154 int ring_size = BIT(ring->order);
155 int i;
156
157 if (!ring->buf)
158 return;
159
160 for (i = 0; i < ring_size; i++)
161 if (ring->buf[i].rx_buf) {
162 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
163 ag->rx_buf_size, DMA_FROM_DEVICE);
164 skb_free_frag(ring->buf[i].rx_buf);
165 }
166 }
167
168 static int ag71xx_buffer_offset(struct ag71xx *ag)
169 {
170 int offset = NET_SKB_PAD;
171
172 /*
173 * On AR71xx/AR91xx packets must be 4-byte aligned.
174 *
175 * When using builtin AR8216 support, hardware adds a 2-byte header,
176 * so we don't need any extra alignment in that case.
177 */
178 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
179 return offset;
180
181 return offset + NET_IP_ALIGN;
182 }
183
184 static int ag71xx_buffer_size(struct ag71xx *ag)
185 {
186 return ag->rx_buf_size +
187 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
188 }
189
190 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
191 int offset,
192 void *(*alloc)(unsigned int size))
193 {
194 struct ag71xx_ring *ring = &ag->rx_ring;
195 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
196 void *data;
197
198 data = alloc(ag71xx_buffer_size(ag));
199 if (!data)
200 return false;
201
202 buf->rx_buf = data;
203 buf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
204 DMA_FROM_DEVICE);
205 desc->data = (u32) buf->dma_addr + offset;
206 return true;
207 }
208
209 static int ag71xx_ring_rx_init(struct ag71xx *ag)
210 {
211 struct ag71xx_ring *ring = &ag->rx_ring;
212 int ring_size = BIT(ring->order);
213 int ring_mask = BIT(ring->order) - 1;
214 unsigned int i;
215 int ret;
216 int offset = ag71xx_buffer_offset(ag);
217
218 ret = 0;
219 for (i = 0; i < ring_size; i++) {
220 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
221
222 desc->next = (u32) (ring->descs_dma +
223 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 desc, desc->next);
227 }
228
229 for (i = 0; i < ring_size; i++) {
230 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
231
232 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
233 netdev_alloc_frag)) {
234 ret = -ENOMEM;
235 break;
236 }
237
238 desc->ctrl = DESC_EMPTY;
239 }
240
241 /* flush descriptors */
242 wmb();
243
244 ring->curr = 0;
245 ring->dirty = 0;
246
247 return ret;
248 }
249
250 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
251 {
252 struct ag71xx_ring *ring = &ag->rx_ring;
253 int ring_mask = BIT(ring->order) - 1;
254 unsigned int count;
255 int offset = ag71xx_buffer_offset(ag);
256
257 count = 0;
258 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
259 struct ag71xx_desc *desc;
260 unsigned int i;
261
262 i = ring->dirty & ring_mask;
263 desc = ag71xx_ring_desc(ring, i);
264
265 if (!ring->buf[i].rx_buf &&
266 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
267 napi_alloc_frag))
268 break;
269
270 desc->ctrl = DESC_EMPTY;
271 count++;
272 }
273
274 /* flush descriptors */
275 wmb();
276
277 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
278
279 return count;
280 }
281
282 static int ag71xx_rings_init(struct ag71xx *ag)
283 {
284 struct ag71xx_ring *tx = &ag->tx_ring;
285 struct ag71xx_ring *rx = &ag->rx_ring;
286 int ring_size = BIT(tx->order) + BIT(rx->order);
287 int tx_size = BIT(tx->order);
288
289 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
290 if (!tx->buf)
291 return -ENOMEM;
292
293 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
294 &tx->descs_dma, GFP_KERNEL);
295 if (!tx->descs_cpu) {
296 kfree(tx->buf);
297 tx->buf = NULL;
298 return -ENOMEM;
299 }
300
301 rx->buf = &tx->buf[tx_size];
302 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
303 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
304
305 ag71xx_ring_tx_init(ag);
306 return ag71xx_ring_rx_init(ag);
307 }
308
309 static void ag71xx_rings_free(struct ag71xx *ag)
310 {
311 struct ag71xx_ring *tx = &ag->tx_ring;
312 struct ag71xx_ring *rx = &ag->rx_ring;
313 int ring_size = BIT(tx->order) + BIT(rx->order);
314
315 if (tx->descs_cpu)
316 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
317 tx->descs_cpu, tx->descs_dma);
318
319 kfree(tx->buf);
320
321 tx->descs_cpu = NULL;
322 rx->descs_cpu = NULL;
323 tx->buf = NULL;
324 rx->buf = NULL;
325 }
326
327 static void ag71xx_rings_cleanup(struct ag71xx *ag)
328 {
329 ag71xx_ring_rx_clean(ag);
330 ag71xx_ring_tx_clean(ag);
331 ag71xx_rings_free(ag);
332
333 netdev_reset_queue(ag->dev);
334 }
335
336 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
337 {
338 switch (ag->speed) {
339 case SPEED_1000:
340 return "1000";
341 case SPEED_100:
342 return "100";
343 case SPEED_10:
344 return "10";
345 }
346
347 return "?";
348 }
349
350 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
351 {
352 u32 t;
353
354 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
355 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
356
357 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
358
359 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
360 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
361 }
362
363 static void ag71xx_dma_reset(struct ag71xx *ag)
364 {
365 u32 val;
366 int i;
367
368 ag71xx_dump_dma_regs(ag);
369
370 /* stop RX and TX */
371 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
372 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
373
374 /*
375 * give the hardware some time to really stop all rx/tx activity
376 * clearing the descriptors too early causes random memory corruption
377 */
378 mdelay(1);
379
380 /* clear descriptor addresses */
381 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
382 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
383
384 /* clear pending RX/TX interrupts */
385 for (i = 0; i < 256; i++) {
386 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
387 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
388 }
389
390 /* clear pending errors */
391 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
392 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
393
394 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
395 if (val)
396 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
397 ag->dev->name, val);
398
399 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
400
401 /* mask out reserved bits */
402 val &= ~0xff000000;
403
404 if (val)
405 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
406 ag->dev->name, val);
407
408 ag71xx_dump_dma_regs(ag);
409 }
410
411 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
412 MAC_CFG1_SRX | MAC_CFG1_STX)
413
414 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
415
416 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
417 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
418 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
419 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
420 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
421 FIFO_CFG4_VT)
422
423 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
424 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
425 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
426 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
427 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
428 FIFO_CFG5_17 | FIFO_CFG5_SF)
429
430 static void ag71xx_hw_stop(struct ag71xx *ag)
431 {
432 /* disable all interrupts and stop the rx/tx engine */
433 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
434 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
435 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
436 }
437
438 static void ag71xx_hw_setup(struct ag71xx *ag)
439 {
440 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
441 u32 init = MAC_CFG1_INIT;
442
443 /* setup MAC configuration registers */
444 if (pdata->use_flow_control)
445 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
446 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
447
448 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
449 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
450
451 /* setup max frame length to zero */
452 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
453
454 /* setup FIFO configuration registers */
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
456 if (pdata->is_ar724x) {
457 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0010ffff);
458 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x015500aa);
459 } else {
460 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
461 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
462 }
463 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
464 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
465 }
466
467 static void ag71xx_hw_init(struct ag71xx *ag)
468 {
469 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
470 u32 reset_mask = pdata->reset_bit;
471
472 ag71xx_hw_stop(ag);
473
474 if (pdata->is_ar724x) {
475 u32 reset_phy = reset_mask;
476
477 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
478 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
479
480 ath79_device_reset_set(reset_phy);
481 msleep(50);
482 ath79_device_reset_clear(reset_phy);
483 msleep(200);
484 }
485
486 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
487 udelay(20);
488
489 ath79_device_reset_set(reset_mask);
490 msleep(100);
491 ath79_device_reset_clear(reset_mask);
492 msleep(200);
493
494 ag71xx_hw_setup(ag);
495
496 ag71xx_dma_reset(ag);
497 }
498
499 static void ag71xx_fast_reset(struct ag71xx *ag)
500 {
501 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
502 struct net_device *dev = ag->dev;
503 u32 reset_mask = pdata->reset_bit;
504 u32 rx_ds;
505 u32 mii_reg;
506
507 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
508
509 ag71xx_hw_stop(ag);
510 wmb();
511
512 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
513 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
514
515 ag71xx_tx_packets(ag, true);
516
517 ath79_device_reset_set(reset_mask);
518 udelay(10);
519 ath79_device_reset_clear(reset_mask);
520 udelay(10);
521
522 ag71xx_dma_reset(ag);
523 ag71xx_hw_setup(ag);
524 ag->tx_ring.curr = 0;
525 ag->tx_ring.dirty = 0;
526 netdev_reset_queue(ag->dev);
527
528 /* setup max frame length */
529 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
530 ag71xx_max_frame_len(ag->dev->mtu));
531
532 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
533 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
534 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
535
536 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
537 }
538
539 static void ag71xx_hw_start(struct ag71xx *ag)
540 {
541 /* start RX engine */
542 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
543
544 /* enable interrupts */
545 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
546
547 netif_wake_queue(ag->dev);
548 }
549
550 static void
551 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
552 {
553 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
554 u32 cfg2;
555 u32 ifctl;
556 u32 fifo5;
557 u32 fifo3;
558
559 if (!ag->link && update) {
560 ag71xx_hw_stop(ag);
561 netif_carrier_off(ag->dev);
562 if (netif_msg_link(ag))
563 pr_info("%s: link down\n", ag->dev->name);
564 return;
565 }
566
567 if (pdata->is_ar724x)
568 ag71xx_fast_reset(ag);
569
570 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
571 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
572 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
573
574 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
575 ifctl &= ~(MAC_IFCTL_SPEED);
576
577 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
578 fifo5 &= ~FIFO_CFG5_BM;
579
580 switch (ag->speed) {
581 case SPEED_1000:
582 cfg2 |= MAC_CFG2_IF_1000;
583 fifo5 |= FIFO_CFG5_BM;
584 break;
585 case SPEED_100:
586 cfg2 |= MAC_CFG2_IF_10_100;
587 ifctl |= MAC_IFCTL_SPEED;
588 break;
589 case SPEED_10:
590 cfg2 |= MAC_CFG2_IF_10_100;
591 break;
592 default:
593 BUG();
594 return;
595 }
596
597 if (pdata->is_ar91xx)
598 fifo3 = 0x00780fff;
599 else if (pdata->is_ar724x)
600 fifo3 = 0x01f00140;
601 else
602 fifo3 = 0x008001ff;
603
604 if (ag->tx_ring.desc_split) {
605 fifo3 &= 0xffff;
606 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
607 }
608
609 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
610
611 if (update && pdata->set_speed)
612 pdata->set_speed(ag->speed);
613
614 if (update && pdata->enable_sgmii_fixup)
615 ag71xx_qca955x_sgmii_init();
616
617 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
618 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
619 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
620
621 if (pdata->disable_inline_checksum_engine) {
622 /*
623 * The rx ring buffer can stall on small packets on QCA953x and
624 * QCA956x. Disabling the inline checksum engine fixes the stall.
625 * The wr, rr functions cannot be used since this hidden register
626 * is outside of the normal ag71xx register block.
627 */
628 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
629 if (dam) {
630 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
631 (void)__raw_readl(dam);
632 iounmap(dam);
633 }
634 }
635
636 ag71xx_hw_start(ag);
637
638 netif_carrier_on(ag->dev);
639 if (update && netif_msg_link(ag))
640 pr_info("%s: link up (%sMbps/%s duplex)\n",
641 ag->dev->name,
642 ag71xx_speed_str(ag),
643 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
644
645 ag71xx_dump_regs(ag);
646 }
647
648 void ag71xx_link_adjust(struct ag71xx *ag)
649 {
650 __ag71xx_link_adjust(ag, true);
651 }
652
653 static int ag71xx_hw_enable(struct ag71xx *ag)
654 {
655 int ret;
656
657 ret = ag71xx_rings_init(ag);
658 if (ret)
659 return ret;
660
661 napi_enable(&ag->napi);
662 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
663 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
664 netif_start_queue(ag->dev);
665
666 return 0;
667 }
668
669 static void ag71xx_hw_disable(struct ag71xx *ag)
670 {
671 netif_stop_queue(ag->dev);
672
673 ag71xx_hw_stop(ag);
674 ag71xx_dma_reset(ag);
675
676 napi_disable(&ag->napi);
677 del_timer_sync(&ag->oom_timer);
678
679 ag71xx_rings_cleanup(ag);
680 }
681
682 static int ag71xx_open(struct net_device *dev)
683 {
684 struct ag71xx *ag = netdev_priv(dev);
685 unsigned int max_frame_len;
686 int ret;
687
688 netif_carrier_off(dev);
689 max_frame_len = ag71xx_max_frame_len(dev->mtu);
690 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
691
692 /* setup max frame length */
693 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
694 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
695
696 ret = ag71xx_hw_enable(ag);
697 if (ret)
698 goto err;
699
700 ag71xx_phy_start(ag);
701
702 return 0;
703
704 err:
705 ag71xx_rings_cleanup(ag);
706 return ret;
707 }
708
709 static int ag71xx_stop(struct net_device *dev)
710 {
711 struct ag71xx *ag = netdev_priv(dev);
712
713 netif_carrier_off(dev);
714 ag71xx_phy_stop(ag);
715 ag71xx_hw_disable(ag);
716
717 return 0;
718 }
719
720 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
721 {
722 int i;
723 struct ag71xx_desc *desc;
724 int ring_mask = BIT(ring->order) - 1;
725 int ndesc = 0;
726 int split = ring->desc_split;
727
728 if (!split)
729 split = len;
730
731 while (len > 0) {
732 unsigned int cur_len = len;
733
734 i = (ring->curr + ndesc) & ring_mask;
735 desc = ag71xx_ring_desc(ring, i);
736
737 if (!ag71xx_desc_empty(desc))
738 return -1;
739
740 if (cur_len > split) {
741 cur_len = split;
742
743 /*
744 * TX will hang if DMA transfers <= 4 bytes,
745 * make sure next segment is more than 4 bytes long.
746 */
747 if (len <= split + 4)
748 cur_len -= 4;
749 }
750
751 desc->data = addr;
752 addr += cur_len;
753 len -= cur_len;
754
755 if (len > 0)
756 cur_len |= DESC_MORE;
757
758 /* prevent early tx attempt of this descriptor */
759 if (!ndesc)
760 cur_len |= DESC_EMPTY;
761
762 desc->ctrl = cur_len;
763 ndesc++;
764 }
765
766 return ndesc;
767 }
768
769 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
770 struct net_device *dev)
771 {
772 struct ag71xx *ag = netdev_priv(dev);
773 struct ag71xx_ring *ring = &ag->tx_ring;
774 int ring_mask = BIT(ring->order) - 1;
775 int ring_size = BIT(ring->order);
776 struct ag71xx_desc *desc;
777 dma_addr_t dma_addr;
778 int i, n, ring_min;
779
780 if (ag71xx_has_ar8216(ag))
781 ag71xx_add_ar8216_header(ag, skb);
782
783 if (skb->len <= 4) {
784 DBG("%s: packet len is too small\n", ag->dev->name);
785 goto err_drop;
786 }
787
788 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
789 DMA_TO_DEVICE);
790
791 i = ring->curr & ring_mask;
792 desc = ag71xx_ring_desc(ring, i);
793
794 /* setup descriptor fields */
795 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
796 if (n < 0)
797 goto err_drop_unmap;
798
799 i = (ring->curr + n - 1) & ring_mask;
800 ring->buf[i].len = skb->len;
801 ring->buf[i].skb = skb;
802
803 netdev_sent_queue(dev, skb->len);
804
805 skb_tx_timestamp(skb);
806
807 desc->ctrl &= ~DESC_EMPTY;
808 ring->curr += n;
809
810 /* flush descriptor */
811 wmb();
812
813 ring_min = 2;
814 if (ring->desc_split)
815 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
816
817 if (ring->curr - ring->dirty >= ring_size - ring_min) {
818 DBG("%s: tx queue full\n", dev->name);
819 netif_stop_queue(dev);
820 }
821
822 DBG("%s: packet injected into TX queue\n", ag->dev->name);
823
824 /* enable TX engine */
825 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
826
827 return NETDEV_TX_OK;
828
829 err_drop_unmap:
830 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
831
832 err_drop:
833 dev->stats.tx_dropped++;
834
835 dev_kfree_skb(skb);
836 return NETDEV_TX_OK;
837 }
838
839 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
840 {
841 struct ag71xx *ag = netdev_priv(dev);
842
843 switch (cmd) {
844 case SIOCSIFHWADDR:
845 if (copy_from_user
846 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
847 return -EFAULT;
848 return 0;
849
850 case SIOCGIFHWADDR:
851 if (copy_to_user
852 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
853 return -EFAULT;
854 return 0;
855
856 case SIOCGMIIPHY:
857 case SIOCGMIIREG:
858 case SIOCSMIIREG:
859 if (ag->phy_dev == NULL)
860 break;
861
862 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
863
864 default:
865 break;
866 }
867
868 return -EOPNOTSUPP;
869 }
870
871 static void ag71xx_oom_timer_handler(unsigned long data)
872 {
873 struct net_device *dev = (struct net_device *) data;
874 struct ag71xx *ag = netdev_priv(dev);
875
876 napi_schedule(&ag->napi);
877 }
878
879 static void ag71xx_tx_timeout(struct net_device *dev)
880 {
881 struct ag71xx *ag = netdev_priv(dev);
882
883 if (netif_msg_tx_err(ag))
884 pr_info("%s: tx timeout\n", ag->dev->name);
885
886 schedule_delayed_work(&ag->restart_work, 1);
887 }
888
889 static void ag71xx_bit_set(void __iomem *reg, u32 bit)
890 {
891 u32 val = __raw_readl(reg) | bit;
892 __raw_writel(val, reg);
893 __raw_readl(reg);
894 }
895
896 static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
897 {
898 u32 val = __raw_readl(reg) & ~bit;
899 __raw_writel(val, reg);
900 __raw_readl(reg);
901 }
902
903 static void ag71xx_qca955x_sgmii_init()
904 {
905 void __iomem *gmac_base;
906 u32 mr_an_status, sgmii_status;
907 u8 tries = 0;
908
909 gmac_base = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
910
911 if (!gmac_base)
912 goto sgmii_out;
913
914 mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
915 if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
916 goto sgmii_out;
917
918 __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET ,
919 gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
920 __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
921 udelay(10);
922
923 /* Init sequence */
924 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
925 QCA955X_SGMII_RESET_HW_RX_125M_N);
926 udelay(10);
927
928 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
929 QCA955X_SGMII_RESET_RX_125M_N);
930 udelay(10);
931
932 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
933 QCA955X_SGMII_RESET_TX_125M_N);
934 udelay(10);
935
936 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
937 QCA955X_SGMII_RESET_RX_CLK_N);
938 udelay(10);
939
940 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
941 QCA955X_SGMII_RESET_TX_CLK_N);
942 udelay(10);
943
944 do {
945 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
946 QCA955X_MR_AN_CONTROL_PHY_RESET |
947 QCA955X_MR_AN_CONTROL_AN_ENABLE);
948 udelay(100);
949 ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
950 QCA955X_MR_AN_CONTROL_PHY_RESET);
951 mdelay(10);
952 sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) & 0xF;
953
954 if (tries++ >= QCA955X_SGMII_LINK_WAR_MAX_TRY) {
955 pr_warn("ag71xx: max retries for SGMII fixup exceeded!\n");
956 break;
957 }
958 } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
959
960 sgmii_out:
961 iounmap(gmac_base);
962 }
963
964 static void ag71xx_restart_work_func(struct work_struct *work)
965 {
966 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
967
968 rtnl_lock();
969 ag71xx_hw_disable(ag);
970 ag71xx_hw_enable(ag);
971 if (ag->link)
972 __ag71xx_link_adjust(ag, false);
973 rtnl_unlock();
974 }
975
976 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
977 {
978 unsigned long timestamp;
979 u32 rx_sm, tx_sm, rx_fd;
980
981 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
982 if (likely(time_before(jiffies, timestamp + HZ/10)))
983 return false;
984
985 if (!netif_carrier_ok(ag->dev))
986 return false;
987
988 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
989 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
990 return true;
991
992 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
993 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
994 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
995 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
996 return true;
997
998 return false;
999 }
1000
1001 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1002 {
1003 struct ag71xx_ring *ring = &ag->tx_ring;
1004 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1005 bool dma_stuck = false;
1006 int ring_mask = BIT(ring->order) - 1;
1007 int ring_size = BIT(ring->order);
1008 int sent = 0;
1009 int bytes_compl = 0;
1010 int n = 0;
1011
1012 DBG("%s: processing TX ring\n", ag->dev->name);
1013
1014 while (ring->dirty + n != ring->curr) {
1015 unsigned int i = (ring->dirty + n) & ring_mask;
1016 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1017 struct sk_buff *skb = ring->buf[i].skb;
1018
1019 if (!flush && !ag71xx_desc_empty(desc)) {
1020 if (pdata->is_ar724x &&
1021 ag71xx_check_dma_stuck(ag)) {
1022 schedule_delayed_work(&ag->restart_work, HZ / 2);
1023 dma_stuck = true;
1024 }
1025 break;
1026 }
1027
1028 if (flush)
1029 desc->ctrl |= DESC_EMPTY;
1030
1031 n++;
1032 if (!skb)
1033 continue;
1034
1035 dev_kfree_skb_any(skb);
1036 ring->buf[i].skb = NULL;
1037
1038 bytes_compl += ring->buf[i].len;
1039
1040 sent++;
1041 ring->dirty += n;
1042
1043 while (n > 0) {
1044 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1045 n--;
1046 }
1047 }
1048
1049 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1050
1051 if (!sent)
1052 return 0;
1053
1054 ag->dev->stats.tx_bytes += bytes_compl;
1055 ag->dev->stats.tx_packets += sent;
1056
1057 netdev_completed_queue(ag->dev, sent, bytes_compl);
1058 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1059 netif_wake_queue(ag->dev);
1060
1061 if (!dma_stuck)
1062 cancel_delayed_work(&ag->restart_work);
1063
1064 return sent;
1065 }
1066
1067 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1068 {
1069 struct net_device *dev = ag->dev;
1070 struct ag71xx_ring *ring = &ag->rx_ring;
1071 int offset = ag71xx_buffer_offset(ag);
1072 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1073 int ring_mask = BIT(ring->order) - 1;
1074 int ring_size = BIT(ring->order);
1075 struct sk_buff_head queue;
1076 struct sk_buff *skb;
1077 int done = 0;
1078
1079 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1080 dev->name, limit, ring->curr, ring->dirty);
1081
1082 skb_queue_head_init(&queue);
1083
1084 while (done < limit) {
1085 unsigned int i = ring->curr & ring_mask;
1086 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1087 int pktlen;
1088 int err = 0;
1089
1090 if (ag71xx_desc_empty(desc))
1091 break;
1092
1093 if ((ring->dirty + ring_size) == ring->curr) {
1094 ag71xx_assert(0);
1095 break;
1096 }
1097
1098 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1099
1100 pktlen = desc->ctrl & pktlen_mask;
1101 pktlen -= ETH_FCS_LEN;
1102
1103 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
1104 ag->rx_buf_size, DMA_FROM_DEVICE);
1105
1106 dev->stats.rx_packets++;
1107 dev->stats.rx_bytes += pktlen;
1108
1109 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1110 if (!skb) {
1111 skb_free_frag(ring->buf[i].rx_buf);
1112 goto next;
1113 }
1114
1115 skb_reserve(skb, offset);
1116 skb_put(skb, pktlen);
1117
1118 if (ag71xx_has_ar8216(ag))
1119 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1120
1121 if (err) {
1122 dev->stats.rx_dropped++;
1123 kfree_skb(skb);
1124 } else {
1125 skb->dev = dev;
1126 skb->ip_summed = CHECKSUM_NONE;
1127 __skb_queue_tail(&queue, skb);
1128 }
1129
1130 next:
1131 ring->buf[i].rx_buf = NULL;
1132 done++;
1133
1134 ring->curr++;
1135 }
1136
1137 ag71xx_ring_rx_refill(ag);
1138
1139 while ((skb = __skb_dequeue(&queue)) != NULL) {
1140 skb->protocol = eth_type_trans(skb, dev);
1141 netif_receive_skb(skb);
1142 }
1143
1144 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1145 dev->name, ring->curr, ring->dirty, done);
1146
1147 return done;
1148 }
1149
1150 static int ag71xx_poll(struct napi_struct *napi, int limit)
1151 {
1152 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1153 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1154 struct net_device *dev = ag->dev;
1155 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1156 int rx_ring_size = BIT(rx_ring->order);
1157 unsigned long flags;
1158 u32 status;
1159 int tx_done;
1160 int rx_done;
1161
1162 pdata->ddr_flush();
1163 tx_done = ag71xx_tx_packets(ag, false);
1164
1165 DBG("%s: processing RX ring\n", dev->name);
1166 rx_done = ag71xx_rx_packets(ag, limit);
1167
1168 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1169
1170 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1171 goto oom;
1172
1173 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1174 if (unlikely(status & RX_STATUS_OF)) {
1175 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1176 dev->stats.rx_fifo_errors++;
1177
1178 /* restart RX */
1179 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1180 }
1181
1182 if (rx_done < limit) {
1183 if (status & RX_STATUS_PR)
1184 goto more;
1185
1186 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1187 if (status & TX_STATUS_PS)
1188 goto more;
1189
1190 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1191 dev->name, rx_done, tx_done, limit);
1192
1193 napi_complete(napi);
1194
1195 /* enable interrupts */
1196 spin_lock_irqsave(&ag->lock, flags);
1197 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1198 spin_unlock_irqrestore(&ag->lock, flags);
1199 return rx_done;
1200 }
1201
1202 more:
1203 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1204 dev->name, rx_done, tx_done, limit);
1205 return limit;
1206
1207 oom:
1208 if (netif_msg_rx_err(ag))
1209 pr_info("%s: out of memory\n", dev->name);
1210
1211 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1212 napi_complete(napi);
1213 return 0;
1214 }
1215
1216 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1217 {
1218 struct net_device *dev = dev_id;
1219 struct ag71xx *ag = netdev_priv(dev);
1220 u32 status;
1221
1222 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1223 ag71xx_dump_intr(ag, "raw", status);
1224
1225 if (unlikely(!status))
1226 return IRQ_NONE;
1227
1228 if (unlikely(status & AG71XX_INT_ERR)) {
1229 if (status & AG71XX_INT_TX_BE) {
1230 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1231 dev_err(&dev->dev, "TX BUS error\n");
1232 }
1233 if (status & AG71XX_INT_RX_BE) {
1234 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1235 dev_err(&dev->dev, "RX BUS error\n");
1236 }
1237 }
1238
1239 if (likely(status & AG71XX_INT_POLL)) {
1240 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1241 DBG("%s: enable polling mode\n", dev->name);
1242 napi_schedule(&ag->napi);
1243 }
1244
1245 ag71xx_debugfs_update_int_stats(ag, status);
1246
1247 return IRQ_HANDLED;
1248 }
1249
1250 #ifdef CONFIG_NET_POLL_CONTROLLER
1251 /*
1252 * Polling 'interrupt' - used by things like netconsole to send skbs
1253 * without having to re-enable interrupts. It's not called while
1254 * the interrupt routine is executing.
1255 */
1256 static void ag71xx_netpoll(struct net_device *dev)
1257 {
1258 disable_irq(dev->irq);
1259 ag71xx_interrupt(dev->irq, dev);
1260 enable_irq(dev->irq);
1261 }
1262 #endif
1263
1264 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1265 {
1266 struct ag71xx *ag = netdev_priv(dev);
1267 unsigned int max_frame_len;
1268
1269 max_frame_len = ag71xx_max_frame_len(new_mtu);
1270 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1271 return -EINVAL;
1272
1273 if (netif_running(dev))
1274 return -EBUSY;
1275
1276 dev->mtu = new_mtu;
1277 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1278 ag71xx_max_frame_len(dev->mtu));
1279
1280 return 0;
1281 }
1282
1283 static const struct net_device_ops ag71xx_netdev_ops = {
1284 .ndo_open = ag71xx_open,
1285 .ndo_stop = ag71xx_stop,
1286 .ndo_start_xmit = ag71xx_hard_start_xmit,
1287 .ndo_do_ioctl = ag71xx_do_ioctl,
1288 .ndo_tx_timeout = ag71xx_tx_timeout,
1289 .ndo_change_mtu = ag71xx_change_mtu,
1290 .ndo_set_mac_address = eth_mac_addr,
1291 .ndo_validate_addr = eth_validate_addr,
1292 #ifdef CONFIG_NET_POLL_CONTROLLER
1293 .ndo_poll_controller = ag71xx_netpoll,
1294 #endif
1295 };
1296
1297 static int ag71xx_probe(struct platform_device *pdev)
1298 {
1299 struct net_device *dev;
1300 struct resource *res;
1301 struct ag71xx *ag;
1302 struct ag71xx_platform_data *pdata;
1303 int tx_size, err;
1304
1305 pdata = pdev->dev.platform_data;
1306 if (!pdata) {
1307 dev_err(&pdev->dev, "no platform data specified\n");
1308 return -ENXIO;
1309
1310 }
1311
1312 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1313 dev_err(&pdev->dev, "no MII bus device specified\n");
1314 return -EINVAL;
1315 }
1316
1317 dev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1318 if (!dev)
1319 return -ENOMEM;
1320
1321 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1322 return -EINVAL;
1323
1324 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1325 if (!res)
1326 return -EINVAL;
1327
1328 SET_NETDEV_DEV(dev, &pdev->dev);
1329
1330 ag = netdev_priv(dev);
1331 ag->pdev = pdev;
1332 ag->dev = dev;
1333 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1334 AG71XX_DEFAULT_MSG_ENABLE);
1335 spin_lock_init(&ag->lock);
1336
1337 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1338 if (!res) {
1339 dev_err(&pdev->dev, "no mac_base resource found\n");
1340 return -ENXIO;
1341 }
1342
1343 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1344 res->end - res->start + 1);
1345 if (!ag->mac_base)
1346 return -ENOMEM;
1347
1348 dev->irq = platform_get_irq(pdev, 0);
1349 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1350 0x0, dev_name(&pdev->dev), dev);
1351 if (err) {
1352 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1353 return err;
1354 }
1355
1356 dev->base_addr = (unsigned long)ag->mac_base;
1357 dev->netdev_ops = &ag71xx_netdev_ops;
1358 dev->ethtool_ops = &ag71xx_ethtool_ops;
1359
1360 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1361
1362 init_timer(&ag->oom_timer);
1363 ag->oom_timer.data = (unsigned long) dev;
1364 ag->oom_timer.function = ag71xx_oom_timer_handler;
1365
1366 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1367 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1368
1369 ag->max_frame_len = pdata->max_frame_len;
1370 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1371
1372 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1373 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1374 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1375 }
1376 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1377
1378 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1379 sizeof(struct ag71xx_desc),
1380 &ag->stop_desc_dma, GFP_KERNEL);
1381
1382 if (!ag->stop_desc)
1383 return -ENOMEM;
1384
1385 ag->stop_desc->data = 0;
1386 ag->stop_desc->ctrl = 0;
1387 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1388
1389 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1390
1391 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1392
1393 ag71xx_dump_regs(ag);
1394
1395 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1396
1397 ag71xx_hw_init(ag);
1398
1399 ag71xx_dump_regs(ag);
1400
1401 err = ag71xx_phy_connect(ag);
1402 if (err)
1403 return err;
1404
1405 err = ag71xx_debugfs_init(ag);
1406 if (err)
1407 goto err_phy_disconnect;
1408
1409 platform_set_drvdata(pdev, dev);
1410
1411 err = register_netdev(dev);
1412 if (err) {
1413 dev_err(&pdev->dev, "unable to register net device\n");
1414 platform_set_drvdata(pdev, NULL);
1415 ag71xx_debugfs_exit(ag);
1416 goto err_phy_disconnect;
1417 }
1418
1419 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1420 dev->name, (unsigned long) ag->mac_base, dev->irq,
1421 phy_modes(pdata->phy_if_mode));
1422
1423 return 0;
1424
1425 err_phy_disconnect:
1426 ag71xx_phy_disconnect(ag);
1427 return err;
1428 }
1429
1430 static int ag71xx_remove(struct platform_device *pdev)
1431 {
1432 struct net_device *dev = platform_get_drvdata(pdev);
1433 struct ag71xx *ag;
1434
1435 if (!dev)
1436 return 0;
1437
1438 ag = netdev_priv(dev);
1439 ag71xx_debugfs_exit(ag);
1440 ag71xx_phy_disconnect(ag);
1441 unregister_netdev(dev);
1442 platform_set_drvdata(pdev, NULL);
1443 return 0;
1444 }
1445
1446 static struct platform_driver ag71xx_driver = {
1447 .probe = ag71xx_probe,
1448 .remove = ag71xx_remove,
1449 .driver = {
1450 .name = AG71XX_DRV_NAME,
1451 }
1452 };
1453
1454 static int __init ag71xx_module_init(void)
1455 {
1456 int ret;
1457
1458 ret = ag71xx_debugfs_root_init();
1459 if (ret)
1460 goto err_out;
1461
1462 ret = ag71xx_mdio_driver_init();
1463 if (ret)
1464 goto err_debugfs_exit;
1465
1466 ret = platform_driver_register(&ag71xx_driver);
1467 if (ret)
1468 goto err_mdio_exit;
1469
1470 return 0;
1471
1472 err_mdio_exit:
1473 ag71xx_mdio_driver_exit();
1474 err_debugfs_exit:
1475 ag71xx_debugfs_root_exit();
1476 err_out:
1477 return ret;
1478 }
1479
1480 static void __exit ag71xx_module_exit(void)
1481 {
1482 platform_driver_unregister(&ag71xx_driver);
1483 ag71xx_mdio_driver_exit();
1484 ag71xx_debugfs_root_exit();
1485 }
1486
1487 module_init(ag71xx_module_init);
1488 module_exit(ag71xx_module_exit);
1489
1490 MODULE_VERSION(AG71XX_DRV_VERSION);
1491 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1492 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1493 MODULE_LICENSE("GPL v2");
1494 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository