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ar71xx: ack completed tx descriptors only after the full frame has been completed
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define ETH_SWITCH_HEADER_LEN 2
32
33 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
34 {
35 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
36 }
37
38 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
39 {
40 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
45
46 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
51 }
52
53 static void ag71xx_dump_regs(struct ag71xx *ag)
54 {
55 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
58 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
59 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
60 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
61 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
62 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
63 ag->dev->name,
64 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
65 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
66 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
67 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
68 ag->dev->name,
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
71 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
72 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
73 ag->dev->name,
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
77 }
78
79 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
80 {
81 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
82 ag->dev->name, label, intr,
83 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
84 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
85 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
86 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
87 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
88 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
89 }
90
91 static void ag71xx_ring_free(struct ag71xx_ring *ring)
92 {
93 kfree(ring->buf);
94
95 if (ring->descs_cpu)
96 dma_free_coherent(NULL, ring->size * ring->desc_size,
97 ring->descs_cpu, ring->descs_dma);
98 }
99
100 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
101 {
102 int err;
103 int i;
104
105 ring->desc_size = sizeof(struct ag71xx_desc);
106 if (ring->desc_size % cache_line_size()) {
107 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
108 ring, ring->desc_size,
109 roundup(ring->desc_size, cache_line_size()));
110 ring->desc_size = roundup(ring->desc_size, cache_line_size());
111 }
112
113 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
114 &ring->descs_dma, GFP_ATOMIC);
115 if (!ring->descs_cpu) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120
121 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
122 if (!ring->buf) {
123 err = -ENOMEM;
124 goto err;
125 }
126
127 for (i = 0; i < ring->size; i++) {
128 int idx = i * ring->desc_size;
129 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
130 DBG("ag71xx: ring %p, desc %d at %p\n",
131 ring, i, ring->buf[i].desc);
132 }
133
134 return 0;
135
136 err:
137 return err;
138 }
139
140 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
141 {
142 struct ag71xx_ring *ring = &ag->tx_ring;
143 struct net_device *dev = ag->dev;
144 u32 bytes_compl = 0, pkts_compl = 0;
145
146 while (ring->curr != ring->dirty) {
147 u32 i = ring->dirty % ring->size;
148
149 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
150 ring->buf[i].desc->ctrl = 0;
151 dev->stats.tx_errors++;
152 }
153
154 if (ring->buf[i].skb) {
155 bytes_compl += ring->buf[i].len;
156 pkts_compl++;
157 dev_kfree_skb_any(ring->buf[i].skb);
158 }
159 ring->buf[i].skb = NULL;
160 ring->dirty++;
161 }
162
163 /* flush descriptors */
164 wmb();
165
166 netdev_completed_queue(dev, pkts_compl, bytes_compl);
167 }
168
169 static void ag71xx_ring_tx_init(struct ag71xx *ag)
170 {
171 struct ag71xx_ring *ring = &ag->tx_ring;
172 int i;
173
174 for (i = 0; i < ring->size; i++) {
175 ring->buf[i].desc->next = (u32) (ring->descs_dma +
176 ring->desc_size * ((i + 1) % ring->size));
177
178 ring->buf[i].desc->ctrl = DESC_EMPTY;
179 ring->buf[i].skb = NULL;
180 }
181
182 /* flush descriptors */
183 wmb();
184
185 ring->curr = 0;
186 ring->dirty = 0;
187 netdev_reset_queue(ag->dev);
188 }
189
190 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
191 {
192 struct ag71xx_ring *ring = &ag->rx_ring;
193 int i;
194
195 if (!ring->buf)
196 return;
197
198 for (i = 0; i < ring->size; i++)
199 if (ring->buf[i].rx_buf) {
200 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
201 ag->rx_buf_size, DMA_FROM_DEVICE);
202 kfree(ring->buf[i].rx_buf);
203 }
204 }
205
206 static int ag71xx_buffer_offset(struct ag71xx *ag)
207 {
208 int offset = NET_SKB_PAD;
209
210 /*
211 * On AR71xx/AR91xx packets must be 4-byte aligned.
212 *
213 * When using builtin AR8216 support, hardware adds a 2-byte header,
214 * so we don't need any extra alignment in that case.
215 */
216 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
217 return offset;
218
219 return offset + NET_IP_ALIGN;
220 }
221
222 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
223 int offset)
224 {
225 void *data;
226
227 data = kmalloc(ag->rx_buf_size +
228 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
229 GFP_ATOMIC);
230 if (!data)
231 return false;
232
233 buf->rx_buf = data;
234 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
235 DMA_FROM_DEVICE);
236 buf->desc->data = (u32) buf->dma_addr + offset;
237 return true;
238 }
239
240 static int ag71xx_ring_rx_init(struct ag71xx *ag)
241 {
242 struct ag71xx_ring *ring = &ag->rx_ring;
243 unsigned int i;
244 int ret;
245 int offset = ag71xx_buffer_offset(ag);
246
247 ret = 0;
248 for (i = 0; i < ring->size; i++) {
249 ring->buf[i].desc->next = (u32) (ring->descs_dma +
250 ring->desc_size * ((i + 1) % ring->size));
251
252 DBG("ag71xx: RX desc at %p, next is %08x\n",
253 ring->buf[i].desc,
254 ring->buf[i].desc->next);
255 }
256
257 for (i = 0; i < ring->size; i++) {
258 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
259 ret = -ENOMEM;
260 break;
261 }
262
263 ring->buf[i].desc->ctrl = DESC_EMPTY;
264 }
265
266 /* flush descriptors */
267 wmb();
268
269 ring->curr = 0;
270 ring->dirty = 0;
271
272 return ret;
273 }
274
275 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
276 {
277 struct ag71xx_ring *ring = &ag->rx_ring;
278 unsigned int count;
279 int offset = ag71xx_buffer_offset(ag);
280
281 count = 0;
282 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
283 unsigned int i;
284
285 i = ring->dirty % ring->size;
286
287 if (!ring->buf[i].rx_buf &&
288 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
289 break;
290
291 ring->buf[i].desc->ctrl = DESC_EMPTY;
292 count++;
293 }
294
295 /* flush descriptors */
296 wmb();
297
298 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
299
300 return count;
301 }
302
303 static int ag71xx_rings_init(struct ag71xx *ag)
304 {
305 int ret;
306
307 ret = ag71xx_ring_alloc(&ag->tx_ring);
308 if (ret)
309 return ret;
310
311 ag71xx_ring_tx_init(ag);
312
313 ret = ag71xx_ring_alloc(&ag->rx_ring);
314 if (ret)
315 return ret;
316
317 ret = ag71xx_ring_rx_init(ag);
318 return ret;
319 }
320
321 static void ag71xx_rings_cleanup(struct ag71xx *ag)
322 {
323 ag71xx_ring_rx_clean(ag);
324 ag71xx_ring_free(&ag->rx_ring);
325
326 ag71xx_ring_tx_clean(ag);
327 netdev_reset_queue(ag->dev);
328 ag71xx_ring_free(&ag->tx_ring);
329 }
330
331 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
332 {
333 switch (ag->speed) {
334 case SPEED_1000:
335 return "1000";
336 case SPEED_100:
337 return "100";
338 case SPEED_10:
339 return "10";
340 }
341
342 return "?";
343 }
344
345 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
346 {
347 u32 t;
348
349 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
350 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
351
352 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
353
354 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
355 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
356 }
357
358 static void ag71xx_dma_reset(struct ag71xx *ag)
359 {
360 u32 val;
361 int i;
362
363 ag71xx_dump_dma_regs(ag);
364
365 /* stop RX and TX */
366 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
367 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
368
369 /*
370 * give the hardware some time to really stop all rx/tx activity
371 * clearing the descriptors too early causes random memory corruption
372 */
373 mdelay(1);
374
375 /* clear descriptor addresses */
376 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
377 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
378
379 /* clear pending RX/TX interrupts */
380 for (i = 0; i < 256; i++) {
381 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
382 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
383 }
384
385 /* clear pending errors */
386 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
387 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
388
389 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
390 if (val)
391 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
392 ag->dev->name, val);
393
394 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
395
396 /* mask out reserved bits */
397 val &= ~0xff000000;
398
399 if (val)
400 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
401 ag->dev->name, val);
402
403 ag71xx_dump_dma_regs(ag);
404 }
405
406 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
407 MAC_CFG1_SRX | MAC_CFG1_STX)
408
409 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
410
411 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
412 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
413 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
414 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
415 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
416 FIFO_CFG4_VT)
417
418 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
419 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
420 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
421 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
422 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
423 FIFO_CFG5_17 | FIFO_CFG5_SF)
424
425 static void ag71xx_hw_stop(struct ag71xx *ag)
426 {
427 /* disable all interrupts and stop the rx/tx engine */
428 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
429 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
430 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
431 }
432
433 static void ag71xx_hw_setup(struct ag71xx *ag)
434 {
435 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
436
437 /* setup MAC configuration registers */
438 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
439
440 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
441 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
442
443 /* setup max frame length to zero */
444 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
445
446 /* setup FIFO configuration registers */
447 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
448 if (pdata->is_ar724x) {
449 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
451 } else {
452 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
454 }
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
457 }
458
459 static void ag71xx_hw_init(struct ag71xx *ag)
460 {
461 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
462 u32 reset_mask = pdata->reset_bit;
463
464 ag71xx_hw_stop(ag);
465
466 if (pdata->is_ar724x) {
467 u32 reset_phy = reset_mask;
468
469 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
470 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
471
472 ath79_device_reset_set(reset_phy);
473 mdelay(50);
474 ath79_device_reset_clear(reset_phy);
475 mdelay(200);
476 }
477
478 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
479 udelay(20);
480
481 ath79_device_reset_set(reset_mask);
482 mdelay(100);
483 ath79_device_reset_clear(reset_mask);
484 mdelay(200);
485
486 ag71xx_hw_setup(ag);
487
488 ag71xx_dma_reset(ag);
489 }
490
491 static void ag71xx_fast_reset(struct ag71xx *ag)
492 {
493 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
494 struct net_device *dev = ag->dev;
495 u32 reset_mask = pdata->reset_bit;
496 u32 rx_ds, tx_ds;
497 u32 mii_reg;
498
499 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
500
501 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
502 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
503 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
504
505 ath79_device_reset_set(reset_mask);
506 udelay(10);
507 ath79_device_reset_clear(reset_mask);
508 udelay(10);
509
510 ag71xx_dma_reset(ag);
511 ag71xx_hw_setup(ag);
512
513 /* setup max frame length */
514 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
515 ag71xx_max_frame_len(ag->dev->mtu));
516
517 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
518 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
519 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
520
521 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
522 }
523
524 static void ag71xx_hw_start(struct ag71xx *ag)
525 {
526 /* start RX engine */
527 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
528
529 /* enable interrupts */
530 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
531 }
532
533 void ag71xx_link_adjust(struct ag71xx *ag)
534 {
535 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
536 u32 cfg2;
537 u32 ifctl;
538 u32 fifo5;
539 u32 fifo3;
540
541 if (!ag->link) {
542 ag71xx_hw_stop(ag);
543 netif_carrier_off(ag->dev);
544 if (netif_msg_link(ag))
545 pr_info("%s: link down\n", ag->dev->name);
546 return;
547 }
548
549 if (pdata->is_ar724x)
550 ag71xx_fast_reset(ag);
551
552 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
553 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
554 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
555
556 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
557 ifctl &= ~(MAC_IFCTL_SPEED);
558
559 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
560 fifo5 &= ~FIFO_CFG5_BM;
561
562 switch (ag->speed) {
563 case SPEED_1000:
564 cfg2 |= MAC_CFG2_IF_1000;
565 fifo5 |= FIFO_CFG5_BM;
566 break;
567 case SPEED_100:
568 cfg2 |= MAC_CFG2_IF_10_100;
569 ifctl |= MAC_IFCTL_SPEED;
570 break;
571 case SPEED_10:
572 cfg2 |= MAC_CFG2_IF_10_100;
573 break;
574 default:
575 BUG();
576 return;
577 }
578
579 if (pdata->is_ar91xx)
580 fifo3 = 0x00780fff;
581 else if (pdata->is_ar724x)
582 fifo3 = pdata->fifo_cfg3;
583 else
584 fifo3 = 0x008001ff;
585
586 if (ag->tx_ring.desc_split) {
587 fifo3 &= 0xffff;
588 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
589 }
590
591 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
592
593 if (pdata->set_speed)
594 pdata->set_speed(ag->speed);
595
596 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
597 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
598 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
599 ag71xx_hw_start(ag);
600
601 netif_carrier_on(ag->dev);
602 if (netif_msg_link(ag))
603 pr_info("%s: link up (%sMbps/%s duplex)\n",
604 ag->dev->name,
605 ag71xx_speed_str(ag),
606 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
607
608 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
609 ag->dev->name,
610 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
611 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
612 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
613
614 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
615 ag->dev->name,
616 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
617 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
618 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
619
620 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
621 ag->dev->name,
622 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
623 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
624 }
625
626 static int ag71xx_open(struct net_device *dev)
627 {
628 struct ag71xx *ag = netdev_priv(dev);
629 unsigned int max_frame_len;
630 int ret;
631
632 max_frame_len = ag71xx_max_frame_len(dev->mtu);
633 ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
634
635 /* setup max frame length */
636 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
637
638 ret = ag71xx_rings_init(ag);
639 if (ret)
640 goto err;
641
642 napi_enable(&ag->napi);
643
644 netif_carrier_off(dev);
645 ag71xx_phy_start(ag);
646
647 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
648 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
649
650 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
651
652 netif_start_queue(dev);
653
654 return 0;
655
656 err:
657 ag71xx_rings_cleanup(ag);
658 return ret;
659 }
660
661 static int ag71xx_stop(struct net_device *dev)
662 {
663 struct ag71xx *ag = netdev_priv(dev);
664 unsigned long flags;
665
666 netif_carrier_off(dev);
667 ag71xx_phy_stop(ag);
668
669 spin_lock_irqsave(&ag->lock, flags);
670
671 netif_stop_queue(dev);
672
673 ag71xx_hw_stop(ag);
674 ag71xx_dma_reset(ag);
675
676 napi_disable(&ag->napi);
677 del_timer_sync(&ag->oom_timer);
678
679 spin_unlock_irqrestore(&ag->lock, flags);
680
681 ag71xx_rings_cleanup(ag);
682
683 return 0;
684 }
685
686 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
687 {
688 int i;
689 struct ag71xx_desc *desc;
690 int ndesc = 0;
691 int split = ring->desc_split;
692
693 if (!split)
694 split = len;
695
696 while (len > 0) {
697 unsigned int cur_len = len;
698
699 i = (ring->curr + ndesc) % ring->size;
700 desc = ring->buf[i].desc;
701
702 if (!ag71xx_desc_empty(desc))
703 return -1;
704
705 if (cur_len > split) {
706 cur_len = split;
707
708 /*
709 * TX will hang if DMA transfers <= 4 bytes,
710 * make sure next segment is more than 4 bytes long.
711 */
712 if (len <= split + 4)
713 cur_len -= 4;
714 }
715
716 desc->data = addr;
717 addr += cur_len;
718 len -= cur_len;
719
720 if (len > 0)
721 cur_len |= DESC_MORE;
722
723 /* prevent early tx attempt of this descriptor */
724 if (!ndesc)
725 cur_len |= DESC_EMPTY;
726
727 desc->ctrl = cur_len;
728 ndesc++;
729 }
730
731 return ndesc;
732 }
733
734 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
735 struct net_device *dev)
736 {
737 struct ag71xx *ag = netdev_priv(dev);
738 struct ag71xx_ring *ring = &ag->tx_ring;
739 struct ag71xx_desc *desc;
740 dma_addr_t dma_addr;
741 int i, n, ring_min;
742
743 if (ag71xx_has_ar8216(ag))
744 ag71xx_add_ar8216_header(ag, skb);
745
746 if (skb->len <= 4) {
747 DBG("%s: packet len is too small\n", ag->dev->name);
748 goto err_drop;
749 }
750
751 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
752 DMA_TO_DEVICE);
753
754 i = ring->curr % ring->size;
755 desc = ring->buf[i].desc;
756
757 /* setup descriptor fields */
758 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
759 if (n < 0)
760 goto err_drop_unmap;
761
762 i = (ring->curr + n - 1) % ring->size;
763 ring->buf[i].len = skb->len;
764 ring->buf[i].skb = skb;
765 ring->buf[i].timestamp = jiffies;
766
767 netdev_sent_queue(dev, skb->len);
768
769 desc->ctrl &= ~DESC_EMPTY;
770 ring->curr += n;
771
772 /* flush descriptor */
773 wmb();
774
775 ring_min = 2;
776 if (ring->desc_split)
777 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
778
779 if (ring->curr - ring->dirty >= ring->size - ring_min) {
780 DBG("%s: tx queue full\n", dev->name);
781 netif_stop_queue(dev);
782 }
783
784 DBG("%s: packet injected into TX queue\n", ag->dev->name);
785
786 /* enable TX engine */
787 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
788
789 return NETDEV_TX_OK;
790
791 err_drop_unmap:
792 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
793
794 err_drop:
795 dev->stats.tx_dropped++;
796
797 dev_kfree_skb(skb);
798 return NETDEV_TX_OK;
799 }
800
801 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
802 {
803 struct ag71xx *ag = netdev_priv(dev);
804 int ret;
805
806 switch (cmd) {
807 case SIOCETHTOOL:
808 if (ag->phy_dev == NULL)
809 break;
810
811 spin_lock_irq(&ag->lock);
812 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
813 spin_unlock_irq(&ag->lock);
814 return ret;
815
816 case SIOCSIFHWADDR:
817 if (copy_from_user
818 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
819 return -EFAULT;
820 return 0;
821
822 case SIOCGIFHWADDR:
823 if (copy_to_user
824 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
825 return -EFAULT;
826 return 0;
827
828 case SIOCGMIIPHY:
829 case SIOCGMIIREG:
830 case SIOCSMIIREG:
831 if (ag->phy_dev == NULL)
832 break;
833
834 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
835
836 default:
837 break;
838 }
839
840 return -EOPNOTSUPP;
841 }
842
843 static void ag71xx_oom_timer_handler(unsigned long data)
844 {
845 struct net_device *dev = (struct net_device *) data;
846 struct ag71xx *ag = netdev_priv(dev);
847
848 napi_schedule(&ag->napi);
849 }
850
851 static void ag71xx_tx_timeout(struct net_device *dev)
852 {
853 struct ag71xx *ag = netdev_priv(dev);
854
855 if (netif_msg_tx_err(ag))
856 pr_info("%s: tx timeout\n", ag->dev->name);
857
858 schedule_work(&ag->restart_work);
859 }
860
861 static void ag71xx_restart_work_func(struct work_struct *work)
862 {
863 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
864
865 if (ag71xx_get_pdata(ag)->is_ar724x) {
866 ag->link = 0;
867 ag71xx_link_adjust(ag);
868 return;
869 }
870
871 ag71xx_stop(ag->dev);
872 ag71xx_open(ag->dev);
873 }
874
875 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
876 {
877 u32 rx_sm, tx_sm, rx_fd;
878
879 if (likely(time_before(jiffies, timestamp + HZ/10)))
880 return false;
881
882 if (!netif_carrier_ok(ag->dev))
883 return false;
884
885 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
886 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
887 return true;
888
889 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
890 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
891 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
892 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
893 return true;
894
895 return false;
896 }
897
898 static int ag71xx_tx_packets(struct ag71xx *ag)
899 {
900 struct ag71xx_ring *ring = &ag->tx_ring;
901 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
902 int sent = 0;
903 int bytes_compl = 0;
904 int n = 0;
905
906 DBG("%s: processing TX ring\n", ag->dev->name);
907
908 while (ring->dirty + n != ring->curr) {
909 unsigned int i = (ring->dirty + n) % ring->size;
910 struct ag71xx_desc *desc = ring->buf[i].desc;
911 struct sk_buff *skb = ring->buf[i].skb;
912
913 if (!ag71xx_desc_empty(desc)) {
914 if (pdata->is_ar7240 &&
915 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
916 schedule_work(&ag->restart_work);
917 break;
918 }
919
920 n++;
921 if (!skb)
922 continue;
923
924 dev_kfree_skb_any(skb);
925 ring->buf[i].skb = NULL;
926
927 bytes_compl += ring->buf[i].len;
928
929 sent++;
930 ring->dirty += n;
931
932 while (n > 0) {
933 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
934 n--;
935 }
936 }
937
938 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
939
940 ag->dev->stats.tx_bytes += bytes_compl;
941 ag->dev->stats.tx_packets += sent;
942
943 if (!sent)
944 return 0;
945
946 netdev_completed_queue(ag->dev, sent, bytes_compl);
947 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
948 netif_wake_queue(ag->dev);
949
950 return sent;
951 }
952
953 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
954 {
955 struct net_device *dev = ag->dev;
956 struct ag71xx_ring *ring = &ag->rx_ring;
957 int offset = ag71xx_buffer_offset(ag);
958 unsigned int pktlen_mask = ag->desc_pktlen_mask;
959 int done = 0;
960
961 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
962 dev->name, limit, ring->curr, ring->dirty);
963
964 while (done < limit) {
965 unsigned int i = ring->curr % ring->size;
966 struct ag71xx_desc *desc = ring->buf[i].desc;
967 struct sk_buff *skb;
968 int pktlen;
969 int err = 0;
970
971 if (ag71xx_desc_empty(desc))
972 break;
973
974 if ((ring->dirty + ring->size) == ring->curr) {
975 ag71xx_assert(0);
976 break;
977 }
978
979 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
980
981 pktlen = desc->ctrl & pktlen_mask;
982 pktlen -= ETH_FCS_LEN;
983
984 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
985 ag->rx_buf_size, DMA_FROM_DEVICE);
986
987 dev->stats.rx_packets++;
988 dev->stats.rx_bytes += pktlen;
989
990 skb = build_skb(ring->buf[i].rx_buf, 0);
991 if (!skb) {
992 kfree(ring->buf[i].rx_buf);
993 goto next;
994 }
995
996 skb_reserve(skb, offset);
997 skb_put(skb, pktlen);
998
999 if (ag71xx_has_ar8216(ag))
1000 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1001
1002 if (err) {
1003 dev->stats.rx_dropped++;
1004 kfree_skb(skb);
1005 } else {
1006 skb->dev = dev;
1007 skb->ip_summed = CHECKSUM_NONE;
1008 skb->protocol = eth_type_trans(skb, dev);
1009 netif_receive_skb(skb);
1010 }
1011
1012 next:
1013 ring->buf[i].rx_buf = NULL;
1014 done++;
1015
1016 ring->curr++;
1017 }
1018
1019 ag71xx_ring_rx_refill(ag);
1020
1021 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1022 dev->name, ring->curr, ring->dirty, done);
1023
1024 return done;
1025 }
1026
1027 static int ag71xx_poll(struct napi_struct *napi, int limit)
1028 {
1029 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1030 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1031 struct net_device *dev = ag->dev;
1032 struct ag71xx_ring *rx_ring;
1033 unsigned long flags;
1034 u32 status;
1035 int tx_done;
1036 int rx_done;
1037
1038 pdata->ddr_flush();
1039 tx_done = ag71xx_tx_packets(ag);
1040
1041 DBG("%s: processing RX ring\n", dev->name);
1042 rx_done = ag71xx_rx_packets(ag, limit);
1043
1044 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1045
1046 rx_ring = &ag->rx_ring;
1047 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
1048 goto oom;
1049
1050 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1051 if (unlikely(status & RX_STATUS_OF)) {
1052 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1053 dev->stats.rx_fifo_errors++;
1054
1055 /* restart RX */
1056 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1057 }
1058
1059 if (rx_done < limit) {
1060 if (status & RX_STATUS_PR)
1061 goto more;
1062
1063 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1064 if (status & TX_STATUS_PS)
1065 goto more;
1066
1067 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1068 dev->name, rx_done, tx_done, limit);
1069
1070 napi_complete(napi);
1071
1072 /* enable interrupts */
1073 spin_lock_irqsave(&ag->lock, flags);
1074 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1075 spin_unlock_irqrestore(&ag->lock, flags);
1076 return rx_done;
1077 }
1078
1079 more:
1080 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1081 dev->name, rx_done, tx_done, limit);
1082 return rx_done;
1083
1084 oom:
1085 if (netif_msg_rx_err(ag))
1086 pr_info("%s: out of memory\n", dev->name);
1087
1088 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1089 napi_complete(napi);
1090 return 0;
1091 }
1092
1093 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1094 {
1095 struct net_device *dev = dev_id;
1096 struct ag71xx *ag = netdev_priv(dev);
1097 u32 status;
1098
1099 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1100 ag71xx_dump_intr(ag, "raw", status);
1101
1102 if (unlikely(!status))
1103 return IRQ_NONE;
1104
1105 if (unlikely(status & AG71XX_INT_ERR)) {
1106 if (status & AG71XX_INT_TX_BE) {
1107 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1108 dev_err(&dev->dev, "TX BUS error\n");
1109 }
1110 if (status & AG71XX_INT_RX_BE) {
1111 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1112 dev_err(&dev->dev, "RX BUS error\n");
1113 }
1114 }
1115
1116 if (likely(status & AG71XX_INT_POLL)) {
1117 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1118 DBG("%s: enable polling mode\n", dev->name);
1119 napi_schedule(&ag->napi);
1120 }
1121
1122 ag71xx_debugfs_update_int_stats(ag, status);
1123
1124 return IRQ_HANDLED;
1125 }
1126
1127 #ifdef CONFIG_NET_POLL_CONTROLLER
1128 /*
1129 * Polling 'interrupt' - used by things like netconsole to send skbs
1130 * without having to re-enable interrupts. It's not called while
1131 * the interrupt routine is executing.
1132 */
1133 static void ag71xx_netpoll(struct net_device *dev)
1134 {
1135 disable_irq(dev->irq);
1136 ag71xx_interrupt(dev->irq, dev);
1137 enable_irq(dev->irq);
1138 }
1139 #endif
1140
1141 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1142 {
1143 struct ag71xx *ag = netdev_priv(dev);
1144 unsigned int max_frame_len;
1145
1146 max_frame_len = ag71xx_max_frame_len(new_mtu);
1147 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1148 return -EINVAL;
1149
1150 if (netif_running(dev))
1151 return -EBUSY;
1152
1153 dev->mtu = new_mtu;
1154 return 0;
1155 }
1156
1157 static const struct net_device_ops ag71xx_netdev_ops = {
1158 .ndo_open = ag71xx_open,
1159 .ndo_stop = ag71xx_stop,
1160 .ndo_start_xmit = ag71xx_hard_start_xmit,
1161 .ndo_do_ioctl = ag71xx_do_ioctl,
1162 .ndo_tx_timeout = ag71xx_tx_timeout,
1163 .ndo_change_mtu = ag71xx_change_mtu,
1164 .ndo_set_mac_address = eth_mac_addr,
1165 .ndo_validate_addr = eth_validate_addr,
1166 #ifdef CONFIG_NET_POLL_CONTROLLER
1167 .ndo_poll_controller = ag71xx_netpoll,
1168 #endif
1169 };
1170
1171 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1172 {
1173 switch (mode) {
1174 case PHY_INTERFACE_MODE_MII:
1175 return "MII";
1176 case PHY_INTERFACE_MODE_GMII:
1177 return "GMII";
1178 case PHY_INTERFACE_MODE_RMII:
1179 return "RMII";
1180 case PHY_INTERFACE_MODE_RGMII:
1181 return "RGMII";
1182 case PHY_INTERFACE_MODE_SGMII:
1183 return "SGMII";
1184 default:
1185 break;
1186 }
1187
1188 return "unknown";
1189 }
1190
1191
1192 static int ag71xx_probe(struct platform_device *pdev)
1193 {
1194 struct net_device *dev;
1195 struct resource *res;
1196 struct ag71xx *ag;
1197 struct ag71xx_platform_data *pdata;
1198 int err;
1199
1200 pdata = pdev->dev.platform_data;
1201 if (!pdata) {
1202 dev_err(&pdev->dev, "no platform data specified\n");
1203 err = -ENXIO;
1204 goto err_out;
1205 }
1206
1207 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1208 dev_err(&pdev->dev, "no MII bus device specified\n");
1209 err = -EINVAL;
1210 goto err_out;
1211 }
1212
1213 dev = alloc_etherdev(sizeof(*ag));
1214 if (!dev) {
1215 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1216 err = -ENOMEM;
1217 goto err_out;
1218 }
1219
1220 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1221 return -EINVAL;
1222
1223 SET_NETDEV_DEV(dev, &pdev->dev);
1224
1225 ag = netdev_priv(dev);
1226 ag->pdev = pdev;
1227 ag->dev = dev;
1228 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1229 AG71XX_DEFAULT_MSG_ENABLE);
1230 spin_lock_init(&ag->lock);
1231
1232 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1233 if (!res) {
1234 dev_err(&pdev->dev, "no mac_base resource found\n");
1235 err = -ENXIO;
1236 goto err_out;
1237 }
1238
1239 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1240 if (!ag->mac_base) {
1241 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1242 err = -ENOMEM;
1243 goto err_free_dev;
1244 }
1245
1246 dev->irq = platform_get_irq(pdev, 0);
1247 err = request_irq(dev->irq, ag71xx_interrupt,
1248 IRQF_DISABLED,
1249 dev->name, dev);
1250 if (err) {
1251 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1252 goto err_unmap_base;
1253 }
1254
1255 dev->base_addr = (unsigned long)ag->mac_base;
1256 dev->netdev_ops = &ag71xx_netdev_ops;
1257 dev->ethtool_ops = &ag71xx_ethtool_ops;
1258
1259 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1260
1261 init_timer(&ag->oom_timer);
1262 ag->oom_timer.data = (unsigned long) dev;
1263 ag->oom_timer.function = ag71xx_oom_timer_handler;
1264
1265 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1266 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1267
1268 ag->max_frame_len = pdata->max_frame_len;
1269 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1270
1271 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1272 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1273 ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT;
1274 }
1275
1276 ag->stop_desc = dma_alloc_coherent(NULL,
1277 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1278
1279 if (!ag->stop_desc)
1280 goto err_free_irq;
1281
1282 ag->stop_desc->data = 0;
1283 ag->stop_desc->ctrl = 0;
1284 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1285
1286 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1287
1288 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1289
1290 ag71xx_dump_regs(ag);
1291
1292 ag71xx_hw_init(ag);
1293
1294 ag71xx_dump_regs(ag);
1295
1296 err = ag71xx_phy_connect(ag);
1297 if (err)
1298 goto err_free_desc;
1299
1300 err = ag71xx_debugfs_init(ag);
1301 if (err)
1302 goto err_phy_disconnect;
1303
1304 platform_set_drvdata(pdev, dev);
1305
1306 err = register_netdev(dev);
1307 if (err) {
1308 dev_err(&pdev->dev, "unable to register net device\n");
1309 goto err_debugfs_exit;
1310 }
1311
1312 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1313 dev->name, dev->base_addr, dev->irq,
1314 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1315
1316 return 0;
1317
1318 err_debugfs_exit:
1319 ag71xx_debugfs_exit(ag);
1320 err_phy_disconnect:
1321 ag71xx_phy_disconnect(ag);
1322 err_free_desc:
1323 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1324 ag->stop_desc_dma);
1325 err_free_irq:
1326 free_irq(dev->irq, dev);
1327 err_unmap_base:
1328 iounmap(ag->mac_base);
1329 err_free_dev:
1330 kfree(dev);
1331 err_out:
1332 platform_set_drvdata(pdev, NULL);
1333 return err;
1334 }
1335
1336 static int ag71xx_remove(struct platform_device *pdev)
1337 {
1338 struct net_device *dev = platform_get_drvdata(pdev);
1339
1340 if (dev) {
1341 struct ag71xx *ag = netdev_priv(dev);
1342
1343 ag71xx_debugfs_exit(ag);
1344 ag71xx_phy_disconnect(ag);
1345 unregister_netdev(dev);
1346 free_irq(dev->irq, dev);
1347 iounmap(ag->mac_base);
1348 kfree(dev);
1349 platform_set_drvdata(pdev, NULL);
1350 }
1351
1352 return 0;
1353 }
1354
1355 static struct platform_driver ag71xx_driver = {
1356 .probe = ag71xx_probe,
1357 .remove = ag71xx_remove,
1358 .driver = {
1359 .name = AG71XX_DRV_NAME,
1360 }
1361 };
1362
1363 static int __init ag71xx_module_init(void)
1364 {
1365 int ret;
1366
1367 ret = ag71xx_debugfs_root_init();
1368 if (ret)
1369 goto err_out;
1370
1371 ret = ag71xx_mdio_driver_init();
1372 if (ret)
1373 goto err_debugfs_exit;
1374
1375 ret = platform_driver_register(&ag71xx_driver);
1376 if (ret)
1377 goto err_mdio_exit;
1378
1379 return 0;
1380
1381 err_mdio_exit:
1382 ag71xx_mdio_driver_exit();
1383 err_debugfs_exit:
1384 ag71xx_debugfs_root_exit();
1385 err_out:
1386 return ret;
1387 }
1388
1389 static void __exit ag71xx_module_exit(void)
1390 {
1391 platform_driver_unregister(&ag71xx_driver);
1392 ag71xx_mdio_driver_exit();
1393 ag71xx_debugfs_root_exit();
1394 }
1395
1396 module_init(ag71xx_module_init);
1397 module_exit(ag71xx_module_exit);
1398
1399 MODULE_VERSION(AG71XX_DRV_VERSION);
1400 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1401 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1402 MODULE_LICENSE("GPL v2");
1403 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository