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ar71xx: improve ethernet driver cache footprint by removing an unnecessary pointer
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define ETH_SWITCH_HEADER_LEN 2
32
33 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
34 {
35 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
36 }
37
38 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
39 {
40 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
45
46 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
51 }
52
53 static void ag71xx_dump_regs(struct ag71xx *ag)
54 {
55 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
58 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
59 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
60 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
61 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
62 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
63 ag->dev->name,
64 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
65 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
66 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
67 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
68 ag->dev->name,
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
71 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
72 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
73 ag->dev->name,
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
77 }
78
79 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
80 {
81 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
82 ag->dev->name, label, intr,
83 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
84 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
85 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
86 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
87 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
88 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
89 }
90
91 static void ag71xx_ring_free(struct ag71xx_ring *ring)
92 {
93 kfree(ring->buf);
94
95 if (ring->descs_cpu)
96 dma_free_coherent(NULL, ring->size * ring->desc_size,
97 ring->descs_cpu, ring->descs_dma);
98 }
99
100 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
101 {
102 int err;
103
104 ring->desc_size = sizeof(struct ag71xx_desc);
105 if (ring->desc_size % cache_line_size()) {
106 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
107 ring, ring->desc_size,
108 roundup(ring->desc_size, cache_line_size()));
109 ring->desc_size = roundup(ring->desc_size, cache_line_size());
110 }
111
112 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
113 &ring->descs_dma, GFP_ATOMIC);
114 if (!ring->descs_cpu) {
115 err = -ENOMEM;
116 goto err;
117 }
118
119
120 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
121 if (!ring->buf) {
122 err = -ENOMEM;
123 goto err;
124 }
125
126 return 0;
127
128 err:
129 return err;
130 }
131
132 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
133 {
134 struct ag71xx_ring *ring = &ag->tx_ring;
135 struct net_device *dev = ag->dev;
136 u32 bytes_compl = 0, pkts_compl = 0;
137
138 while (ring->curr != ring->dirty) {
139 struct ag71xx_desc *desc;
140 u32 i = ring->dirty % ring->size;
141
142 desc = ag71xx_ring_desc(ring, i);
143 if (!ag71xx_desc_empty(desc)) {
144 desc->ctrl = 0;
145 dev->stats.tx_errors++;
146 }
147
148 if (ring->buf[i].skb) {
149 bytes_compl += ring->buf[i].len;
150 pkts_compl++;
151 dev_kfree_skb_any(ring->buf[i].skb);
152 }
153 ring->buf[i].skb = NULL;
154 ring->dirty++;
155 }
156
157 /* flush descriptors */
158 wmb();
159
160 netdev_completed_queue(dev, pkts_compl, bytes_compl);
161 }
162
163 static void ag71xx_ring_tx_init(struct ag71xx *ag)
164 {
165 struct ag71xx_ring *ring = &ag->tx_ring;
166 int i;
167
168 for (i = 0; i < ring->size; i++) {
169 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
170
171 desc->next = (u32) (ring->descs_dma +
172 ring->desc_size * ((i + 1) % ring->size));
173
174 desc->ctrl = DESC_EMPTY;
175 ring->buf[i].skb = NULL;
176 }
177
178 /* flush descriptors */
179 wmb();
180
181 ring->curr = 0;
182 ring->dirty = 0;
183 netdev_reset_queue(ag->dev);
184 }
185
186 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
187 {
188 struct ag71xx_ring *ring = &ag->rx_ring;
189 int i;
190
191 if (!ring->buf)
192 return;
193
194 for (i = 0; i < ring->size; i++)
195 if (ring->buf[i].rx_buf) {
196 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
197 ag->rx_buf_size, DMA_FROM_DEVICE);
198 kfree(ring->buf[i].rx_buf);
199 }
200 }
201
202 static int ag71xx_buffer_offset(struct ag71xx *ag)
203 {
204 int offset = NET_SKB_PAD;
205
206 /*
207 * On AR71xx/AR91xx packets must be 4-byte aligned.
208 *
209 * When using builtin AR8216 support, hardware adds a 2-byte header,
210 * so we don't need any extra alignment in that case.
211 */
212 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
213 return offset;
214
215 return offset + NET_IP_ALIGN;
216 }
217
218 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
219 int offset)
220 {
221 struct ag71xx_ring *ring = &ag->rx_ring;
222 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
223 void *data;
224
225 data = kmalloc(ag->rx_buf_size +
226 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
227 GFP_ATOMIC);
228 if (!data)
229 return false;
230
231 buf->rx_buf = data;
232 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
233 DMA_FROM_DEVICE);
234 desc->data = (u32) buf->dma_addr + offset;
235 return true;
236 }
237
238 static int ag71xx_ring_rx_init(struct ag71xx *ag)
239 {
240 struct ag71xx_ring *ring = &ag->rx_ring;
241 unsigned int i;
242 int ret;
243 int offset = ag71xx_buffer_offset(ag);
244
245 ret = 0;
246 for (i = 0; i < ring->size; i++) {
247 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
248
249 desc->next = (u32) (ring->descs_dma +
250 ring->desc_size * ((i + 1) % ring->size));
251
252 DBG("ag71xx: RX desc at %p, next is %08x\n",
253 desc, desc->next);
254 }
255
256 for (i = 0; i < ring->size; i++) {
257 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
258
259 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
260 ret = -ENOMEM;
261 break;
262 }
263
264 desc->ctrl = DESC_EMPTY;
265 }
266
267 /* flush descriptors */
268 wmb();
269
270 ring->curr = 0;
271 ring->dirty = 0;
272
273 return ret;
274 }
275
276 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
277 {
278 struct ag71xx_ring *ring = &ag->rx_ring;
279 unsigned int count;
280 int offset = ag71xx_buffer_offset(ag);
281
282 count = 0;
283 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
284 struct ag71xx_desc *desc;
285 unsigned int i;
286
287 i = ring->dirty % ring->size;
288 desc = ag71xx_ring_desc(ring, i);
289
290 if (!ring->buf[i].rx_buf &&
291 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
292 break;
293
294 desc->ctrl = DESC_EMPTY;
295 count++;
296 }
297
298 /* flush descriptors */
299 wmb();
300
301 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
302
303 return count;
304 }
305
306 static int ag71xx_rings_init(struct ag71xx *ag)
307 {
308 int ret;
309
310 ret = ag71xx_ring_alloc(&ag->tx_ring);
311 if (ret)
312 return ret;
313
314 ag71xx_ring_tx_init(ag);
315
316 ret = ag71xx_ring_alloc(&ag->rx_ring);
317 if (ret)
318 return ret;
319
320 ret = ag71xx_ring_rx_init(ag);
321 return ret;
322 }
323
324 static void ag71xx_rings_cleanup(struct ag71xx *ag)
325 {
326 ag71xx_ring_rx_clean(ag);
327 ag71xx_ring_free(&ag->rx_ring);
328
329 ag71xx_ring_tx_clean(ag);
330 netdev_reset_queue(ag->dev);
331 ag71xx_ring_free(&ag->tx_ring);
332 }
333
334 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
335 {
336 switch (ag->speed) {
337 case SPEED_1000:
338 return "1000";
339 case SPEED_100:
340 return "100";
341 case SPEED_10:
342 return "10";
343 }
344
345 return "?";
346 }
347
348 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
349 {
350 u32 t;
351
352 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
353 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
354
355 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
356
357 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
358 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
359 }
360
361 static void ag71xx_dma_reset(struct ag71xx *ag)
362 {
363 u32 val;
364 int i;
365
366 ag71xx_dump_dma_regs(ag);
367
368 /* stop RX and TX */
369 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
370 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
371
372 /*
373 * give the hardware some time to really stop all rx/tx activity
374 * clearing the descriptors too early causes random memory corruption
375 */
376 mdelay(1);
377
378 /* clear descriptor addresses */
379 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
380 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
381
382 /* clear pending RX/TX interrupts */
383 for (i = 0; i < 256; i++) {
384 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
385 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
386 }
387
388 /* clear pending errors */
389 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
390 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
391
392 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
393 if (val)
394 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
395 ag->dev->name, val);
396
397 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
398
399 /* mask out reserved bits */
400 val &= ~0xff000000;
401
402 if (val)
403 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
404 ag->dev->name, val);
405
406 ag71xx_dump_dma_regs(ag);
407 }
408
409 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
410 MAC_CFG1_SRX | MAC_CFG1_STX)
411
412 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
413
414 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
415 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
416 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
417 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
418 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
419 FIFO_CFG4_VT)
420
421 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
422 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
423 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
424 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
425 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
426 FIFO_CFG5_17 | FIFO_CFG5_SF)
427
428 static void ag71xx_hw_stop(struct ag71xx *ag)
429 {
430 /* disable all interrupts and stop the rx/tx engine */
431 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
432 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
433 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
434 }
435
436 static void ag71xx_hw_setup(struct ag71xx *ag)
437 {
438 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
439
440 /* setup MAC configuration registers */
441 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
442
443 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
444 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
445
446 /* setup max frame length to zero */
447 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
448
449 /* setup FIFO configuration registers */
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
451 if (pdata->is_ar724x) {
452 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
454 } else {
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
457 }
458 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
459 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
460 }
461
462 static void ag71xx_hw_init(struct ag71xx *ag)
463 {
464 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
465 u32 reset_mask = pdata->reset_bit;
466
467 ag71xx_hw_stop(ag);
468
469 if (pdata->is_ar724x) {
470 u32 reset_phy = reset_mask;
471
472 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
473 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
474
475 ath79_device_reset_set(reset_phy);
476 msleep(50);
477 ath79_device_reset_clear(reset_phy);
478 msleep(200);
479 }
480
481 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
482 udelay(20);
483
484 ath79_device_reset_set(reset_mask);
485 msleep(100);
486 ath79_device_reset_clear(reset_mask);
487 msleep(200);
488
489 ag71xx_hw_setup(ag);
490
491 ag71xx_dma_reset(ag);
492 }
493
494 static void ag71xx_fast_reset(struct ag71xx *ag)
495 {
496 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
497 struct net_device *dev = ag->dev;
498 u32 reset_mask = pdata->reset_bit;
499 u32 rx_ds, tx_ds;
500 u32 mii_reg;
501
502 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
503
504 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
505 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
506 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
507
508 ath79_device_reset_set(reset_mask);
509 udelay(10);
510 ath79_device_reset_clear(reset_mask);
511 udelay(10);
512
513 ag71xx_dma_reset(ag);
514 ag71xx_hw_setup(ag);
515
516 /* setup max frame length */
517 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
518 ag71xx_max_frame_len(ag->dev->mtu));
519
520 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
521 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
522 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
523
524 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
525 }
526
527 static void ag71xx_hw_start(struct ag71xx *ag)
528 {
529 /* start RX engine */
530 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
531
532 /* enable interrupts */
533 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
534 }
535
536 void ag71xx_link_adjust(struct ag71xx *ag)
537 {
538 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
539 u32 cfg2;
540 u32 ifctl;
541 u32 fifo5;
542 u32 fifo3;
543
544 if (!ag->link) {
545 ag71xx_hw_stop(ag);
546 netif_carrier_off(ag->dev);
547 if (netif_msg_link(ag))
548 pr_info("%s: link down\n", ag->dev->name);
549 return;
550 }
551
552 if (pdata->is_ar724x)
553 ag71xx_fast_reset(ag);
554
555 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
556 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
557 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
558
559 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
560 ifctl &= ~(MAC_IFCTL_SPEED);
561
562 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
563 fifo5 &= ~FIFO_CFG5_BM;
564
565 switch (ag->speed) {
566 case SPEED_1000:
567 cfg2 |= MAC_CFG2_IF_1000;
568 fifo5 |= FIFO_CFG5_BM;
569 break;
570 case SPEED_100:
571 cfg2 |= MAC_CFG2_IF_10_100;
572 ifctl |= MAC_IFCTL_SPEED;
573 break;
574 case SPEED_10:
575 cfg2 |= MAC_CFG2_IF_10_100;
576 break;
577 default:
578 BUG();
579 return;
580 }
581
582 if (pdata->is_ar91xx)
583 fifo3 = 0x00780fff;
584 else if (pdata->is_ar724x)
585 fifo3 = pdata->fifo_cfg3;
586 else
587 fifo3 = 0x008001ff;
588
589 if (ag->tx_ring.desc_split) {
590 fifo3 &= 0xffff;
591 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
592 }
593
594 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
595
596 if (pdata->set_speed)
597 pdata->set_speed(ag->speed);
598
599 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
600 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
601 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
602 ag71xx_hw_start(ag);
603
604 netif_carrier_on(ag->dev);
605 if (netif_msg_link(ag))
606 pr_info("%s: link up (%sMbps/%s duplex)\n",
607 ag->dev->name,
608 ag71xx_speed_str(ag),
609 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
610
611 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
612 ag->dev->name,
613 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
614 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
615 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
616
617 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
618 ag->dev->name,
619 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
620 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
621 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
622
623 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
624 ag->dev->name,
625 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
626 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
627 }
628
629 static int ag71xx_open(struct net_device *dev)
630 {
631 struct ag71xx *ag = netdev_priv(dev);
632 unsigned int max_frame_len;
633 int ret;
634
635 max_frame_len = ag71xx_max_frame_len(dev->mtu);
636 ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
637
638 /* setup max frame length */
639 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
640
641 ret = ag71xx_rings_init(ag);
642 if (ret)
643 goto err;
644
645 napi_enable(&ag->napi);
646
647 netif_carrier_off(dev);
648 ag71xx_phy_start(ag);
649
650 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
651 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
652
653 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
654
655 netif_start_queue(dev);
656
657 return 0;
658
659 err:
660 ag71xx_rings_cleanup(ag);
661 return ret;
662 }
663
664 static int ag71xx_stop(struct net_device *dev)
665 {
666 struct ag71xx *ag = netdev_priv(dev);
667 unsigned long flags;
668
669 netif_carrier_off(dev);
670 ag71xx_phy_stop(ag);
671
672 spin_lock_irqsave(&ag->lock, flags);
673
674 netif_stop_queue(dev);
675
676 ag71xx_hw_stop(ag);
677 ag71xx_dma_reset(ag);
678
679 napi_disable(&ag->napi);
680 del_timer_sync(&ag->oom_timer);
681
682 spin_unlock_irqrestore(&ag->lock, flags);
683
684 ag71xx_rings_cleanup(ag);
685
686 return 0;
687 }
688
689 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
690 {
691 int i;
692 struct ag71xx_desc *desc;
693 int ndesc = 0;
694 int split = ring->desc_split;
695
696 if (!split)
697 split = len;
698
699 while (len > 0) {
700 unsigned int cur_len = len;
701
702 i = (ring->curr + ndesc) % ring->size;
703 desc = ag71xx_ring_desc(ring, i);
704
705 if (!ag71xx_desc_empty(desc))
706 return -1;
707
708 if (cur_len > split) {
709 cur_len = split;
710
711 /*
712 * TX will hang if DMA transfers <= 4 bytes,
713 * make sure next segment is more than 4 bytes long.
714 */
715 if (len <= split + 4)
716 cur_len -= 4;
717 }
718
719 desc->data = addr;
720 addr += cur_len;
721 len -= cur_len;
722
723 if (len > 0)
724 cur_len |= DESC_MORE;
725
726 /* prevent early tx attempt of this descriptor */
727 if (!ndesc)
728 cur_len |= DESC_EMPTY;
729
730 desc->ctrl = cur_len;
731 ndesc++;
732 }
733
734 return ndesc;
735 }
736
737 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
738 struct net_device *dev)
739 {
740 struct ag71xx *ag = netdev_priv(dev);
741 struct ag71xx_ring *ring = &ag->tx_ring;
742 struct ag71xx_desc *desc;
743 dma_addr_t dma_addr;
744 int i, n, ring_min;
745
746 if (ag71xx_has_ar8216(ag))
747 ag71xx_add_ar8216_header(ag, skb);
748
749 if (skb->len <= 4) {
750 DBG("%s: packet len is too small\n", ag->dev->name);
751 goto err_drop;
752 }
753
754 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
755 DMA_TO_DEVICE);
756
757 i = ring->curr % ring->size;
758 desc = ag71xx_ring_desc(ring, i);
759
760 /* setup descriptor fields */
761 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
762 if (n < 0)
763 goto err_drop_unmap;
764
765 i = (ring->curr + n - 1) % ring->size;
766 ring->buf[i].len = skb->len;
767 ring->buf[i].skb = skb;
768 ring->buf[i].timestamp = jiffies;
769
770 netdev_sent_queue(dev, skb->len);
771
772 desc->ctrl &= ~DESC_EMPTY;
773 ring->curr += n;
774
775 /* flush descriptor */
776 wmb();
777
778 ring_min = 2;
779 if (ring->desc_split)
780 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
781
782 if (ring->curr - ring->dirty >= ring->size - ring_min) {
783 DBG("%s: tx queue full\n", dev->name);
784 netif_stop_queue(dev);
785 }
786
787 DBG("%s: packet injected into TX queue\n", ag->dev->name);
788
789 /* enable TX engine */
790 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
791
792 return NETDEV_TX_OK;
793
794 err_drop_unmap:
795 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
796
797 err_drop:
798 dev->stats.tx_dropped++;
799
800 dev_kfree_skb(skb);
801 return NETDEV_TX_OK;
802 }
803
804 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
805 {
806 struct ag71xx *ag = netdev_priv(dev);
807 int ret;
808
809 switch (cmd) {
810 case SIOCETHTOOL:
811 if (ag->phy_dev == NULL)
812 break;
813
814 spin_lock_irq(&ag->lock);
815 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
816 spin_unlock_irq(&ag->lock);
817 return ret;
818
819 case SIOCSIFHWADDR:
820 if (copy_from_user
821 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
822 return -EFAULT;
823 return 0;
824
825 case SIOCGIFHWADDR:
826 if (copy_to_user
827 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
828 return -EFAULT;
829 return 0;
830
831 case SIOCGMIIPHY:
832 case SIOCGMIIREG:
833 case SIOCSMIIREG:
834 if (ag->phy_dev == NULL)
835 break;
836
837 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
838
839 default:
840 break;
841 }
842
843 return -EOPNOTSUPP;
844 }
845
846 static void ag71xx_oom_timer_handler(unsigned long data)
847 {
848 struct net_device *dev = (struct net_device *) data;
849 struct ag71xx *ag = netdev_priv(dev);
850
851 napi_schedule(&ag->napi);
852 }
853
854 static void ag71xx_tx_timeout(struct net_device *dev)
855 {
856 struct ag71xx *ag = netdev_priv(dev);
857
858 if (netif_msg_tx_err(ag))
859 pr_info("%s: tx timeout\n", ag->dev->name);
860
861 schedule_work(&ag->restart_work);
862 }
863
864 static void ag71xx_restart_work_func(struct work_struct *work)
865 {
866 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
867
868 if (ag71xx_get_pdata(ag)->is_ar724x) {
869 ag->link = 0;
870 ag71xx_link_adjust(ag);
871 return;
872 }
873
874 ag71xx_stop(ag->dev);
875 ag71xx_open(ag->dev);
876 }
877
878 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
879 {
880 u32 rx_sm, tx_sm, rx_fd;
881
882 if (likely(time_before(jiffies, timestamp + HZ/10)))
883 return false;
884
885 if (!netif_carrier_ok(ag->dev))
886 return false;
887
888 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
889 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
890 return true;
891
892 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
893 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
894 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
895 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
896 return true;
897
898 return false;
899 }
900
901 static int ag71xx_tx_packets(struct ag71xx *ag)
902 {
903 struct ag71xx_ring *ring = &ag->tx_ring;
904 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
905 int sent = 0;
906 int bytes_compl = 0;
907 int n = 0;
908
909 DBG("%s: processing TX ring\n", ag->dev->name);
910
911 while (ring->dirty + n != ring->curr) {
912 unsigned int i = (ring->dirty + n) % ring->size;
913 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
914 struct sk_buff *skb = ring->buf[i].skb;
915
916 if (!ag71xx_desc_empty(desc)) {
917 if (pdata->is_ar7240 &&
918 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
919 schedule_work(&ag->restart_work);
920 break;
921 }
922
923 n++;
924 if (!skb)
925 continue;
926
927 dev_kfree_skb_any(skb);
928 ring->buf[i].skb = NULL;
929
930 bytes_compl += ring->buf[i].len;
931
932 sent++;
933 ring->dirty += n;
934
935 while (n > 0) {
936 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
937 n--;
938 }
939 }
940
941 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
942
943 ag->dev->stats.tx_bytes += bytes_compl;
944 ag->dev->stats.tx_packets += sent;
945
946 if (!sent)
947 return 0;
948
949 netdev_completed_queue(ag->dev, sent, bytes_compl);
950 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
951 netif_wake_queue(ag->dev);
952
953 return sent;
954 }
955
956 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
957 {
958 struct net_device *dev = ag->dev;
959 struct ag71xx_ring *ring = &ag->rx_ring;
960 int offset = ag71xx_buffer_offset(ag);
961 unsigned int pktlen_mask = ag->desc_pktlen_mask;
962 int done = 0;
963
964 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
965 dev->name, limit, ring->curr, ring->dirty);
966
967 while (done < limit) {
968 unsigned int i = ring->curr % ring->size;
969 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
970 struct sk_buff *skb;
971 int pktlen;
972 int err = 0;
973
974 if (ag71xx_desc_empty(desc))
975 break;
976
977 if ((ring->dirty + ring->size) == ring->curr) {
978 ag71xx_assert(0);
979 break;
980 }
981
982 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
983
984 pktlen = desc->ctrl & pktlen_mask;
985 pktlen -= ETH_FCS_LEN;
986
987 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
988 ag->rx_buf_size, DMA_FROM_DEVICE);
989
990 dev->stats.rx_packets++;
991 dev->stats.rx_bytes += pktlen;
992
993 skb = build_skb(ring->buf[i].rx_buf, 0);
994 if (!skb) {
995 kfree(ring->buf[i].rx_buf);
996 goto next;
997 }
998
999 skb_reserve(skb, offset);
1000 skb_put(skb, pktlen);
1001
1002 if (ag71xx_has_ar8216(ag))
1003 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1004
1005 if (err) {
1006 dev->stats.rx_dropped++;
1007 kfree_skb(skb);
1008 } else {
1009 skb->dev = dev;
1010 skb->ip_summed = CHECKSUM_NONE;
1011 skb->protocol = eth_type_trans(skb, dev);
1012 netif_receive_skb(skb);
1013 }
1014
1015 next:
1016 ring->buf[i].rx_buf = NULL;
1017 done++;
1018
1019 ring->curr++;
1020 }
1021
1022 ag71xx_ring_rx_refill(ag);
1023
1024 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1025 dev->name, ring->curr, ring->dirty, done);
1026
1027 return done;
1028 }
1029
1030 static int ag71xx_poll(struct napi_struct *napi, int limit)
1031 {
1032 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1033 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1034 struct net_device *dev = ag->dev;
1035 struct ag71xx_ring *rx_ring;
1036 unsigned long flags;
1037 u32 status;
1038 int tx_done;
1039 int rx_done;
1040
1041 pdata->ddr_flush();
1042 tx_done = ag71xx_tx_packets(ag);
1043
1044 DBG("%s: processing RX ring\n", dev->name);
1045 rx_done = ag71xx_rx_packets(ag, limit);
1046
1047 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1048
1049 rx_ring = &ag->rx_ring;
1050 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
1051 goto oom;
1052
1053 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1054 if (unlikely(status & RX_STATUS_OF)) {
1055 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1056 dev->stats.rx_fifo_errors++;
1057
1058 /* restart RX */
1059 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1060 }
1061
1062 if (rx_done < limit) {
1063 if (status & RX_STATUS_PR)
1064 goto more;
1065
1066 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1067 if (status & TX_STATUS_PS)
1068 goto more;
1069
1070 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1071 dev->name, rx_done, tx_done, limit);
1072
1073 napi_complete(napi);
1074
1075 /* enable interrupts */
1076 spin_lock_irqsave(&ag->lock, flags);
1077 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1078 spin_unlock_irqrestore(&ag->lock, flags);
1079 return rx_done;
1080 }
1081
1082 more:
1083 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1084 dev->name, rx_done, tx_done, limit);
1085 return rx_done;
1086
1087 oom:
1088 if (netif_msg_rx_err(ag))
1089 pr_info("%s: out of memory\n", dev->name);
1090
1091 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1092 napi_complete(napi);
1093 return 0;
1094 }
1095
1096 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1097 {
1098 struct net_device *dev = dev_id;
1099 struct ag71xx *ag = netdev_priv(dev);
1100 u32 status;
1101
1102 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1103 ag71xx_dump_intr(ag, "raw", status);
1104
1105 if (unlikely(!status))
1106 return IRQ_NONE;
1107
1108 if (unlikely(status & AG71XX_INT_ERR)) {
1109 if (status & AG71XX_INT_TX_BE) {
1110 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1111 dev_err(&dev->dev, "TX BUS error\n");
1112 }
1113 if (status & AG71XX_INT_RX_BE) {
1114 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1115 dev_err(&dev->dev, "RX BUS error\n");
1116 }
1117 }
1118
1119 if (likely(status & AG71XX_INT_POLL)) {
1120 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1121 DBG("%s: enable polling mode\n", dev->name);
1122 napi_schedule(&ag->napi);
1123 }
1124
1125 ag71xx_debugfs_update_int_stats(ag, status);
1126
1127 return IRQ_HANDLED;
1128 }
1129
1130 #ifdef CONFIG_NET_POLL_CONTROLLER
1131 /*
1132 * Polling 'interrupt' - used by things like netconsole to send skbs
1133 * without having to re-enable interrupts. It's not called while
1134 * the interrupt routine is executing.
1135 */
1136 static void ag71xx_netpoll(struct net_device *dev)
1137 {
1138 disable_irq(dev->irq);
1139 ag71xx_interrupt(dev->irq, dev);
1140 enable_irq(dev->irq);
1141 }
1142 #endif
1143
1144 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1145 {
1146 struct ag71xx *ag = netdev_priv(dev);
1147 unsigned int max_frame_len;
1148
1149 max_frame_len = ag71xx_max_frame_len(new_mtu);
1150 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1151 return -EINVAL;
1152
1153 if (netif_running(dev))
1154 return -EBUSY;
1155
1156 dev->mtu = new_mtu;
1157 return 0;
1158 }
1159
1160 static const struct net_device_ops ag71xx_netdev_ops = {
1161 .ndo_open = ag71xx_open,
1162 .ndo_stop = ag71xx_stop,
1163 .ndo_start_xmit = ag71xx_hard_start_xmit,
1164 .ndo_do_ioctl = ag71xx_do_ioctl,
1165 .ndo_tx_timeout = ag71xx_tx_timeout,
1166 .ndo_change_mtu = ag71xx_change_mtu,
1167 .ndo_set_mac_address = eth_mac_addr,
1168 .ndo_validate_addr = eth_validate_addr,
1169 #ifdef CONFIG_NET_POLL_CONTROLLER
1170 .ndo_poll_controller = ag71xx_netpoll,
1171 #endif
1172 };
1173
1174 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1175 {
1176 switch (mode) {
1177 case PHY_INTERFACE_MODE_MII:
1178 return "MII";
1179 case PHY_INTERFACE_MODE_GMII:
1180 return "GMII";
1181 case PHY_INTERFACE_MODE_RMII:
1182 return "RMII";
1183 case PHY_INTERFACE_MODE_RGMII:
1184 return "RGMII";
1185 case PHY_INTERFACE_MODE_SGMII:
1186 return "SGMII";
1187 default:
1188 break;
1189 }
1190
1191 return "unknown";
1192 }
1193
1194
1195 static int ag71xx_probe(struct platform_device *pdev)
1196 {
1197 struct net_device *dev;
1198 struct resource *res;
1199 struct ag71xx *ag;
1200 struct ag71xx_platform_data *pdata;
1201 int err;
1202
1203 pdata = pdev->dev.platform_data;
1204 if (!pdata) {
1205 dev_err(&pdev->dev, "no platform data specified\n");
1206 err = -ENXIO;
1207 goto err_out;
1208 }
1209
1210 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1211 dev_err(&pdev->dev, "no MII bus device specified\n");
1212 err = -EINVAL;
1213 goto err_out;
1214 }
1215
1216 dev = alloc_etherdev(sizeof(*ag));
1217 if (!dev) {
1218 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1219 err = -ENOMEM;
1220 goto err_out;
1221 }
1222
1223 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1224 return -EINVAL;
1225
1226 SET_NETDEV_DEV(dev, &pdev->dev);
1227
1228 ag = netdev_priv(dev);
1229 ag->pdev = pdev;
1230 ag->dev = dev;
1231 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1232 AG71XX_DEFAULT_MSG_ENABLE);
1233 spin_lock_init(&ag->lock);
1234
1235 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1236 if (!res) {
1237 dev_err(&pdev->dev, "no mac_base resource found\n");
1238 err = -ENXIO;
1239 goto err_out;
1240 }
1241
1242 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1243 if (!ag->mac_base) {
1244 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1245 err = -ENOMEM;
1246 goto err_free_dev;
1247 }
1248
1249 dev->irq = platform_get_irq(pdev, 0);
1250 err = request_irq(dev->irq, ag71xx_interrupt,
1251 IRQF_DISABLED,
1252 dev->name, dev);
1253 if (err) {
1254 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1255 goto err_unmap_base;
1256 }
1257
1258 dev->base_addr = (unsigned long)ag->mac_base;
1259 dev->netdev_ops = &ag71xx_netdev_ops;
1260 dev->ethtool_ops = &ag71xx_ethtool_ops;
1261
1262 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1263
1264 init_timer(&ag->oom_timer);
1265 ag->oom_timer.data = (unsigned long) dev;
1266 ag->oom_timer.function = ag71xx_oom_timer_handler;
1267
1268 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1269 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1270
1271 ag->max_frame_len = pdata->max_frame_len;
1272 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1273
1274 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1275 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1276 ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT;
1277 }
1278
1279 ag->stop_desc = dma_alloc_coherent(NULL,
1280 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1281
1282 if (!ag->stop_desc)
1283 goto err_free_irq;
1284
1285 ag->stop_desc->data = 0;
1286 ag->stop_desc->ctrl = 0;
1287 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1288
1289 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1290
1291 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1292
1293 ag71xx_dump_regs(ag);
1294
1295 ag71xx_hw_init(ag);
1296
1297 ag71xx_dump_regs(ag);
1298
1299 err = ag71xx_phy_connect(ag);
1300 if (err)
1301 goto err_free_desc;
1302
1303 err = ag71xx_debugfs_init(ag);
1304 if (err)
1305 goto err_phy_disconnect;
1306
1307 platform_set_drvdata(pdev, dev);
1308
1309 err = register_netdev(dev);
1310 if (err) {
1311 dev_err(&pdev->dev, "unable to register net device\n");
1312 goto err_debugfs_exit;
1313 }
1314
1315 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1316 dev->name, dev->base_addr, dev->irq,
1317 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1318
1319 return 0;
1320
1321 err_debugfs_exit:
1322 ag71xx_debugfs_exit(ag);
1323 err_phy_disconnect:
1324 ag71xx_phy_disconnect(ag);
1325 err_free_desc:
1326 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1327 ag->stop_desc_dma);
1328 err_free_irq:
1329 free_irq(dev->irq, dev);
1330 err_unmap_base:
1331 iounmap(ag->mac_base);
1332 err_free_dev:
1333 kfree(dev);
1334 err_out:
1335 platform_set_drvdata(pdev, NULL);
1336 return err;
1337 }
1338
1339 static int ag71xx_remove(struct platform_device *pdev)
1340 {
1341 struct net_device *dev = platform_get_drvdata(pdev);
1342
1343 if (dev) {
1344 struct ag71xx *ag = netdev_priv(dev);
1345
1346 ag71xx_debugfs_exit(ag);
1347 ag71xx_phy_disconnect(ag);
1348 unregister_netdev(dev);
1349 free_irq(dev->irq, dev);
1350 iounmap(ag->mac_base);
1351 kfree(dev);
1352 platform_set_drvdata(pdev, NULL);
1353 }
1354
1355 return 0;
1356 }
1357
1358 static struct platform_driver ag71xx_driver = {
1359 .probe = ag71xx_probe,
1360 .remove = ag71xx_remove,
1361 .driver = {
1362 .name = AG71XX_DRV_NAME,
1363 }
1364 };
1365
1366 static int __init ag71xx_module_init(void)
1367 {
1368 int ret;
1369
1370 ret = ag71xx_debugfs_root_init();
1371 if (ret)
1372 goto err_out;
1373
1374 ret = ag71xx_mdio_driver_init();
1375 if (ret)
1376 goto err_debugfs_exit;
1377
1378 ret = platform_driver_register(&ag71xx_driver);
1379 if (ret)
1380 goto err_mdio_exit;
1381
1382 return 0;
1383
1384 err_mdio_exit:
1385 ag71xx_mdio_driver_exit();
1386 err_debugfs_exit:
1387 ag71xx_debugfs_root_exit();
1388 err_out:
1389 return ret;
1390 }
1391
1392 static void __exit ag71xx_module_exit(void)
1393 {
1394 platform_driver_unregister(&ag71xx_driver);
1395 ag71xx_mdio_driver_exit();
1396 ag71xx_debugfs_root_exit();
1397 }
1398
1399 module_init(ag71xx_module_init);
1400 module_exit(ag71xx_module_exit);
1401
1402 MODULE_VERSION(AG71XX_DRV_VERSION);
1403 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1404 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1405 MODULE_LICENSE("GPL v2");
1406 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository