ar71xx: Add support for AP147-010 reference board
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.1 / 606-MIPS-ath79-pb44-fixes.patch
1 --- a/arch/mips/ath79/mach-pb44.c
2 +++ b/arch/mips/ath79/mach-pb44.c
3 @@ -8,23 +8,48 @@
4 * by the Free Software Foundation.
5 */
6
7 +#include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/i2c.h>
11 #include <linux/i2c-gpio.h>
12 #include <linux/i2c/pcf857x.h>
13 +#include <linux/i2c/pcf857x.h>
14 +#include <linux/spi/flash.h>
15 +#include <linux/spi/vsc7385.h>
16
17 -#include "machtypes.h"
18 +#include <asm/mach-ath79/ar71xx_regs.h>
19 +#include <asm/mach-ath79/ath79.h>
20 +
21 +#include "dev-eth.h"
22 #include "dev-gpio-buttons.h"
23 #include "dev-leds-gpio.h"
24 #include "dev-spi.h"
25 #include "dev-usb.h"
26 +#include "machtypes.h"
27 #include "pci.h"
28
29 #define PB44_GPIO_I2C_SCL 0
30 #define PB44_GPIO_I2C_SDA 1
31
32 +#define PB44_PCF8757_VSC7395_CS 0
33 +#define PB44_PCF8757_STEREO_CS 1
34 +#define PB44_PCF8757_SLIC_CS0 2
35 +#define PB44_PCF8757_SLIC_TEST 3
36 +#define PB44_PCF8757_SLIC_INT0 4
37 +#define PB44_PCF8757_SLIC_INT1 5
38 +#define PB44_PCF8757_SW_RESET 6
39 +#define PB44_PCF8757_SW_JUMP 8
40 +#define PB44_PCF8757_LED_JUMP1 9
41 +#define PB44_PCF8757_LED_JUMP2 10
42 +#define PB44_PCF8757_TP24 11
43 +#define PB44_PCF8757_TP25 12
44 +#define PB44_PCF8757_TP26 13
45 +#define PB44_PCF8757_TP27 14
46 +#define PB44_PCF8757_TP28 15
47 +
48 #define PB44_GPIO_EXP_BASE 16
49 +#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
50 #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
51 #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
52 #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
53 @@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
54 .cs_line = 0,
55 };
56
57 +static struct ath79_spi_controller_data pb44_spi1_data = {
58 + .cs_type = ATH79_SPI_CS_TYPE_GPIO,
59 + .cs_line = PB44_GPIO_VSC7395_CS,
60 +};
61 +
62 +static void pb44_vsc7395_reset(void)
63 +{
64 + ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
65 + udelay(10);
66 + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
67 + mdelay(50);
68 +}
69 +
70 +static struct vsc7385_platform_data pb44_vsc7395_data = {
71 + .reset = pb44_vsc7395_reset,
72 + .ucode_name = "vsc7395_ucode_pb44.bin",
73 + .mac_cfg = {
74 + .tx_ipg = 6,
75 + .bit2 = 1,
76 + .clk_sel = 0,
77 + },
78 +};
79 +
80 +static const char *pb44_part_probes[] = {
81 + "RedBoot",
82 + NULL,
83 +};
84 +
85 +static struct flash_platform_data pb44_flash_data = {
86 + .part_probes = pb44_part_probes,
87 +};
88 +
89 static struct spi_board_info pb44_spi_info[] = {
90 {
91 .bus_num = 0,
92 .chip_select = 0,
93 .max_speed_hz = 25000000,
94 .modalias = "m25p64",
95 + .platform_data = &pb44_flash_data,
96 .controller_data = &pb44_spi0_data,
97 },
98 + {
99 + .bus_num = 0,
100 + .chip_select = 1,
101 + .max_speed_hz = 25000000,
102 + .modalias = "spi-vsc7385",
103 + .platform_data = &pb44_vsc7395_data,
104 + .controller_data = &pb44_spi1_data,
105 + }
106 };
107
108 static struct ath79_spi_platform_data pb44_spi_data = {
109 .bus_num = 0,
110 - .num_chipselect = 1,
111 + .num_chipselect = 2,
112 };
113
114 +#define PB44_WAN_PHYMASK BIT(0)
115 +#define PB44_LAN_PHYMASK 0
116 +#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
117 +
118 static void __init pb44_init(void)
119 {
120 i2c_register_board_info(0, pb44_i2c_board_info,
121 @@ -122,6 +192,22 @@ static void __init pb44_init(void)
122 ARRAY_SIZE(pb44_spi_info));
123 ath79_register_usb();
124 ath79_register_pci();
125 +
126 + ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
127 +
128 + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
129 + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
130 + ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
131 +
132 + ath79_register_eth(0);
133 +
134 + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
135 + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
136 + ath79_eth1_data.speed = SPEED_1000;
137 + ath79_eth1_data.duplex = DUPLEX_FULL;
138 + ath79_eth1_pll_data.pll_1000 = 0x110000;
139 +
140 + ath79_register_eth(1);
141 }
142
143 MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
144 --- a/arch/mips/ath79/Kconfig
145 +++ b/arch/mips/ath79/Kconfig
146 @@ -58,6 +58,7 @@ config ATH79_MACH_DB120
147 config ATH79_MACH_PB44
148 bool "Atheros PB44 reference board"
149 select SOC_AR71XX
150 + select ATH79_DEV_ETH
151 select ATH79_DEV_GPIO_BUTTONS
152 select ATH79_DEV_LEDS_GPIO
153 select ATH79_DEV_SPI