target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch

   1 --- a/arch/mips/ath79/common.h
   2 +++ b/arch/mips/ath79/common.h
   3 @@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask
   4  void ath79_gpio_function_disable(u32 mask);
   5  void ath79_gpio_function_setup(u32 set, u32 clear);
   6  void ath79_gpio_output_select(unsigned gpio, u8 val);
   7 +int ath79_gpio_direction_select(unsigned gpio, bool oe);
   8  void ath79_gpio_init(void);
   9
  10  #endif /* __ATH79_COMMON_H */
  11 --- a/arch/mips/ath79/gpio.c
  12 +++ b/arch/mips/ath79/gpio.c
  13 @@ -130,6 +130,30 @@ static int ar934x_gpio_direction_output(
  14         return 0;
  15  }
  16
  17 +int ath79_gpio_direction_select(unsigned gpio, bool oe)
  18 +{
  19 +       void __iomem *base = ath79_gpio_base;
  20 +       unsigned long flags;
  21 +       bool ieq_1 = (soc_is_ar934x() ||
  22 +                       soc_is_qca953x());
  23 +
  24 +       if (gpio >= ath79_gpio_count)
  25 +               return -1;
  26 +
  27 +       spin_lock_irqsave(&ath79_gpio_lock, flags);
  28 +
  29 +       if ((ieq_1 && oe) || (!ieq_1 && !oe))
  30 +               __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
  31 +                               base + AR71XX_GPIO_REG_OE);
  32 +       else
  33 +               __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
  34 +                               base + AR71XX_GPIO_REG_OE);
  35 +
  36 +       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
  37 +
  38 +       return 0;
  39 +}
  40 +
  41  static struct gpio_chip ath79_gpio_chip = {
  42         .label                  = "ath79",
  43         .get                    = ath79_gpio_get_value,