ar71xx: add v4.14 support
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.14 / 106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch
1 From 460f382c278fe66059a773c41cbcd0db86d53983 Mon Sep 17 00:00:00 2001
2 From: Mathias Kresin <dev@kresin.me>
3 Date: Thu, 13 Apr 2017 09:47:42 +0200
4 Subject: [PATCH] MIPS: pci-ar724x: get PCIe controller out of reset
5
6 The ar724x pci driver expects the PCIe controller to be brought out of
7 reset by the bootloader.
8
9 At least the AVM Fritz 300E bootloader doesn't take care of releasing
10 the different PCIe controller related resets which causes an endless
11 hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
12 Application Control register (0x180f0000) is read from.
13
14 Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
15 host controller is still in reset during probing.
16
17 The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
18 set to ready. It has been shown that 10ms might not be enough time if
19 PCIe should be used right after setting the bit. During my tests it
20 took up to 20ms till the link was up. Giving the link up to 100ms
21 should work for all cases.
22
23 Signed-off-by: Mathias Kresin <dev@kresin.me>
24 ---
25 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++
26 arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++
27 2 files changed, 45 insertions(+)
28
29 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
30 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
31 @@ -169,6 +169,9 @@
32 #define AR724X_PLL_REG_CPU_CONFIG 0x00
33 #define AR724X_PLL_REG_PCIE_CONFIG 0x10
34
35 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
36 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
37 +
38 #define AR724X_PLL_FB_SHIFT 0
39 #define AR724X_PLL_FB_MASK 0x3ff
40 #define AR724X_PLL_REF_DIV_SHIFT 10
41 --- a/arch/mips/pci/pci-ar724x.c
42 +++ b/arch/mips/pci/pci-ar724x.c
43 @@ -12,14 +12,18 @@
44 #include <linux/irq.h>
45 #include <linux/pci.h>
46 #include <linux/init.h>
47 +#include <linux/delay.h>
48 #include <linux/platform_device.h>
49 #include <asm/mach-ath79/ath79.h>
50 #include <asm/mach-ath79/ar71xx_regs.h>
51
52 +#define AR724X_PCI_REG_APP 0x0
53 #define AR724X_PCI_REG_RESET 0x18
54 #define AR724X_PCI_REG_INT_STATUS 0x4c
55 #define AR724X_PCI_REG_INT_MASK 0x50
56
57 +#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
58 +
59 #define AR724X_PCI_RESET_LINK_UP BIT(0)
60
61 #define AR724X_PCI_INT_DEV0 BIT(14)
62 @@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
63 apc);
64 }
65
66 +static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
67 +{
68 + u32 ppl, app;
69 + int wait = 0;
70 +
71 + /* deassert PCIe host controller and PCIe PHY reset */
72 + ath79_device_reset_clear(AR724X_RESET_PCIE);
73 + ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
74 +
75 + /* remove the reset of the PCIE PLL */
76 + ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
77 + ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
78 + ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
79 +
80 + /* deassert bypass for the PCIE PLL */
81 + ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
82 + ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
83 + ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
84 +
85 + /* set PCIE Application Control to ready */
86 + app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
87 + app |= AR724X_PCI_APP_LTSSM_ENABLE;
88 + __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
89 +
90 + /* wait up to 100ms for PHY link up */
91 + do {
92 + mdelay(10);
93 + wait++;
94 + } while (wait < 10 && !ar724x_pci_check_link(apc));
95 +}
96 +
97 static int ar724x_pci_probe(struct platform_device *pdev)
98 {
99 struct ar724x_pci_controller *apc;
100 @@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
101 apc->pci_controller.io_resource = &apc->io_res;
102 apc->pci_controller.mem_resource = &apc->mem_res;
103
104 + /*
105 + * Do the full PCIE Root Complex Initialization Sequence if the PCIe
106 + * host controller is in reset.
107 + */
108 + if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
109 + ar724x_pci_hw_init(apc);
110 +
111 apc->link_up = ar724x_pci_check_link(apc);
112 if (!apc->link_up)
113 dev_warn(&pdev->dev, "PCIe link is down\n");