target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch

   1 From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
   2 Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
   3 From: Matthias Schiffer <mschiffer@universe-factory.net>
   4 Date: Sat, 29 Mar 2014 20:26:08 +0100
   5 Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
   6
   7 Note that the clock calculation looks very similar to the QCA955x, but the
   8 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
   9 ---
  10  arch/mips/ath79/Kconfig                        |  6 +-
  11  arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
  12  arch/mips/ath79/common.c                       |  4 ++
  13  arch/mips/ath79/dev-common.c                   |  1 +
  14  arch/mips/ath79/dev-wmac.c                     | 20 +++++++
  15  arch/mips/ath79/early_printk.c                 |  1 +
  16  arch/mips/ath79/gpio.c                         |  4 +-
  17  arch/mips/ath79/irq.c                          |  4 ++
  18  arch/mips/ath79/setup.c                        |  8 ++-
  19  arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
  20  arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
  21  11 files changed, 182 insertions(+), 3 deletions(-)
  22
  23 --- a/arch/mips/ath79/Kconfig
  24 +++ b/arch/mips/ath79/Kconfig
  25 @@ -105,6 +105,10 @@ config SOC_AR934X
  26         select PCI_AR724X if PCI
  27         def_bool n
  28
  29 +config SOC_QCA953X
  30 +       select USB_ARCH_HAS_EHCI
  31 +       def_bool n
  32 +
  33  config SOC_QCA955X
  34         select HW_HAS_PCI
  35         select PCI_AR724X if PCI
  36 @@ -144,7 +148,7 @@ config ATH79_DEV_USB
  37         def_bool n
  38
  39  config ATH79_DEV_WMAC
  40 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  41 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  42         def_bool n
  43
  44  config ATH79_NVRAM
  45 --- a/arch/mips/ath79/clock.c
  46 +++ b/arch/mips/ath79/clock.c
  47 @@ -357,6 +357,87 @@ static void __init ar934x_clocks_init(vo
  48         iounmap(dpll_base);
  49  }
  50
  51 +static void __init qca953x_clocks_init(void)
  52 +{
  53 +       unsigned long ref_rate;
  54 +       unsigned long cpu_rate;
  55 +       unsigned long ddr_rate;
  56 +       unsigned long ahb_rate;
  57 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  58 +       u32 cpu_pll, ddr_pll;
  59 +
  60 +       /* QCA953X only supports 25MHz ref_clk */
  61 +       ref_rate = 25 * 1000 * 1000;
  62 +
  63 +       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  64 +       out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  65 +                 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  66 +       ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  67 +                 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  68 +       nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  69 +              QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  70 +       frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  71 +              QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  72 +
  73 +       cpu_pll = nint * ref_rate / ref_div;
  74 +       cpu_pll += frac * (ref_rate >> 6) / ref_div;
  75 +       cpu_pll /= (1 << out_div);
  76 +
  77 +       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  78 +       out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  79 +                 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  80 +       ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  81 +                 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  82 +       nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  83 +              QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  84 +       frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  85 +              QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  86 +
  87 +       ddr_pll = nint * ref_rate / ref_div;
  88 +       ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
  89 +       ddr_pll /= (1 << out_div);
  90 +
  91 +       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  92 +
  93 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  94 +                 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  95 +
  96 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  97 +               cpu_rate = ref_rate;
  98 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  99 +               cpu_rate = cpu_pll / (postdiv + 1);
 100 +       else
 101 +               cpu_rate = ddr_pll / (postdiv + 1);
 102 +
 103 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 104 +                 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 105 +
 106 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 107 +               ddr_rate = ref_rate;
 108 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 109 +               ddr_rate = ddr_pll / (postdiv + 1);
 110 +       else
 111 +               ddr_rate = cpu_pll / (postdiv + 1);
 112 +
 113 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 114 +                 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 115 +
 116 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 117 +               ahb_rate = ref_rate;
 118 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 119 +               ahb_rate = ddr_pll / (postdiv + 1);
 120 +       else
 121 +               ahb_rate = cpu_pll / (postdiv + 1);
 122 +
 123 +       ath79_add_sys_clkdev("ref", ref_rate);
 124 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 125 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 126 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 127 +
 128 +       clk_add_alias("wdt", NULL, "ref", NULL);
 129 +       clk_add_alias("uart", NULL, "ref", NULL);
 130 +}
 131 +
 132  static void __init qca955x_clocks_init(void)
 133  {
 134         unsigned long ref_rate;
 135 @@ -452,6 +533,8 @@ void __init ath79_clocks_init(void)
 136                 ar933x_clocks_init();
 137         else if (soc_is_ar934x())
 138                 ar934x_clocks_init();
 139 +       else if (soc_is_qca953x())
 140 +               qca953x_clocks_init();
 141         else if (soc_is_qca955x())
 142                 qca955x_clocks_init();
 143         else
 144 --- a/arch/mips/ath79/common.c
 145 +++ b/arch/mips/ath79/common.c
 146 @@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
 147                 reg = AR933X_RESET_REG_RESET_MODULE;
 148         else if (soc_is_ar934x())
 149                 reg = AR934X_RESET_REG_RESET_MODULE;
 150 +       else if (soc_is_qca953x())
 151 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 152         else if (soc_is_qca955x())
 153                 reg = QCA955X_RESET_REG_RESET_MODULE;
 154         else
 155 @@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
 156                 reg = AR933X_RESET_REG_RESET_MODULE;
 157         else if (soc_is_ar934x())
 158                 reg = AR934X_RESET_REG_RESET_MODULE;
 159 +       else if (soc_is_qca953x())
 160 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 161         else if (soc_is_qca955x())
 162                 reg = QCA955X_RESET_REG_RESET_MODULE;
 163         else
 164 --- a/arch/mips/ath79/dev-common.c
 165 +++ b/arch/mips/ath79/dev-common.c
 166 @@ -94,6 +94,7 @@ void __init ath79_register_uart(void)
 167             soc_is_ar724x() ||
 168             soc_is_ar913x() ||
 169             soc_is_ar934x() ||
 170 +           soc_is_qca953x() ||
 171             soc_is_qca955x()) {
 172                 ath79_uart_data[0].uartclk = uart_clk_rate;
 173                 platform_device_register(&ath79_uart_device);
 174 @@ -157,6 +158,9 @@ void __init ath79_gpio_init(void)
 175         } else if (soc_is_ar934x()) {
 176                 ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
 177                 ath79_gpio_pdata.oe_inverted = 1;
 178 +       } else if (soc_is_qca953x()) {
 179 +               ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
 180 +               ath79_gpio_pdata.oe_inverted = 1;
 181         } else if (soc_is_qca955x()) {
 182                 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
 183                 ath79_gpio_pdata.oe_inverted = 1;
 184 --- a/arch/mips/ath79/dev-usb.c
 185 +++ b/arch/mips/ath79/dev-usb.c
 186 @@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
 187                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 188  }
 189
 190 +static void __init qca953x_usb_setup(void)
 191 +{
 192 +       u32 bootstrap;
 193 +
 194 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 195 +
 196 +       ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
 197 +       udelay(1000);
 198 +
 199 +       ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
 200 +       udelay(1000);
 201 +
 202 +       ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
 203 +       udelay(1000);
 204 +
 205 +       ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
 206 +       udelay(1000);
 207 +
 208 +       ath79_usb_register("ehci-platform", -1,
 209 +                          QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
 210 +                          ATH79_CPU_IRQ(3),
 211 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 212 +}
 213 +
 214  static void qca955x_usb_reset_notifier(struct platform_device *pdev)
 215  {
 216         u32 base;
 217 @@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
 218                 ar933x_usb_setup();
 219         else if (soc_is_ar934x())
 220                 ar934x_usb_setup();
 221 +       else if (soc_is_qca953x())
 222 +               qca953x_usb_setup();
 223         else if (soc_is_qca955x())
 224                 qca955x_usb_setup();
 225         else
 226 --- a/arch/mips/ath79/dev-wmac.c
 227 +++ b/arch/mips/ath79/dev-wmac.c
 228 @@ -100,7 +100,7 @@ static int ar933x_wmac_reset(void)
 229         return -ETIMEDOUT;
 230  }
 231
 232 -static int ar933x_r1_get_wmac_revision(void)
 233 +static int ar93xx_get_soc_revision(void)
 234  {
 235         return ath79_soc_rev;
 236  }
 237 @@ -125,7 +125,7 @@ static void __init ar933x_wmac_setup(voi
 238                 ath79_wmac_data.is_clk_25mhz = true;
 239
 240         if (ath79_soc_rev == 1)
 241 -               ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
 242 +               ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 243
 244         ath79_wmac_data.external_reset = ar933x_wmac_reset;
 245  }
 246 @@ -150,6 +150,21 @@ static void ar934x_wmac_setup(void)
 247         ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 248  }
 249
 250 +static void qca953x_wmac_setup(void)
 251 +{
 252 +       ath79_wmac_device.name = "qca953x_wmac";
 253 +
 254 +       ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 255 +       ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
 256 +       ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
 257 +       ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
 258 +
 259 +       /* QCA953X only supports 25MHz ref_clk */
 260 +       ath79_wmac_data.is_clk_25mhz = true;
 261 +
 262 +       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 263 +}
 264 +
 265  static void qca955x_wmac_setup(void)
 266  {
 267         u32 t;
 268 @@ -379,6 +394,8 @@ void __init ath79_register_wmac(u8 *cal_
 269                 ar933x_wmac_setup();
 270         else if (soc_is_ar934x())
 271                 ar934x_wmac_setup();
 272 +       else if (soc_is_qca953x())
 273 +               qca953x_wmac_setup();
 274         else if (soc_is_qca955x())
 275                 qca955x_wmac_setup();
 276         else
 277 --- a/arch/mips/ath79/early_printk.c
 278 +++ b/arch/mips/ath79/early_printk.c
 279 @@ -116,6 +116,8 @@ static void prom_putchar_init(void)
 280         case REV_ID_MAJOR_AR9341:
 281         case REV_ID_MAJOR_AR9342:
 282         case REV_ID_MAJOR_AR9344:
 283 +       case REV_ID_MAJOR_QCA9533:
 284 +       case REV_ID_MAJOR_QCA9533_V2:
 285         case REV_ID_MAJOR_QCA9556:
 286         case REV_ID_MAJOR_QCA9558:
 287                 _prom_putchar = prom_putchar_ar71xx;
 288 --- a/arch/mips/ath79/gpio.c
 289 +++ b/arch/mips/ath79/gpio.c
 290 @@ -31,7 +31,7 @@ static void __iomem *ath79_gpio_get_func
 291             soc_is_ar913x() ||
 292             soc_is_ar933x())
 293                 reg = AR71XX_GPIO_REG_FUNC;
 294 -       else if (soc_is_ar934x())
 295 +       else if (soc_is_ar934x() || soc_is_qca953x())
 296                 reg = AR934X_GPIO_REG_FUNC;
 297         else
 298                 BUG();
 299 @@ -64,7 +64,7 @@ void __init ath79_gpio_output_select(uns
 300         unsigned int reg;
 301         u32 t, s;
 302
 303 -       BUG_ON(!soc_is_ar934x());
 304 +       BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
 305
 306         if (gpio >= AR934X_GPIO_COUNT)
 307                 return;
 308 --- a/arch/mips/ath79/irq.c
 309 +++ b/arch/mips/ath79/irq.c
 310 @@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void)
 311         irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
 312  }
 313
 314 +static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
 315 +{
 316 +       u32 status;
 317 +
 318 +       status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
 319 +
 320 +       if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
 321 +               ath79_ddr_wb_flush(3);
 322 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 323 +       } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
 324 +               ath79_ddr_wb_flush(4);
 325 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 326 +       } else {
 327 +               spurious_interrupt();
 328 +       }
 329 +}
 330 +
 331 +static void qca953x_irq_init(void)
 332 +{
 333 +       int i;
 334 +
 335 +       for (i = ATH79_IP2_IRQ_BASE;
 336 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 337 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 338 +
 339 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
 340 +}
 341 +
 342  static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
 343  {
 344         u32 status;
 345 @@ -143,7 +171,7 @@ void __init arch_init_irq(void)
 346             soc_is_ar913x() || soc_is_ar933x()) {
 347                 irq_wb_chan2 = 3;
 348                 irq_wb_chan3 = 2;
 349 -       } else if (soc_is_ar934x()) {
 350 +       } else if (soc_is_ar934x() || soc_is_qca953x()) {
 351                 irq_wb_chan3 = 2;
 352         }
 353
 354 @@ -154,6 +182,7 @@ void __init arch_init_irq(void)
 355         else if (soc_is_ar724x() ||
 356                  soc_is_ar933x() ||
 357                  soc_is_ar934x() ||
 358 +                soc_is_qca953x() ||
 359                  soc_is_qca955x())
 360                 misc_is_ar71xx = false;
 361         else
 362 @@ -164,6 +193,8 @@ void __init arch_init_irq(void)
 363
 364         if (soc_is_ar934x())
 365                 ar934x_ip2_irq_init();
 366 +       else if (soc_is_qca953x())
 367 +               qca953x_irq_init();
 368         else if (soc_is_qca955x())
 369                 qca955x_irq_init();
 370  }
 371 --- a/arch/mips/ath79/setup.c
 372 +++ b/arch/mips/ath79/setup.c
 373 @@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
 374         u32 major;
 375         u32 minor;
 376         u32 rev = 0;
 377 +       u32 ver = 1;
 378
 379         id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
 380         major = id & REV_ID_MAJOR_MASK;
 381 @@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
 382                 rev = id & AR934X_REV_ID_REVISION_MASK;
 383                 break;
 384
 385 +       case REV_ID_MAJOR_QCA9533_V2:
 386 +               ver = 2;
 387 +               ath79_soc_rev = 2;
 388 +               /* drop through */
 389 +
 390 +       case REV_ID_MAJOR_QCA9533:
 391 +               ath79_soc = ATH79_SOC_QCA9533;
 392 +               chip = "9533";
 393 +               rev = id & QCA953X_REV_ID_REVISION_MASK;
 394 +               break;
 395 +
 396         case REV_ID_MAJOR_QCA9556:
 397                 ath79_soc = ATH79_SOC_QCA9556;
 398                 chip = "9556";
 399 @@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type
 400                 panic("ath79: unknown SoC, id:0x%08x", id);
 401         }
 402
 403 -       ath79_soc_rev = rev;
 404 +       if (ver == 1)
 405 +               ath79_soc_rev = rev;
 406
 407 -       if (soc_is_qca955x())
 408 -               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 409 -                       chip, rev);
 410 +       if (soc_is_qca953x() || soc_is_qca955x())
 411 +               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 412 +                       chip, ver, rev);
 413         else
 414                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 415         pr_info("SoC: %s\n", ath79_sys_type);
 416 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 417 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 418 @@ -105,6 +105,21 @@
 419  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
 420  #define AR934X_SRIF_SIZE       0x1000
 421
 422 +#define QCA953X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
 423 +#define QCA953X_GMAC_SIZE      0x14
 424 +#define QCA953X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 425 +#define QCA953X_WMAC_SIZE      0x20000
 426 +#define QCA953X_EHCI_BASE      0x1b000000
 427 +#define QCA953X_EHCI_SIZE      0x200
 428 +#define QCA953X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
 429 +#define QCA953X_SRIF_SIZE      0x1000
 430 +
 431 +#define QCA953X_PCI_CFG_BASE0  0x14000000
 432 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
 433 +#define QCA953X_PCI_CRP_BASE0  (AR71XX_APB_BASE + 0x000c0000)
 434 +#define QCA953X_PCI_MEM_BASE0  0x10000000
 435 +#define QCA953X_PCI_MEM_SIZE   0x02000000
 436 +
 437  #define QCA955X_PCI_MEM_BASE0  0x10000000
 438  #define QCA955X_PCI_MEM_BASE1  0x12000000
 439  #define QCA955X_PCI_MEM_SIZE   0x02000000
 440 @@ -180,6 +195,12 @@
 441  #define AR934X_OTP_INTF3_ADDRESS                       0x3100c
 442  #define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS       0x31034
 443
 444 +#define QCA953X_DDR_REG_FLUSH_GE0      0x9c
 445 +#define QCA953X_DDR_REG_FLUSH_GE1      0xa0
 446 +#define QCA953X_DDR_REG_FLUSH_USB      0xa4
 447 +#define QCA953X_DDR_REG_FLUSH_PCIE     0xa8
 448 +#define QCA953X_DDR_REG_FLUSH_WMAC     0xac
 449 +
 450  /*
 451   * PLL block
 452   */
 453 @@ -289,6 +310,44 @@
 454
 455  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
 456
 457 +#define QCA953X_PLL_CPU_CONFIG_REG             0x00
 458 +#define QCA953X_PLL_DDR_CONFIG_REG             0x04
 459 +#define QCA953X_PLL_CLK_CTRL_REG               0x08
 460 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG   0x24
 461 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG       0x2c
 462 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG      0x48
 463 +
 464 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 465 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 466 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT      6
 467 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK       0x3f
 468 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT    12
 469 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK     0x1f
 470 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT    19
 471 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK     0x7
 472 +
 473 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT     0
 474 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK      0x3ff
 475 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT      10
 476 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK       0x3f
 477 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT    16
 478 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK     0x1f
 479 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT    23
 480 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK     0x7
 481 +
 482 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 483 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 484 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 485 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 486 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 487 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 488 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 489 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 490 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 491 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL                BIT(20)
 492 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 493 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 494 +
 495  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
 496  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
 497  #define QCA955X_PLL_CLK_CTRL_REG               0x08
 498 @@ -365,6 +424,10 @@
 499  #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 500  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
 501
 502 +#define QCA953X_RESET_REG_RESET_MODULE         0x1c
 503 +#define QCA953X_RESET_REG_BOOTSTRAP            0xb0
 504 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
 505 +
 506  #define QCA955X_RESET_REG_RESET_MODULE         0x1c
 507  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 508  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
 509 @@ -460,6 +523,27 @@
 510  #define AR934X_RESET_MBOX              BIT(1)
 511  #define AR934X_RESET_I2S               BIT(0)
 512
 513 +#define QCA953X_RESET_USB_EXT_PWR      BIT(29)
 514 +#define QCA953X_RESET_EXTERNAL         BIT(28)
 515 +#define QCA953X_RESET_RTC              BIT(27)
 516 +#define QCA953X_RESET_FULL_CHIP                BIT(24)
 517 +#define QCA953X_RESET_GE1_MDIO         BIT(23)
 518 +#define QCA953X_RESET_GE0_MDIO         BIT(22)
 519 +#define QCA953X_RESET_CPU_NMI          BIT(21)
 520 +#define QCA953X_RESET_CPU_COLD         BIT(20)
 521 +#define QCA953X_RESET_DDR              BIT(16)
 522 +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
 523 +#define QCA953X_RESET_GE1_MAC          BIT(13)
 524 +#define QCA953X_RESET_ETH_SWITCH_ANALOG        BIT(12)
 525 +#define QCA953X_RESET_USB_PHY_ANALOG   BIT(11)
 526 +#define QCA953X_RESET_GE0_MAC          BIT(9)
 527 +#define QCA953X_RESET_ETH_SWITCH       BIT(8)
 528 +#define QCA953X_RESET_PCIE_PHY         BIT(7)
 529 +#define QCA953X_RESET_PCIE             BIT(6)
 530 +#define QCA953X_RESET_USB_HOST         BIT(5)
 531 +#define QCA953X_RESET_USB_PHY          BIT(4)
 532 +#define QCA953X_RESET_USBSUS_OVERRIDE  BIT(3)
 533 +
 534  #define QCA955X_RESET_HOST             BIT(31)
 535  #define QCA955X_RESET_SLIC             BIT(30)
 536  #define QCA955X_RESET_HDMA             BIT(29)
 537 @@ -513,6 +597,13 @@
 538  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 539  #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 540
 541 +#define QCA953X_BOOTSTRAP_SW_OPTION2   BIT(12)
 542 +#define QCA953X_BOOTSTRAP_SW_OPTION1   BIT(11)
 543 +#define QCA953X_BOOTSTRAP_EJTAG_MODE   BIT(5)
 544 +#define QCA953X_BOOTSTRAP_REF_CLK      BIT(4)
 545 +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 546 +#define QCA953X_BOOTSTRAP_DDR1         BIT(0)
 547 +
 548  #define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 549
 550  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 551 @@ -533,6 +624,24 @@
 552          AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
 553          AR934X_PCIE_WMAC_INT_PCIE_RC3)
 554
 555 +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
 556 +#define QCA953X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
 557 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
 558 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP                BIT(3)
 559 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC          BIT(4)
 560 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0         BIT(5)
 561 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1         BIT(6)
 562 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2         BIT(7)
 563 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3         BIT(8)
 564 +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
 565 +       (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
 566 +        QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
 567 +
 568 +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
 569 +       (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
 570 +        QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
 571 +        QCA953X_PCIE_WMAC_INT_PCIE_RC3)
 572 +
 573  #define QCA955X_EXT_INT_WMAC_MISC              BIT(0)
 574  #define QCA955X_EXT_INT_WMAC_TX                        BIT(1)
 575  #define QCA955X_EXT_INT_WMAC_RXLP              BIT(2)
 576 @@ -575,6 +684,8 @@
 577  #define REV_ID_MAJOR_AR9341            0x0120
 578  #define REV_ID_MAJOR_AR9342            0x1120
 579  #define REV_ID_MAJOR_AR9344            0x2120
 580 +#define REV_ID_MAJOR_QCA9533           0x0140
 581 +#define REV_ID_MAJOR_QCA9533_V2                0x0160
 582  #define REV_ID_MAJOR_QCA9556           0x0130
 583  #define REV_ID_MAJOR_QCA9558           0x1130
 584
 585 @@ -597,6 +708,8 @@
 586
 587  #define AR934X_REV_ID_REVISION_MASK    0xf
 588
 589 +#define QCA953X_REV_ID_REVISION_MASK   0xf
 590 +
 591  #define QCA955X_REV_ID_REVISION_MASK   0xf
 592
 593  /*
 594 @@ -644,6 +757,25 @@
 595  #define AR934X_GPIO_REG_OUT_FUNC5      0x40
 596  #define AR934X_GPIO_REG_FUNC           0x6c
 597
 598 +#define QCA953X_GPIO_REG_OUT_FUNC0     0x2c
 599 +#define QCA953X_GPIO_REG_OUT_FUNC1     0x30
 600 +#define QCA953X_GPIO_REG_OUT_FUNC2     0x34
 601 +#define QCA953X_GPIO_REG_OUT_FUNC3     0x38
 602 +#define QCA953X_GPIO_REG_OUT_FUNC4     0x3c
 603 +#define QCA953X_GPIO_REG_IN_ENABLE0    0x44
 604 +#define QCA953X_GPIO_REG_FUNC          0x6c
 605 +
 606 +#define QCA953X_GPIO_OUT_MUX_SPI_CS1           10
 607 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2           11
 608 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0           9
 609 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK           8
 610 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI          12
 611 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1         41
 612 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2         42
 613 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3         43
 614 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4         44
 615 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5         45
 616 +
 617  #define QCA955X_GPIO_REG_OUT_FUNC0     0x2c
 618  #define QCA955X_GPIO_REG_OUT_FUNC1     0x30
 619  #define QCA955X_GPIO_REG_OUT_FUNC2     0x34
 620 @@ -658,6 +790,7 @@
 621  #define AR913X_GPIO_COUNT              22
 622  #define AR933X_GPIO_COUNT              30
 623  #define AR934X_GPIO_COUNT              23
 624 +#define QCA953X_GPIO_COUNT             18
 625  #define QCA955X_GPIO_COUNT             24
 626
 627  /*
 628 @@ -681,6 +814,24 @@
 629  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
 630  #define AR934X_SRIF_DPLL2_OUTDIV_MASK  0x7
 631
 632 +#define QCA953X_SRIF_CPU_DPLL1_REG     0x1c0
 633 +#define QCA953X_SRIF_CPU_DPLL2_REG     0x1c4
 634 +#define QCA953X_SRIF_CPU_DPLL3_REG     0x1c8
 635 +
 636 +#define QCA953X_SRIF_DDR_DPLL1_REG     0x240
 637 +#define QCA953X_SRIF_DDR_DPLL2_REG     0x244
 638 +#define QCA953X_SRIF_DDR_DPLL3_REG     0x248
 639 +
 640 +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT        27
 641 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
 642 +#define QCA953X_SRIF_DPLL1_NINT_SHIFT  18
 643 +#define QCA953X_SRIF_DPLL1_NINT_MASK   0x1ff
 644 +#define QCA953X_SRIF_DPLL1_NFRAC_MASK  0x0003ffff
 645 +
 646 +#define QCA953X_SRIF_DPLL2_LOCAL_PLL   BIT(30)
 647 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT        13
 648 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
 649 +
 650  #define AR71XX_GPIO_FUNC_STEREO_EN             BIT(17)
 651  #define AR71XX_GPIO_FUNC_SLIC_EN               BIT(16)
 652  #define AR71XX_GPIO_FUNC_SPI_CS2_EN            BIT(13)
 653 @@ -887,6 +1038,16 @@
 654  #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
 655
 656  /*
 657 + * QCA953X GMAC Interface
 658 + */
 659 +#define QCA953X_GMAC_REG_ETH_CFG               0x00
 660 +
 661 +#define QCA953X_ETH_CFG_SW_ONLY_MODE           BIT(6)
 662 +#define QCA953X_ETH_CFG_SW_PHY_SWAP            BIT(7)
 663 +#define QCA953X_ETH_CFG_SW_APB_ACCESS          BIT(9)
 664 +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
 665 +
 666 +/*
 667   * QCA955X GMAC Interface
 668   */
 669
 670 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 671 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 672 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 673         ATH79_SOC_AR9341,
 674         ATH79_SOC_AR9342,
 675         ATH79_SOC_AR9344,
 676 +       ATH79_SOC_QCA9533,
 677         ATH79_SOC_QCA9556,
 678         ATH79_SOC_QCA9558,
 679  };
 680 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
 681         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 682  }
 683
 684 +static inline int soc_is_qca9533(void)
 685 +{
 686 +       return ath79_soc == ATH79_SOC_QCA9533;
 687 +}
 688 +
 689 +static inline int soc_is_qca953x(void)
 690 +{
 691 +       return soc_is_qca9533();
 692 +}
 693 +
 694  static inline int soc_is_qca9556(void)
 695  {
 696         return ath79_soc == ATH79_SOC_QCA9556;