projects / openwrt / openwrt.git / blob
? search:


56dea98fe555d5061eb0420ed53d4d22de6fc1b9
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.14 / 621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
1 Index: linux-4.14.61/arch/mips/ath79/Kconfig
2 ===================================================================
3 --- linux-4.14.61.orig/arch/mips/ath79/Kconfig
4 +++ linux-4.14.61/arch/mips/ath79/Kconfig
5 @@ -114,6 +114,12 @@ config SOC_QCA955X
6 select PCI_AR724X if PCI
7 def_bool n
8
9 +config SOC_QCA956X
10 + select USB_ARCH_HAS_EHCI
11 + select HW_HAS_PCI
12 + select PCI_AR724X if PCI
13 + def_bool n
14 +
15 config ATH79_DEV_M25P80
16 select ATH79_DEV_SPI
17 def_bool n
18 @@ -148,7 +154,7 @@ config ATH79_DEV_USB
19 def_bool n
20
21 config ATH79_DEV_WMAC
22 - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
23 + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
24 def_bool n
25
26 config ATH79_NVRAM
27 Index: linux-4.14.61/arch/mips/ath79/clock.c
28 ===================================================================
29 --- linux-4.14.61.orig/arch/mips/ath79/clock.c
30 +++ linux-4.14.61/arch/mips/ath79/clock.c
31 @@ -523,6 +523,100 @@ static void __init qca955x_clocks_init(v
32 clk_add_alias("uart", NULL, "ref", NULL);
33 }
34
35 +static void __init qca956x_clocks_init(void)
36 +{
37 + unsigned long ref_rate;
38 + unsigned long cpu_rate;
39 + unsigned long ddr_rate;
40 + unsigned long ahb_rate;
41 + u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
42 + u32 cpu_pll, ddr_pll;
43 + u32 bootstrap;
44 +
45 + bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
46 + if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
47 + ref_rate = 40 * 1000 * 1000;
48 + else
49 + ref_rate = 25 * 1000 * 1000;
50 +
51 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
52 + out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
53 + QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
54 + ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
55 + QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
56 +
57 + pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
58 + nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
59 + QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
60 + hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
61 + QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
62 + lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
63 + QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
64 +
65 + cpu_pll = nint * ref_rate / ref_div;
66 + cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
67 + cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
68 + cpu_pll /= (1 << out_div);
69 +
70 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
71 + out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
72 + QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
73 + ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
74 + QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
75 + pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
76 + nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
77 + QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
78 + hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
79 + QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
80 + lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
81 + QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
82 +
83 + ddr_pll = nint * ref_rate / ref_div;
84 + ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
85 + ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
86 + ddr_pll /= (1 << out_div);
87 +
88 + clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
89 +
90 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
91 + QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
92 +
93 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
94 + cpu_rate = ref_rate;
95 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
96 + cpu_rate = ddr_pll / (postdiv + 1);
97 + else
98 + cpu_rate = cpu_pll / (postdiv + 1);
99 +
100 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
101 + QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
102 +
103 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
104 + ddr_rate = ref_rate;
105 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
106 + ddr_rate = cpu_pll / (postdiv + 1);
107 + else
108 + ddr_rate = ddr_pll / (postdiv + 1);
109 +
110 + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
111 + QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
112 +
113 + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
114 + ahb_rate = ref_rate;
115 + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
116 + ahb_rate = ddr_pll / (postdiv + 1);
117 + else
118 + ahb_rate = cpu_pll / (postdiv + 1);
119 +
120 + ath79_add_sys_clkdev("ref", ref_rate);
121 + ath79_add_sys_clkdev("cpu", cpu_rate);
122 + ath79_add_sys_clkdev("ddr", ddr_rate);
123 + ath79_add_sys_clkdev("ahb", ahb_rate);
124 +
125 + clk_add_alias("wdt", NULL, "ref", NULL);
126 + clk_add_alias("uart", NULL, "ref", NULL);
127 +}
128 +
129 void __init ath79_clocks_init(void)
130 {
131 if (soc_is_ar71xx())
132 @@ -537,6 +631,8 @@ void __init ath79_clocks_init(void)
133 qca953x_clocks_init();
134 else if (soc_is_qca955x())
135 qca955x_clocks_init();
136 + else if (soc_is_qca956x() || soc_is_tp9343())
137 + qca956x_clocks_init();
138 else
139 BUG();
140 }
141 Index: linux-4.14.61/arch/mips/ath79/common.c
142 ===================================================================
143 --- linux-4.14.61.orig/arch/mips/ath79/common.c
144 +++ linux-4.14.61/arch/mips/ath79/common.c
145 @@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
146 reg = QCA953X_RESET_REG_RESET_MODULE;
147 else if (soc_is_qca955x())
148 reg = QCA955X_RESET_REG_RESET_MODULE;
149 + else if (soc_is_qca956x() || soc_is_tp9343())
150 + reg = QCA956X_RESET_REG_RESET_MODULE;
151 else
152 panic("Reset register not defined for this SOC");
153
154 @@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
155 reg = QCA953X_RESET_REG_RESET_MODULE;
156 else if (soc_is_qca955x())
157 reg = QCA955X_RESET_REG_RESET_MODULE;
158 + else if (soc_is_qca956x() || soc_is_tp9343())
159 + reg = QCA956X_RESET_REG_RESET_MODULE;
160 else
161 panic("Reset register not defined for this SOC");
162
163 @@ -163,6 +167,8 @@ u32 ath79_device_reset_get(u32 mask)
164 reg = AR933X_RESET_REG_RESET_MODULE;
165 else if (soc_is_ar934x())
166 reg = AR934X_RESET_REG_RESET_MODULE;
167 + else if (soc_is_qca956x() || soc_is_tp9343())
168 + reg = QCA956X_RESET_REG_RESET_MODULE;
169 else
170 BUG();
171
172 Index: linux-4.14.61/arch/mips/ath79/dev-common.c
173 ===================================================================
174 --- linux-4.14.61.orig/arch/mips/ath79/dev-common.c
175 +++ linux-4.14.61/arch/mips/ath79/dev-common.c
176 @@ -95,7 +95,9 @@ void __init ath79_register_uart(void)
177 soc_is_ar913x() ||
178 soc_is_ar934x() ||
179 soc_is_qca953x() ||
180 - soc_is_qca955x()) {
181 + soc_is_qca955x() ||
182 + soc_is_qca956x() ||
183 + soc_is_tp9343()) {
184 ath79_uart_data[0].uartclk = uart_clk_rate;
185 platform_device_register(&ath79_uart_device);
186 } else if (soc_is_ar933x()) {
187 @@ -164,6 +166,9 @@ void __init ath79_gpio_init(void)
188 } else if (soc_is_qca955x()) {
189 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
190 ath79_gpio_pdata.oe_inverted = 1;
191 + } else if (soc_is_qca956x() || soc_is_tp9343()) {
192 + ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
193 + ath79_gpio_pdata.oe_inverted = 1;
194 } else {
195 BUG();
196 }
197 Index: linux-4.14.61/arch/mips/ath79/dev-usb.c
198 ===================================================================
199 --- linux-4.14.61.orig/arch/mips/ath79/dev-usb.c
200 +++ linux-4.14.61/arch/mips/ath79/dev-usb.c
201 @@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
202 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
203 }
204
205 +static void __init qca956x_usb_setup(void)
206 +{
207 + ath79_usb_register("ehci-platform", 0,
208 + QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
209 + ATH79_IP3_IRQ(0),
210 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
211 +
212 + ath79_usb_register("ehci-platform", 1,
213 + QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
214 + ATH79_IP3_IRQ(1),
215 + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
216 +}
217 +
218 void __init ath79_register_usb(void)
219 {
220 if (soc_is_ar71xx())
221 @@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
222 qca953x_usb_setup();
223 else if (soc_is_qca955x())
224 qca955x_usb_setup();
225 + else if (soc_is_qca956x())
226 + qca956x_usb_setup();
227 else
228 BUG();
229 }
230 Index: linux-4.14.61/arch/mips/ath79/dev-wmac.c
231 ===================================================================
232 --- linux-4.14.61.orig/arch/mips/ath79/dev-wmac.c
233 +++ linux-4.14.61/arch/mips/ath79/dev-wmac.c
234 @@ -195,6 +195,26 @@ static void qca955x_wmac_setup(void)
235 #define AR93XX_OTP_READ_DATA \
236 (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
237
238 +static void qca956x_wmac_setup(void)
239 +{
240 + u32 t;
241 +
242 + ath79_wmac_device.name = "qca956x_wmac";
243 +
244 + ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
245 + ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
246 + ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
247 + ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
248 +
249 + t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
250 + if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
251 + ath79_wmac_data.is_clk_25mhz = false;
252 + else
253 + ath79_wmac_data.is_clk_25mhz = true;
254 +
255 + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
256 +}
257 +
258 static bool __init
259 ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
260 {
261 @@ -398,6 +418,8 @@ void __init ath79_register_wmac(u8 *cal_
262 qca953x_wmac_setup();
263 else if (soc_is_qca955x())
264 qca955x_wmac_setup();
265 + else if (soc_is_qca956x() || soc_is_tp9343())
266 + qca956x_wmac_setup();
267 else
268 BUG();
269
270 Index: linux-4.14.61/arch/mips/ath79/early_printk.c
271 ===================================================================
272 --- linux-4.14.61.orig/arch/mips/ath79/early_printk.c
273 +++ linux-4.14.61/arch/mips/ath79/early_printk.c
274 @@ -120,6 +120,8 @@ static void prom_putchar_init(void)
275 case REV_ID_MAJOR_QCA9533_V2:
276 case REV_ID_MAJOR_QCA9556:
277 case REV_ID_MAJOR_QCA9558:
278 + case REV_ID_MAJOR_TP9343:
279 + case REV_ID_MAJOR_QCA956X:
280 _prom_putchar = prom_putchar_ar71xx;
281 break;
282
283 Index: linux-4.14.61/arch/mips/ath79/gpio.c
284 ===================================================================
285 --- linux-4.14.61.orig/arch/mips/ath79/gpio.c
286 +++ linux-4.14.61/arch/mips/ath79/gpio.c
287 @@ -31,7 +31,10 @@ static void __iomem *ath79_gpio_get_func
288 soc_is_ar913x() ||
289 soc_is_ar933x())
290 reg = AR71XX_GPIO_REG_FUNC;
291 - else if (soc_is_ar934x() || soc_is_qca953x())
292 + else if (soc_is_ar934x() ||
293 + soc_is_qca953x() ||
294 + soc_is_qca956x() ||
295 + soc_is_tp9343())
296 reg = AR934X_GPIO_REG_FUNC;
297 else
298 BUG();
299 @@ -64,7 +67,7 @@ void __init ath79_gpio_output_select(uns
300 unsigned int reg;
301 u32 t, s;
302
303 - BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
304 + BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
305
306 if (gpio >= AR934X_GPIO_COUNT)
307 return;
308 Index: linux-4.14.61/arch/mips/ath79/irq.c
309 ===================================================================
310 --- linux-4.14.61.orig/arch/mips/ath79/irq.c
311 +++ linux-4.14.61/arch/mips/ath79/irq.c
312 @@ -156,6 +156,87 @@ static void qca955x_irq_init(void)
313 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
314 }
315
316 +static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
317 +{
318 + u32 status;
319 +
320 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
321 + status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
322 +
323 + if (status == 0) {
324 + spurious_interrupt();
325 + return;
326 + }
327 +
328 + if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
329 + /* TODO: flush DDR? */
330 + generic_handle_irq(ATH79_IP2_IRQ(0));
331 + }
332 +
333 + if (status & QCA956X_EXT_INT_WMAC_ALL) {
334 + /* TODO: flsuh DDR? */
335 + generic_handle_irq(ATH79_IP2_IRQ(1));
336 + }
337 +}
338 +
339 +static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
340 +{
341 + u32 status;
342 +
343 + status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
344 + status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
345 + QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
346 +
347 + if (status == 0) {
348 + spurious_interrupt();
349 + return;
350 + }
351 +
352 + if (status & QCA956X_EXT_INT_USB1) {
353 + /* TODO: flush DDR? */
354 + generic_handle_irq(ATH79_IP3_IRQ(0));
355 + }
356 +
357 + if (status & QCA956X_EXT_INT_USB2) {
358 + /* TODO: flush DDR? */
359 + generic_handle_irq(ATH79_IP3_IRQ(1));
360 + }
361 +
362 + if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
363 + /* TODO: flush DDR? */
364 + generic_handle_irq(ATH79_IP3_IRQ(2));
365 + }
366 +}
367 +
368 +static void qca956x_enable_timer_cb(void) {
369 + u32 misc;
370 +
371 + misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
372 + misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
373 + ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
374 +}
375 +
376 +static void qca956x_irq_init(void)
377 +{
378 + int i;
379 +
380 + for (i = ATH79_IP2_IRQ_BASE;
381 + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
382 + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
383 +
384 + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
385 +
386 + for (i = ATH79_IP3_IRQ_BASE;
387 + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
388 + irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
389 +
390 + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
391 +
392 + /* QCA956x timer init workaround has to be applied right before setting
393 + * up the clock. Else, there will be no jiffies */
394 + late_time_init = &qca956x_enable_timer_cb;
395 +}
396 +
397 void __init arch_init_irq(void)
398 {
399 unsigned irq_wb_chan2 = -1;
400 @@ -183,7 +264,9 @@ void __init arch_init_irq(void)
401 soc_is_ar933x() ||
402 soc_is_ar934x() ||
403 soc_is_qca953x() ||
404 - soc_is_qca955x())
405 + soc_is_qca955x() ||
406 + soc_is_qca956x() ||
407 + soc_is_tp9343())
408 misc_is_ar71xx = false;
409 else
410 BUG();
411 @@ -197,4 +280,6 @@ void __init arch_init_irq(void)
412 qca953x_irq_init();
413 else if (soc_is_qca955x())
414 qca955x_irq_init();
415 + else if (soc_is_qca956x() || soc_is_tp9343())
416 + qca956x_irq_init();
417 }
418 Index: linux-4.14.61/arch/mips/ath79/pci.c
419 ===================================================================
420 --- linux-4.14.61.orig/arch/mips/ath79/pci.c
421 +++ linux-4.14.61/arch/mips/ath79/pci.c
422 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
423 },
424 };
425
426 +static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
427 + {
428 + .bus = 0,
429 + .slot = 0,
430 + .pin = 1,
431 + .irq = ATH79_PCI_IRQ(0),
432 + },
433 + {
434 + .bus = 1,
435 + .slot = 0,
436 + .pin = 1,
437 + .irq = ATH79_PCI_IRQ(1),
438 + },
439 +};
440 +
441 int pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
442 {
443 int irq = -1;
444 @@ -86,6 +101,9 @@ int pcibios_map_irq(const struct pci_dev
445 } else if (soc_is_qca955x()) {
446 ath79_pci_irq_map = qca955x_pci_irq_map;
447 ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
448 + } else if (soc_is_qca956x()) {
449 + ath79_pci_irq_map = qca956x_pci_irq_map;
450 + ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
451 } else {
452 pr_crit("pci %s: invalid irq map\n",
453 pci_name((struct pci_dev *) dev));
454 @@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
455 QCA955X_PCI_MEM_SIZE,
456 1,
457 ATH79_IP3_IRQ(2));
458 + } else if (soc_is_qca956x()) {
459 + pdev = ath79_register_pci_ar724x(0,
460 + QCA956X_PCI_CFG_BASE1,
461 + QCA956X_PCI_CTRL_BASE1,
462 + QCA956X_PCI_CRP_BASE1,
463 + QCA956X_PCI_MEM_BASE1,
464 + QCA956X_PCI_MEM_SIZE,
465 + 1,
466 + ATH79_IP3_IRQ(2));
467 } else {
468 /* No PCI support */
469 return -ENODEV;
470 Index: linux-4.14.61/arch/mips/ath79/setup.c
471 ===================================================================
472 --- linux-4.14.61.orig/arch/mips/ath79/setup.c
473 +++ linux-4.14.61/arch/mips/ath79/setup.c
474 @@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
475 rev = id & QCA955X_REV_ID_REVISION_MASK;
476 break;
477
478 + case REV_ID_MAJOR_QCA956X:
479 + ath79_soc = ATH79_SOC_QCA956X;
480 + chip = "956X";
481 + rev = id & QCA956X_REV_ID_REVISION_MASK;
482 + break;
483 +
484 + case REV_ID_MAJOR_TP9343:
485 + ath79_soc = ATH79_SOC_TP9343;
486 + chip = "9343";
487 + rev = id & QCA956X_REV_ID_REVISION_MASK;
488 + break;
489 +
490 default:
491 panic("ath79: unknown SoC, id:0x%08x", id);
492 }
493 @@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
494 if (ver == 1)
495 ath79_soc_rev = rev;
496
497 - if (soc_is_qca953x() || soc_is_qca955x())
498 + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
499 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
500 chip, ver, rev);
501 + else if (soc_is_tp9343())
502 + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
503 + chip, rev);
504 else
505 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
506 pr_info("SoC: %s\n", ath79_sys_type);
507 Index: linux-4.14.61/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
508 ===================================================================
509 --- linux-4.14.61.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
510 +++ linux-4.14.61/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
511 @@ -143,6 +143,23 @@
512 #define QCA955X_NFC_BASE 0x1b800200
513 #define QCA955X_NFC_SIZE 0xb8
514
515 +#define QCA956X_PCI_MEM_BASE1 0x12000000
516 +#define QCA956X_PCI_MEM_SIZE 0x02000000
517 +#define QCA956X_PCI_CFG_BASE1 0x16000000
518 +#define QCA956X_PCI_CFG_SIZE 0x1000
519 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
520 +#define QCA956X_PCI_CRP_SIZE 0x1000
521 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
522 +#define QCA956X_PCI_CTRL_SIZE 0x100
523 +
524 +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
525 +#define QCA956X_WMAC_SIZE 0x20000
526 +#define QCA956X_EHCI0_BASE 0x1b000000
527 +#define QCA956X_EHCI1_BASE 0x1b400000
528 +#define QCA956X_EHCI_SIZE 0x200
529 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
530 +#define QCA956X_GMAC_SIZE 0x64
531 +
532 #define AR9300_OTP_BASE 0x14000
533 #define AR9300_OTP_STATUS 0x15f18
534 #define AR9300_OTP_STATUS_TYPE 0x7
535 @@ -152,6 +169,13 @@
536 #define AR9300_OTP_READ_DATA 0x15f1c
537
538 /*
539 + * Hidden Registers
540 + */
541 +#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
542 +#define QCA956X_DAM_RESET_SIZE 0x4
543 +#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
544 +
545 +/*
546 * DDR_CTRL block
547 */
548 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
549 @@ -385,6 +409,49 @@
550 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
551 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
552
553 +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
554 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
555 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
556 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
557 +#define QCA956X_PLL_CLK_CTRL_REG 0x10
558 +
559 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
560 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
561 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
562 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
563 +
564 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
565 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
566 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
567 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
568 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
569 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
570 +
571 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
572 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
573 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
574 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
575 +
576 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
577 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
578 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
579 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
580 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
581 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
582 +
583 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
584 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
585 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
586 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
587 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
588 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
589 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
590 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
591 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
592 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
593 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
594 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
595 +
596 /*
597 * USB_CONFIG block
598 */
599 @@ -432,6 +499,11 @@
600 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
601 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
602
603 +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
604 +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
605 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
606 +
607 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
608 #define MISC_INT_ETHSW BIT(12)
609 #define MISC_INT_TIMER4 BIT(10)
610 #define MISC_INT_TIMER3 BIT(9)
611 @@ -606,6 +678,8 @@
612
613 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
614
615 +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
616 +
617 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
618 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
619 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
620 @@ -673,6 +747,37 @@
621 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
622 QCA955X_EXT_INT_PCIE_RC2_INT3)
623
624 +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
625 +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
626 +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
627 +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
628 +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
629 +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
630 +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
631 +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
632 +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
633 +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
634 +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
635 +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
636 +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
637 +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
638 +#define QCA956X_EXT_INT_USB1 BIT(24)
639 +#define QCA956X_EXT_INT_USB2 BIT(28)
640 +
641 +#define QCA956X_EXT_INT_WMAC_ALL \
642 + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
643 + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
644 +
645 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
646 + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
647 + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
648 + QCA956X_EXT_INT_PCIE_RC1_INT3)
649 +
650 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
651 + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
652 + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
653 + QCA956X_EXT_INT_PCIE_RC2_INT3)
654 +
655 #define REV_ID_MAJOR_MASK 0xfff0
656 #define REV_ID_MAJOR_AR71XX 0x00a0
657 #define REV_ID_MAJOR_AR913X 0x00b0
658 @@ -688,6 +793,8 @@
659 #define REV_ID_MAJOR_QCA9533_V2 0x0160
660 #define REV_ID_MAJOR_QCA9556 0x0130
661 #define REV_ID_MAJOR_QCA9558 0x1130
662 +#define REV_ID_MAJOR_TP9343 0x0150
663 +#define REV_ID_MAJOR_QCA956X 0x1150
664
665 #define AR71XX_REV_ID_MINOR_MASK 0x3
666 #define AR71XX_REV_ID_MINOR_AR7130 0x0
667 @@ -712,6 +819,8 @@
668
669 #define QCA955X_REV_ID_REVISION_MASK 0xf
670
671 +#define QCA956X_REV_ID_REVISION_MASK 0xf
672 +
673 /*
674 * SPI block
675 */
676 @@ -784,6 +893,19 @@
677 #define QCA955X_GPIO_REG_OUT_FUNC5 0x40
678 #define QCA955X_GPIO_REG_FUNC 0x6c
679
680 +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
681 +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
682 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
683 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
684 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
685 +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
686 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
687 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
688 +#define QCA956X_GPIO_REG_FUNC 0x6c
689 +
690 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
691 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
692 +
693 #define AR71XX_GPIO_COUNT 16
694 #define AR7240_GPIO_COUNT 18
695 #define AR7241_GPIO_COUNT 20
696 @@ -792,6 +914,7 @@
697 #define AR934X_GPIO_COUNT 23
698 #define QCA953X_GPIO_COUNT 18
699 #define QCA955X_GPIO_COUNT 24
700 +#define QCA956X_GPIO_COUNT 23
701
702 /*
703 * SRIF block
704 Index: linux-4.14.61/arch/mips/include/asm/mach-ath79/ath79.h
705 ===================================================================
706 --- linux-4.14.61.orig/arch/mips/include/asm/mach-ath79/ath79.h
707 +++ linux-4.14.61/arch/mips/include/asm/mach-ath79/ath79.h
708 @@ -35,6 +35,8 @@ enum ath79_soc_type {
709 ATH79_SOC_QCA9533,
710 ATH79_SOC_QCA9556,
711 ATH79_SOC_QCA9558,
712 + ATH79_SOC_TP9343,
713 + ATH79_SOC_QCA956X,
714 };
715
716 extern enum ath79_soc_type ath79_soc;
717 @@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
718 return soc_is_qca9556() || soc_is_qca9558();
719 }
720
721 +static inline int soc_is_tp9343(void)
722 +{
723 + return ath79_soc == ATH79_SOC_TP9343;
724 +}
725 +
726 +static inline int soc_is_qca9561(void)
727 +{
728 + return ath79_soc == ATH79_SOC_QCA956X;
729 +}
730 +
731 +static inline int soc_is_qca9563(void)
732 +{
733 + return ath79_soc == ATH79_SOC_QCA956X;
734 +}
735 +
736 +static inline int soc_is_qca956x(void)
737 +{
738 + return soc_is_qca9561() || soc_is_qca9563();
739 +}
740 +
741 void ath79_ddr_wb_flush(unsigned int reg);
742 void ath79_ddr_set_pci_windows(void);
743
OpenWrt Source Repository