target/linux/ar71xx/patches-4.4/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch

   1 From 0f15814bcdf59f10b708a3fba636acb089e9a4f1 Mon Sep 17 00:00:00 2001
   2 From: Mathias Kresin <dev@kresin.me>
   3 Date: Thu, 30 Mar 2017 15:34:39 +0200
   4 Subject: [PATCH] MIPS: ath79: fix AR724X_PLL_REG_PCIE_CONFIG offset
   5
   6 According to the QCA u-boot source the "PCIE Phase Lock Loop
   7 Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
   8 QCA955X and QCA956X at offset 0x10.
   9
  10 Since the PCIE PLL config register is only defined for the AR724x fix
  11 only this value. The value is wrong since the day it was added and isn't
  12 yet used by any driver.
  13
  14 Signed-off-by: Mathias Kresin <dev@kresin.me>
  15 ---
  16  arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +-
  17  1 file changed, 1 insertion(+), 1 deletion(-)
  18
  19 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  20 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  21 @@ -167,7 +167,7 @@
  22  #define AR71XX_AHB_DIV_MASK            0x7
  23
  24  #define AR724X_PLL_REG_CPU_CONFIG      0x00
  25 -#define AR724X_PLL_REG_PCIE_CONFIG     0x18
  26 +#define AR724X_PLL_REG_PCIE_CONFIG     0x10
  27
  28  #define AR724X_PLL_FB_SHIFT            0
  29  #define AR724X_PLL_FB_MASK             0x3ff