0dc73a8b5b930d39bcb80449e9a103924721d41f
[openwrt/openwrt.git] / target / linux / ar71xx / patches-4.4 / 461-spi-ath79-add-fast-flash-read.patch
1 --- a/drivers/spi/spi-ath79.c
2 +++ b/drivers/spi/spi-ath79.c
3 @@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7
4 /* save CTRL register */
5 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
6 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
7 -
8 - /* TODO: setup speed? */
9 - ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
10 }
11
12 static void ath79_spi_disable(struct ath79_spi *sp)
13 @@ -205,6 +202,33 @@ static u32 ath79_spi_txrx_mode0(struct s
14 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
15 }
16
17 +static int ath79_spi_read_flash_data(struct spi_device *spi,
18 + struct spi_flash_read_message *msg)
19 +{
20 + struct ath79_spi *sp = ath79_spidev_to_sp(spi);
21 +
22 + if (msg->addr_width > 3)
23 + return -EOPNOTSUPP;
24 +
25 + if (spi->chip_select || gpio_is_valid(spi->cs_gpio))
26 + return -EOPNOTSUPP;
27 +
28 + /* disable GPIO mode */
29 + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
30 +
31 + memcpy_fromio(msg->buf, sp->base + msg->from, msg->len);
32 +
33 + /* enable GPIO mode */
34 + ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
35 +
36 + /* restore IOC register */
37 + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
38 +
39 + msg->retlen = msg->len;
40 +
41 + return 0;
42 +}
43 +
44 static int ath79_spi_probe(struct platform_device *pdev)
45 {
46 struct spi_master *master;
47 @@ -234,6 +258,7 @@ static int ath79_spi_probe(struct platfo
48 master->num_chipselect = pdata->num_chipselect;
49 master->cs_gpios = pdata->cs_gpios;
50 }
51 + master->spi_flash_read = ath79_spi_read_flash_data;
52
53 sp->bitbang.master = master;
54 sp->bitbang.chipselect = ath79_spi_chipselect;